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1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/display/drm_dp_helper.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_encoder.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_modeset_helper_vtables.h>
38#include <linux/i2c.h>
39#include <linux/i2c-algo-bit.h>
40
41struct drm_fb_helper;
42struct drm_fb_helper_surface_size;
43
44struct edid;
45struct drm_edid;
46struct radeon_bo;
47struct radeon_device;
48
49#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
50#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
51#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
52
53#define RADEON_MAX_HPD_PINS 7
54#define RADEON_MAX_CRTCS 6
55#define RADEON_MAX_AFMT_BLOCKS 7
56
57enum radeon_rmx_type {
58 RMX_OFF,
59 RMX_FULL,
60 RMX_CENTER,
61 RMX_ASPECT
62};
63
64enum radeon_tv_std {
65 TV_STD_NTSC,
66 TV_STD_PAL,
67 TV_STD_PAL_M,
68 TV_STD_PAL_60,
69 TV_STD_NTSC_J,
70 TV_STD_SCART_PAL,
71 TV_STD_SECAM,
72 TV_STD_PAL_CN,
73 TV_STD_PAL_N,
74};
75
76enum radeon_underscan_type {
77 UNDERSCAN_OFF,
78 UNDERSCAN_ON,
79 UNDERSCAN_AUTO,
80};
81
82enum radeon_hpd_id {
83 RADEON_HPD_1 = 0,
84 RADEON_HPD_2,
85 RADEON_HPD_3,
86 RADEON_HPD_4,
87 RADEON_HPD_5,
88 RADEON_HPD_6,
89 RADEON_HPD_NONE = 0xff,
90};
91
92enum radeon_output_csc {
93 RADEON_OUTPUT_CSC_BYPASS = 0,
94 RADEON_OUTPUT_CSC_TVRGB = 1,
95 RADEON_OUTPUT_CSC_YCBCR601 = 2,
96 RADEON_OUTPUT_CSC_YCBCR709 = 3,
97};
98
99#define RADEON_MAX_I2C_BUS 16
100
101/* radeon gpio-based i2c
102 * 1. "mask" reg and bits
103 * grabs the gpio pins for software use
104 * 0=not held 1=held
105 * 2. "a" reg and bits
106 * output pin value
107 * 0=low 1=high
108 * 3. "en" reg and bits
109 * sets the pin direction
110 * 0=input 1=output
111 * 4. "y" reg and bits
112 * input pin value
113 * 0=low 1=high
114 */
115struct radeon_i2c_bus_rec {
116 bool valid;
117 /* id used by atom */
118 uint8_t i2c_id;
119 /* id used by atom */
120 enum radeon_hpd_id hpd;
121 /* can be used with hw i2c engine */
122 bool hw_capable;
123 /* uses multi-media i2c engine */
124 bool mm_i2c;
125 /* regs and bits */
126 uint32_t mask_clk_reg;
127 uint32_t mask_data_reg;
128 uint32_t a_clk_reg;
129 uint32_t a_data_reg;
130 uint32_t en_clk_reg;
131 uint32_t en_data_reg;
132 uint32_t y_clk_reg;
133 uint32_t y_data_reg;
134 uint32_t mask_clk_mask;
135 uint32_t mask_data_mask;
136 uint32_t a_clk_mask;
137 uint32_t a_data_mask;
138 uint32_t en_clk_mask;
139 uint32_t en_data_mask;
140 uint32_t y_clk_mask;
141 uint32_t y_data_mask;
142};
143
144struct radeon_tmds_pll {
145 uint32_t freq;
146 uint32_t value;
147};
148
149#define RADEON_MAX_BIOS_CONNECTOR 16
150
151/* pll flags */
152#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
153#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
154#define RADEON_PLL_USE_REF_DIV (1 << 2)
155#define RADEON_PLL_LEGACY (1 << 3)
156#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
157#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
158#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
159#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
160#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
161#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
162#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
163#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
164#define RADEON_PLL_USE_POST_DIV (1 << 12)
165#define RADEON_PLL_IS_LCD (1 << 13)
166#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
167
168struct radeon_pll {
169 /* reference frequency */
170 uint32_t reference_freq;
171
172 /* fixed dividers */
173 uint32_t reference_div;
174 uint32_t post_div;
175
176 /* pll in/out limits */
177 uint32_t pll_in_min;
178 uint32_t pll_in_max;
179 uint32_t pll_out_min;
180 uint32_t pll_out_max;
181 uint32_t lcd_pll_out_min;
182 uint32_t lcd_pll_out_max;
183 uint32_t best_vco;
184
185 /* divider limits */
186 uint32_t min_ref_div;
187 uint32_t max_ref_div;
188 uint32_t min_post_div;
189 uint32_t max_post_div;
190 uint32_t min_feedback_div;
191 uint32_t max_feedback_div;
192 uint32_t min_frac_feedback_div;
193 uint32_t max_frac_feedback_div;
194
195 /* flags for the current clock */
196 uint32_t flags;
197
198 /* pll id */
199 uint32_t id;
200};
201
202struct radeon_i2c_chan {
203 struct i2c_adapter adapter;
204 struct drm_device *dev;
205 struct i2c_algo_bit_data bit;
206 struct radeon_i2c_bus_rec rec;
207 struct drm_dp_aux aux;
208 bool has_aux;
209 struct mutex mutex;
210};
211
212/* mostly for macs, but really any system without connector tables */
213enum radeon_connector_table {
214 CT_NONE = 0,
215 CT_GENERIC,
216 CT_IBOOK,
217 CT_POWERBOOK_EXTERNAL,
218 CT_POWERBOOK_INTERNAL,
219 CT_POWERBOOK_VGA,
220 CT_MINI_EXTERNAL,
221 CT_MINI_INTERNAL,
222 CT_IMAC_G5_ISIGHT,
223 CT_EMAC,
224 CT_RN50_POWER,
225 CT_MAC_X800,
226 CT_MAC_G5_9600,
227 CT_SAM440EP,
228 CT_MAC_G4_SILVER
229};
230
231enum radeon_dvo_chip {
232 DVO_SIL164,
233 DVO_SIL1178,
234};
235
236struct radeon_afmt {
237 bool enabled;
238 int offset;
239 bool last_buffer_filled_status;
240 int id;
241};
242
243struct radeon_mode_info {
244 struct atom_context *atom_context;
245 struct card_info *atom_card_info;
246 enum radeon_connector_table connector_table;
247 bool mode_config_initialized;
248 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
249 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
250 /* DVI-I properties */
251 struct drm_property *coherent_mode_property;
252 /* DAC enable load detect */
253 struct drm_property *load_detect_property;
254 /* TV standard */
255 struct drm_property *tv_std_property;
256 /* legacy TMDS PLL detect */
257 struct drm_property *tmds_pll_property;
258 /* underscan */
259 struct drm_property *underscan_property;
260 struct drm_property *underscan_hborder_property;
261 struct drm_property *underscan_vborder_property;
262 /* audio */
263 struct drm_property *audio_property;
264 /* FMT dithering */
265 struct drm_property *dither_property;
266 /* Output CSC */
267 struct drm_property *output_csc_property;
268 /* hardcoded DFP edid from BIOS */
269 const struct drm_edid *bios_hardcoded_edid;
270
271 /* firmware flags */
272 u16 firmware_flags;
273 /* pointer to backlight encoder */
274 struct radeon_encoder *bl_encoder;
275
276 /* bitmask for active encoder frontends */
277 uint32_t active_encoders;
278};
279
280#define RADEON_MAX_BL_LEVEL 0xFF
281
282struct radeon_backlight_privdata {
283 struct radeon_encoder *encoder;
284 uint8_t negative;
285};
286
287#define MAX_H_CODE_TIMING_LEN 32
288#define MAX_V_CODE_TIMING_LEN 32
289
290/* need to store these as reading
291 back code tables is excessive */
292struct radeon_tv_regs {
293 uint32_t tv_uv_adr;
294 uint32_t timing_cntl;
295 uint32_t hrestart;
296 uint32_t vrestart;
297 uint32_t frestart;
298 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
299 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
300};
301
302struct radeon_atom_ss {
303 uint16_t percentage;
304 uint16_t percentage_divider;
305 uint8_t type;
306 uint16_t step;
307 uint8_t delay;
308 uint8_t range;
309 uint8_t refdiv;
310 /* asic_ss */
311 uint16_t rate;
312 uint16_t amount;
313};
314
315enum radeon_flip_status {
316 RADEON_FLIP_NONE,
317 RADEON_FLIP_PENDING,
318 RADEON_FLIP_SUBMITTED
319};
320
321struct radeon_crtc {
322 struct drm_crtc base;
323 int crtc_id;
324 bool enabled;
325 bool can_tile;
326 bool cursor_out_of_bounds;
327 uint32_t crtc_offset;
328 struct drm_gem_object *cursor_bo;
329 uint64_t cursor_addr;
330 int cursor_x;
331 int cursor_y;
332 int cursor_hot_x;
333 int cursor_hot_y;
334 int cursor_width;
335 int cursor_height;
336 int max_cursor_width;
337 int max_cursor_height;
338 uint32_t legacy_display_base_addr;
339 enum radeon_rmx_type rmx_type;
340 u8 h_border;
341 u8 v_border;
342 fixed20_12 vsc;
343 fixed20_12 hsc;
344 struct drm_display_mode native_mode;
345 int pll_id;
346 /* page flipping */
347 struct workqueue_struct *flip_queue;
348 struct radeon_flip_work *flip_work;
349 enum radeon_flip_status flip_status;
350 /* pll sharing */
351 struct radeon_atom_ss ss;
352 bool ss_enabled;
353 u32 adjusted_clock;
354 int bpc;
355 u32 pll_reference_div;
356 u32 pll_post_div;
357 u32 pll_flags;
358 struct drm_encoder *encoder;
359 struct drm_connector *connector;
360 /* for dpm */
361 u32 line_time;
362 u32 wm_low;
363 u32 wm_high;
364 u32 lb_vblank_lead_lines;
365 struct drm_display_mode hw_mode;
366 enum radeon_output_csc output_csc;
367};
368
369struct radeon_encoder_primary_dac {
370 /* legacy primary dac */
371 uint32_t ps2_pdac_adj;
372};
373
374struct radeon_encoder_lvds {
375 /* legacy lvds */
376 uint16_t panel_vcc_delay;
377 uint8_t panel_pwr_delay;
378 uint8_t panel_digon_delay;
379 uint8_t panel_blon_delay;
380 uint16_t panel_ref_divider;
381 uint8_t panel_post_divider;
382 uint16_t panel_fb_divider;
383 bool use_bios_dividers;
384 uint32_t lvds_gen_cntl;
385 /* panel mode */
386 struct drm_display_mode native_mode;
387 struct backlight_device *bl_dev;
388 int dpms_mode;
389 uint8_t backlight_level;
390};
391
392struct radeon_encoder_tv_dac {
393 /* legacy tv dac */
394 uint32_t ps2_tvdac_adj;
395 uint32_t ntsc_tvdac_adj;
396 uint32_t pal_tvdac_adj;
397
398 int h_pos;
399 int v_pos;
400 int h_size;
401 int supported_tv_stds;
402 bool tv_on;
403 enum radeon_tv_std tv_std;
404 struct radeon_tv_regs tv;
405};
406
407struct radeon_encoder_int_tmds {
408 /* legacy int tmds */
409 struct radeon_tmds_pll tmds_pll[4];
410};
411
412struct radeon_encoder_ext_tmds {
413 /* tmds over dvo */
414 struct radeon_i2c_chan *i2c_bus;
415 uint8_t slave_addr;
416 enum radeon_dvo_chip dvo_chip;
417};
418
419/* spread spectrum */
420struct radeon_encoder_atom_dig {
421 bool linkb;
422 /* atom dig */
423 bool coherent_mode;
424 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
425 /* atom lvds/edp */
426 uint32_t lcd_misc;
427 uint16_t panel_pwr_delay;
428 uint32_t lcd_ss_id;
429 /* panel mode */
430 struct drm_display_mode native_mode;
431 struct backlight_device *bl_dev;
432 int dpms_mode;
433 uint8_t backlight_level;
434 int panel_mode;
435 struct radeon_afmt *afmt;
436 struct r600_audio_pin *pin;
437};
438
439struct radeon_encoder_atom_dac {
440 enum radeon_tv_std tv_std;
441};
442
443struct radeon_encoder {
444 struct drm_encoder base;
445 uint32_t encoder_enum;
446 uint32_t encoder_id;
447 uint32_t devices;
448 uint32_t active_device;
449 uint32_t flags;
450 uint32_t pixel_clock;
451 enum radeon_rmx_type rmx_type;
452 enum radeon_underscan_type underscan_type;
453 uint32_t underscan_hborder;
454 uint32_t underscan_vborder;
455 struct drm_display_mode native_mode;
456 void *enc_priv;
457 int audio_polling_active;
458 bool is_ext_encoder;
459 u16 caps;
460 struct radeon_audio_funcs *audio;
461 enum radeon_output_csc output_csc;
462 bool can_mst;
463 uint32_t offset;
464};
465
466struct radeon_connector_atom_dig {
467 uint32_t igp_lane_info;
468 /* displayport */
469 u8 dpcd[DP_RECEIVER_CAP_SIZE];
470 u8 dp_sink_type;
471 int dp_clock;
472 int dp_lane_count;
473 bool edp_on;
474};
475
476struct radeon_gpio_rec {
477 bool valid;
478 u8 id;
479 u32 reg;
480 u32 mask;
481 u32 shift;
482};
483
484struct radeon_hpd {
485 enum radeon_hpd_id hpd;
486 u8 plugged_state;
487 struct radeon_gpio_rec gpio;
488};
489
490struct radeon_router {
491 u32 router_id;
492 struct radeon_i2c_bus_rec i2c_info;
493 u8 i2c_addr;
494 /* i2c mux */
495 bool ddc_valid;
496 u8 ddc_mux_type;
497 u8 ddc_mux_control_pin;
498 u8 ddc_mux_state;
499 /* clock/data mux */
500 bool cd_valid;
501 u8 cd_mux_type;
502 u8 cd_mux_control_pin;
503 u8 cd_mux_state;
504};
505
506enum radeon_connector_audio {
507 RADEON_AUDIO_DISABLE = 0,
508 RADEON_AUDIO_ENABLE = 1,
509 RADEON_AUDIO_AUTO = 2
510};
511
512enum radeon_connector_dither {
513 RADEON_FMT_DITHER_DISABLE = 0,
514 RADEON_FMT_DITHER_ENABLE = 1,
515};
516
517struct radeon_connector {
518 struct drm_connector base;
519 uint32_t connector_id;
520 uint32_t devices;
521 struct radeon_i2c_chan *ddc_bus;
522 /* some systems have an hdmi and vga port with a shared ddc line */
523 bool shared_ddc;
524 bool use_digital;
525 /* we need to mind the EDID between detect
526 and get modes due to analog/digital/tvencoder */
527 struct edid *edid;
528 void *con_priv;
529 bool dac_load_detect;
530 bool detected_by_load; /* if the connection status was determined by load */
531 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
532 uint16_t connector_object_id;
533 struct radeon_hpd hpd;
534 struct radeon_router router;
535 struct radeon_i2c_chan *router_bus;
536 enum radeon_connector_audio audio;
537 enum radeon_connector_dither dither;
538 int pixelclock_for_modeset;
539};
540
541#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
542 ((em) == ATOM_ENCODER_MODE_DP_MST))
543
544struct atom_clock_dividers {
545 u32 post_div;
546 union {
547 struct {
548#ifdef __BIG_ENDIAN
549 u32 reserved : 6;
550 u32 whole_fb_div : 12;
551 u32 frac_fb_div : 14;
552#else
553 u32 frac_fb_div : 14;
554 u32 whole_fb_div : 12;
555 u32 reserved : 6;
556#endif
557 };
558 u32 fb_div;
559 };
560 u32 ref_div;
561 bool enable_post_div;
562 bool enable_dithen;
563 u32 vco_mode;
564 u32 real_clock;
565 /* added for CI */
566 u32 post_divider;
567 u32 flags;
568};
569
570struct atom_mpll_param {
571 union {
572 struct {
573#ifdef __BIG_ENDIAN
574 u32 reserved : 8;
575 u32 clkfrac : 12;
576 u32 clkf : 12;
577#else
578 u32 clkf : 12;
579 u32 clkfrac : 12;
580 u32 reserved : 8;
581#endif
582 };
583 u32 fb_div;
584 };
585 u32 post_div;
586 u32 bwcntl;
587 u32 dll_speed;
588 u32 vco_mode;
589 u32 yclk_sel;
590 u32 qdr;
591 u32 half_rate;
592};
593
594#define MEM_TYPE_GDDR5 0x50
595#define MEM_TYPE_GDDR4 0x40
596#define MEM_TYPE_GDDR3 0x30
597#define MEM_TYPE_DDR2 0x20
598#define MEM_TYPE_GDDR1 0x10
599#define MEM_TYPE_DDR3 0xb0
600#define MEM_TYPE_MASK 0xf0
601
602struct atom_memory_info {
603 u8 mem_vendor;
604 u8 mem_type;
605};
606
607#define MAX_AC_TIMING_ENTRIES 16
608
609struct atom_memory_clock_range_table {
610 u8 num_entries;
611 u8 rsv[3];
612 u32 mclk[MAX_AC_TIMING_ENTRIES];
613};
614
615#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
616#define VBIOS_MAX_AC_TIMING_ENTRIES 20
617
618struct atom_mc_reg_entry {
619 u32 mclk_max;
620 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
621};
622
623struct atom_mc_register_address {
624 u16 s1;
625 u8 pre_reg_data;
626};
627
628struct atom_mc_reg_table {
629 u8 last;
630 u8 num_entries;
631 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
632 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
633};
634
635#define MAX_VOLTAGE_ENTRIES 32
636
637struct atom_voltage_table_entry {
638 u16 value;
639 u32 smio_low;
640};
641
642struct atom_voltage_table {
643 u32 count;
644 u32 mask_low;
645 u32 phase_delay;
646 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
647};
648
649/* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
650#define DRM_SCANOUTPOS_VALID (1 << 0)
651#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
652#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
653#define USE_REAL_VBLANKSTART (1 << 30)
654#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
655
656extern void
657radeon_add_atom_connector(struct drm_device *dev,
658 uint32_t connector_id,
659 uint32_t supported_device,
660 int connector_type,
661 struct radeon_i2c_bus_rec *i2c_bus,
662 uint32_t igp_lane_info,
663 uint16_t connector_object_id,
664 struct radeon_hpd *hpd,
665 struct radeon_router *router);
666extern void
667radeon_add_legacy_connector(struct drm_device *dev,
668 uint32_t connector_id,
669 uint32_t supported_device,
670 int connector_type,
671 struct radeon_i2c_bus_rec *i2c_bus,
672 uint16_t connector_object_id,
673 struct radeon_hpd *hpd);
674extern uint32_t
675radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
676 uint8_t dac);
677extern void radeon_link_encoder_connector(struct drm_device *dev);
678
679extern enum radeon_tv_std
680radeon_combios_get_tv_info(struct radeon_device *rdev);
681extern enum radeon_tv_std
682radeon_atombios_get_tv_info(struct radeon_device *rdev);
683extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
684 u16 *vddc, u16 *vddci, u16 *mvdd);
685
686extern void
687radeon_combios_connected_scratch_regs(struct drm_connector *connector,
688 struct drm_encoder *encoder,
689 bool connected);
690extern void
691radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
692 struct drm_encoder *encoder,
693 bool connected);
694
695extern struct drm_connector *
696radeon_get_connector_for_encoder(struct drm_encoder *encoder);
697extern struct drm_connector *
698radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
699extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
700 u32 pixel_clock);
701
702extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
703extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
704extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
705extern int radeon_get_monitor_bpc(struct drm_connector *connector);
706
707extern void radeon_connector_hotplug(struct drm_connector *connector);
708extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
709 struct drm_display_mode *mode);
710extern void radeon_dp_set_link_config(struct drm_connector *connector,
711 const struct drm_display_mode *mode);
712extern void radeon_dp_link_train(struct drm_encoder *encoder,
713 struct drm_connector *connector);
714extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
715extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
716extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
717extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
718 struct drm_connector *connector);
719extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
720 u8 power_state);
721extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
722extern ssize_t
723radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
724
725extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
726extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
727extern void radeon_atom_encoder_init(struct radeon_device *rdev);
728extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
729extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
730 int action, uint8_t lane_num,
731 uint8_t lane_set);
732extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
733 int action, uint8_t lane_num,
734 uint8_t lane_set, int fe);
735extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
736extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
737void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
738
739extern void radeon_i2c_init(struct radeon_device *rdev);
740extern void radeon_i2c_fini(struct radeon_device *rdev);
741extern void radeon_combios_i2c_init(struct radeon_device *rdev);
742extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
743extern void radeon_i2c_add(struct radeon_device *rdev,
744 struct radeon_i2c_bus_rec *rec,
745 const char *name);
746extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
747 struct radeon_i2c_bus_rec *i2c_bus);
748extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
749 struct radeon_i2c_bus_rec *rec,
750 const char *name);
751extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
752extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
753 u8 slave_addr,
754 u8 addr,
755 u8 *val);
756extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
757 u8 slave_addr,
758 u8 addr,
759 u8 val);
760extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
761extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
762extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
763
764extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
765 struct radeon_atom_ss *ss,
766 int id);
767extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
768 struct radeon_atom_ss *ss,
769 int id, u32 clock);
770extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
771 u8 id);
772
773extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
774 uint64_t freq,
775 uint32_t *dot_clock_p,
776 uint32_t *fb_div_p,
777 uint32_t *frac_fb_div_p,
778 uint32_t *ref_div_p,
779 uint32_t *post_div_p);
780
781extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
782 u32 freq,
783 u32 *dot_clock_p,
784 u32 *fb_div_p,
785 u32 *frac_fb_div_p,
786 u32 *ref_div_p,
787 u32 *post_div_p);
788
789extern void radeon_setup_encoder_clones(struct drm_device *dev);
790
791struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
792struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
793struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
794struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
795struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
796extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
797extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
798extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
799extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
800extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
801extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
802
803extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
804extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
805 struct drm_framebuffer *old_fb);
806extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
807 struct drm_framebuffer *fb,
808 int x, int y,
809 enum mode_set_atomic state);
810extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
811 struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode,
813 int x, int y,
814 struct drm_framebuffer *old_fb);
815extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
816
817extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
818 struct drm_framebuffer *old_fb);
819extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
820 struct drm_framebuffer *fb,
821 int x, int y,
822 enum mode_set_atomic state);
823extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
824 struct drm_framebuffer *fb,
825 int x, int y, int atomic);
826extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
827 struct drm_file *file_priv,
828 uint32_t handle,
829 uint32_t width,
830 uint32_t height,
831 int32_t hot_x,
832 int32_t hot_y);
833extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
834 int x, int y);
835extern void radeon_cursor_reset(struct drm_crtc *crtc);
836
837extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
838 unsigned int flags, int *vpos, int *hpos,
839 ktime_t *stime, ktime_t *etime,
840 const struct drm_display_mode *mode);
841
842extern bool
843radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq,
844 int *vpos, int *hpos,
845 ktime_t *stime, ktime_t *etime,
846 const struct drm_display_mode *mode);
847
848extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
849extern struct edid *
850radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
851extern bool radeon_atom_get_clock_info(struct drm_device *dev);
852extern bool radeon_combios_get_clock_info(struct drm_device *dev);
853extern struct radeon_encoder_atom_dig *
854radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
855extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
856 struct radeon_encoder_int_tmds *tmds);
857extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
858 struct radeon_encoder_int_tmds *tmds);
859extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
860 struct radeon_encoder_int_tmds *tmds);
861extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
862 struct radeon_encoder_ext_tmds *tmds);
863extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
864 struct radeon_encoder_ext_tmds *tmds);
865extern struct radeon_encoder_primary_dac *
866radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
867extern struct radeon_encoder_tv_dac *
868radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
869extern struct radeon_encoder_lvds *
870radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
871extern struct radeon_encoder_tv_dac *
872radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
873extern struct radeon_encoder_primary_dac *
874radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
875extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
876extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
877extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
878extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
879extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
880extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
881extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
882extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
883extern void
884radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
885extern void
886radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
887extern void
888radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
889extern void
890radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
891int radeon_framebuffer_init(struct drm_device *dev,
892 struct drm_framebuffer *rfb,
893 const struct drm_mode_fb_cmd2 *mode_cmd,
894 struct drm_gem_object *obj);
895
896int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
897bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
898bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
899void radeon_atombios_init_crtc(struct drm_device *dev,
900 struct radeon_crtc *radeon_crtc);
901void radeon_legacy_init_crtc(struct drm_device *dev,
902 struct radeon_crtc *radeon_crtc);
903
904void radeon_get_clock_info(struct drm_device *dev);
905
906extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
907extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
908
909void radeon_enc_destroy(struct drm_encoder *encoder);
910void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
911void radeon_combios_asic_init(struct drm_device *dev);
912bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
913 const struct drm_display_mode *mode,
914 struct drm_display_mode *adjusted_mode);
915void radeon_panel_mode_fixup(struct drm_encoder *encoder,
916 struct drm_display_mode *adjusted_mode);
917void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
918
919/* legacy tv */
920void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
921 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
922 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
923void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
924 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
925 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
926void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
927 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
928 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
929void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
930 struct drm_display_mode *mode,
931 struct drm_display_mode *adjusted_mode);
932
933/* fmt blocks */
934void avivo_program_fmt(struct drm_encoder *encoder);
935void dce3_program_fmt(struct drm_encoder *encoder);
936void dce4_program_fmt(struct drm_encoder *encoder);
937void dce8_program_fmt(struct drm_encoder *encoder);
938
939/* fbdev layer */
940#if defined(CONFIG_DRM_FBDEV_EMULATION)
941int radeon_fbdev_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
942 struct drm_fb_helper_surface_size *sizes);
943#define RADEON_FBDEV_DRIVER_OPS \
944 .fbdev_probe = radeon_fbdev_driver_fbdev_probe
945bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
946#else
947#define RADEON_FBDEV_DRIVER_OPS \
948 .fbdev_probe = NULL
949static inline bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
950{
951 return false;
952}
953#endif
954
955void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
956
957void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
958
959int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
960void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
961#endif
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
38#include <linux/i2c.h>
39#include <linux/i2c-algo-bit.h>
40
41struct radeon_bo;
42struct radeon_device;
43
44#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
45#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48
49enum radeon_rmx_type {
50 RMX_OFF,
51 RMX_FULL,
52 RMX_CENTER,
53 RMX_ASPECT
54};
55
56enum radeon_tv_std {
57 TV_STD_NTSC,
58 TV_STD_PAL,
59 TV_STD_PAL_M,
60 TV_STD_PAL_60,
61 TV_STD_NTSC_J,
62 TV_STD_SCART_PAL,
63 TV_STD_SECAM,
64 TV_STD_PAL_CN,
65 TV_STD_PAL_N,
66};
67
68enum radeon_underscan_type {
69 UNDERSCAN_OFF,
70 UNDERSCAN_ON,
71 UNDERSCAN_AUTO,
72};
73
74enum radeon_hpd_id {
75 RADEON_HPD_1 = 0,
76 RADEON_HPD_2,
77 RADEON_HPD_3,
78 RADEON_HPD_4,
79 RADEON_HPD_5,
80 RADEON_HPD_6,
81 RADEON_HPD_NONE = 0xff,
82};
83
84#define RADEON_MAX_I2C_BUS 16
85
86/* radeon gpio-based i2c
87 * 1. "mask" reg and bits
88 * grabs the gpio pins for software use
89 * 0=not held 1=held
90 * 2. "a" reg and bits
91 * output pin value
92 * 0=low 1=high
93 * 3. "en" reg and bits
94 * sets the pin direction
95 * 0=input 1=output
96 * 4. "y" reg and bits
97 * input pin value
98 * 0=low 1=high
99 */
100struct radeon_i2c_bus_rec {
101 bool valid;
102 /* id used by atom */
103 uint8_t i2c_id;
104 /* id used by atom */
105 enum radeon_hpd_id hpd;
106 /* can be used with hw i2c engine */
107 bool hw_capable;
108 /* uses multi-media i2c engine */
109 bool mm_i2c;
110 /* regs and bits */
111 uint32_t mask_clk_reg;
112 uint32_t mask_data_reg;
113 uint32_t a_clk_reg;
114 uint32_t a_data_reg;
115 uint32_t en_clk_reg;
116 uint32_t en_data_reg;
117 uint32_t y_clk_reg;
118 uint32_t y_data_reg;
119 uint32_t mask_clk_mask;
120 uint32_t mask_data_mask;
121 uint32_t a_clk_mask;
122 uint32_t a_data_mask;
123 uint32_t en_clk_mask;
124 uint32_t en_data_mask;
125 uint32_t y_clk_mask;
126 uint32_t y_data_mask;
127};
128
129struct radeon_tmds_pll {
130 uint32_t freq;
131 uint32_t value;
132};
133
134#define RADEON_MAX_BIOS_CONNECTOR 16
135
136/* pll flags */
137#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
138#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
139#define RADEON_PLL_USE_REF_DIV (1 << 2)
140#define RADEON_PLL_LEGACY (1 << 3)
141#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
142#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
143#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
144#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
145#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
146#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
147#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
148#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
149#define RADEON_PLL_USE_POST_DIV (1 << 12)
150#define RADEON_PLL_IS_LCD (1 << 13)
151#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
152
153struct radeon_pll {
154 /* reference frequency */
155 uint32_t reference_freq;
156
157 /* fixed dividers */
158 uint32_t reference_div;
159 uint32_t post_div;
160
161 /* pll in/out limits */
162 uint32_t pll_in_min;
163 uint32_t pll_in_max;
164 uint32_t pll_out_min;
165 uint32_t pll_out_max;
166 uint32_t lcd_pll_out_min;
167 uint32_t lcd_pll_out_max;
168 uint32_t best_vco;
169
170 /* divider limits */
171 uint32_t min_ref_div;
172 uint32_t max_ref_div;
173 uint32_t min_post_div;
174 uint32_t max_post_div;
175 uint32_t min_feedback_div;
176 uint32_t max_feedback_div;
177 uint32_t min_frac_feedback_div;
178 uint32_t max_frac_feedback_div;
179
180 /* flags for the current clock */
181 uint32_t flags;
182
183 /* pll id */
184 uint32_t id;
185};
186
187struct radeon_i2c_chan {
188 struct i2c_adapter adapter;
189 struct drm_device *dev;
190 struct i2c_algo_bit_data bit;
191 struct radeon_i2c_bus_rec rec;
192 struct drm_dp_aux aux;
193 bool has_aux;
194};
195
196/* mostly for macs, but really any system without connector tables */
197enum radeon_connector_table {
198 CT_NONE = 0,
199 CT_GENERIC,
200 CT_IBOOK,
201 CT_POWERBOOK_EXTERNAL,
202 CT_POWERBOOK_INTERNAL,
203 CT_POWERBOOK_VGA,
204 CT_MINI_EXTERNAL,
205 CT_MINI_INTERNAL,
206 CT_IMAC_G5_ISIGHT,
207 CT_EMAC,
208 CT_RN50_POWER,
209 CT_MAC_X800,
210 CT_MAC_G5_9600,
211 CT_SAM440EP,
212 CT_MAC_G4_SILVER
213};
214
215enum radeon_dvo_chip {
216 DVO_SIL164,
217 DVO_SIL1178,
218};
219
220struct radeon_fbdev;
221
222struct radeon_afmt {
223 bool enabled;
224 int offset;
225 bool last_buffer_filled_status;
226 int id;
227 struct r600_audio_pin *pin;
228};
229
230struct radeon_mode_info {
231 struct atom_context *atom_context;
232 struct card_info *atom_card_info;
233 enum radeon_connector_table connector_table;
234 bool mode_config_initialized;
235 struct radeon_crtc *crtcs[6];
236 struct radeon_afmt *afmt[7];
237 /* DVI-I properties */
238 struct drm_property *coherent_mode_property;
239 /* DAC enable load detect */
240 struct drm_property *load_detect_property;
241 /* TV standard */
242 struct drm_property *tv_std_property;
243 /* legacy TMDS PLL detect */
244 struct drm_property *tmds_pll_property;
245 /* underscan */
246 struct drm_property *underscan_property;
247 struct drm_property *underscan_hborder_property;
248 struct drm_property *underscan_vborder_property;
249 /* audio */
250 struct drm_property *audio_property;
251 /* FMT dithering */
252 struct drm_property *dither_property;
253 /* hardcoded DFP edid from BIOS */
254 struct edid *bios_hardcoded_edid;
255 int bios_hardcoded_edid_size;
256
257 /* pointer to fbdev info structure */
258 struct radeon_fbdev *rfbdev;
259 /* firmware flags */
260 u16 firmware_flags;
261 /* pointer to backlight encoder */
262 struct radeon_encoder *bl_encoder;
263};
264
265#define RADEON_MAX_BL_LEVEL 0xFF
266
267#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
268
269struct radeon_backlight_privdata {
270 struct radeon_encoder *encoder;
271 uint8_t negative;
272};
273
274#endif
275
276#define MAX_H_CODE_TIMING_LEN 32
277#define MAX_V_CODE_TIMING_LEN 32
278
279/* need to store these as reading
280 back code tables is excessive */
281struct radeon_tv_regs {
282 uint32_t tv_uv_adr;
283 uint32_t timing_cntl;
284 uint32_t hrestart;
285 uint32_t vrestart;
286 uint32_t frestart;
287 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
288 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
289};
290
291struct radeon_atom_ss {
292 uint16_t percentage;
293 uint16_t percentage_divider;
294 uint8_t type;
295 uint16_t step;
296 uint8_t delay;
297 uint8_t range;
298 uint8_t refdiv;
299 /* asic_ss */
300 uint16_t rate;
301 uint16_t amount;
302};
303
304struct radeon_crtc {
305 struct drm_crtc base;
306 int crtc_id;
307 u16 lut_r[256], lut_g[256], lut_b[256];
308 bool enabled;
309 bool can_tile;
310 uint32_t crtc_offset;
311 struct drm_gem_object *cursor_bo;
312 uint64_t cursor_addr;
313 int cursor_width;
314 int cursor_height;
315 int max_cursor_width;
316 int max_cursor_height;
317 uint32_t legacy_display_base_addr;
318 uint32_t legacy_cursor_offset;
319 enum radeon_rmx_type rmx_type;
320 u8 h_border;
321 u8 v_border;
322 fixed20_12 vsc;
323 fixed20_12 hsc;
324 struct drm_display_mode native_mode;
325 int pll_id;
326 /* page flipping */
327 struct radeon_unpin_work *unpin_work;
328 int deferred_flip_completion;
329 /* pll sharing */
330 struct radeon_atom_ss ss;
331 bool ss_enabled;
332 u32 adjusted_clock;
333 int bpc;
334 u32 pll_reference_div;
335 u32 pll_post_div;
336 u32 pll_flags;
337 struct drm_encoder *encoder;
338 struct drm_connector *connector;
339 /* for dpm */
340 u32 line_time;
341 u32 wm_low;
342 u32 wm_high;
343 struct drm_display_mode hw_mode;
344};
345
346struct radeon_encoder_primary_dac {
347 /* legacy primary dac */
348 uint32_t ps2_pdac_adj;
349};
350
351struct radeon_encoder_lvds {
352 /* legacy lvds */
353 uint16_t panel_vcc_delay;
354 uint8_t panel_pwr_delay;
355 uint8_t panel_digon_delay;
356 uint8_t panel_blon_delay;
357 uint16_t panel_ref_divider;
358 uint8_t panel_post_divider;
359 uint16_t panel_fb_divider;
360 bool use_bios_dividers;
361 uint32_t lvds_gen_cntl;
362 /* panel mode */
363 struct drm_display_mode native_mode;
364 struct backlight_device *bl_dev;
365 int dpms_mode;
366 uint8_t backlight_level;
367};
368
369struct radeon_encoder_tv_dac {
370 /* legacy tv dac */
371 uint32_t ps2_tvdac_adj;
372 uint32_t ntsc_tvdac_adj;
373 uint32_t pal_tvdac_adj;
374
375 int h_pos;
376 int v_pos;
377 int h_size;
378 int supported_tv_stds;
379 bool tv_on;
380 enum radeon_tv_std tv_std;
381 struct radeon_tv_regs tv;
382};
383
384struct radeon_encoder_int_tmds {
385 /* legacy int tmds */
386 struct radeon_tmds_pll tmds_pll[4];
387};
388
389struct radeon_encoder_ext_tmds {
390 /* tmds over dvo */
391 struct radeon_i2c_chan *i2c_bus;
392 uint8_t slave_addr;
393 enum radeon_dvo_chip dvo_chip;
394};
395
396/* spread spectrum */
397struct radeon_encoder_atom_dig {
398 bool linkb;
399 /* atom dig */
400 bool coherent_mode;
401 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
402 /* atom lvds/edp */
403 uint32_t lcd_misc;
404 uint16_t panel_pwr_delay;
405 uint32_t lcd_ss_id;
406 /* panel mode */
407 struct drm_display_mode native_mode;
408 struct backlight_device *bl_dev;
409 int dpms_mode;
410 uint8_t backlight_level;
411 int panel_mode;
412 struct radeon_afmt *afmt;
413};
414
415struct radeon_encoder_atom_dac {
416 enum radeon_tv_std tv_std;
417};
418
419struct radeon_encoder {
420 struct drm_encoder base;
421 uint32_t encoder_enum;
422 uint32_t encoder_id;
423 uint32_t devices;
424 uint32_t active_device;
425 uint32_t flags;
426 uint32_t pixel_clock;
427 enum radeon_rmx_type rmx_type;
428 enum radeon_underscan_type underscan_type;
429 uint32_t underscan_hborder;
430 uint32_t underscan_vborder;
431 struct drm_display_mode native_mode;
432 void *enc_priv;
433 int audio_polling_active;
434 bool is_ext_encoder;
435 u16 caps;
436};
437
438struct radeon_connector_atom_dig {
439 uint32_t igp_lane_info;
440 /* displayport */
441 u8 dpcd[DP_RECEIVER_CAP_SIZE];
442 u8 dp_sink_type;
443 int dp_clock;
444 int dp_lane_count;
445 bool edp_on;
446};
447
448struct radeon_gpio_rec {
449 bool valid;
450 u8 id;
451 u32 reg;
452 u32 mask;
453};
454
455struct radeon_hpd {
456 enum radeon_hpd_id hpd;
457 u8 plugged_state;
458 struct radeon_gpio_rec gpio;
459};
460
461struct radeon_router {
462 u32 router_id;
463 struct radeon_i2c_bus_rec i2c_info;
464 u8 i2c_addr;
465 /* i2c mux */
466 bool ddc_valid;
467 u8 ddc_mux_type;
468 u8 ddc_mux_control_pin;
469 u8 ddc_mux_state;
470 /* clock/data mux */
471 bool cd_valid;
472 u8 cd_mux_type;
473 u8 cd_mux_control_pin;
474 u8 cd_mux_state;
475};
476
477enum radeon_connector_audio {
478 RADEON_AUDIO_DISABLE = 0,
479 RADEON_AUDIO_ENABLE = 1,
480 RADEON_AUDIO_AUTO = 2
481};
482
483enum radeon_connector_dither {
484 RADEON_FMT_DITHER_DISABLE = 0,
485 RADEON_FMT_DITHER_ENABLE = 1,
486};
487
488struct radeon_connector {
489 struct drm_connector base;
490 uint32_t connector_id;
491 uint32_t devices;
492 struct radeon_i2c_chan *ddc_bus;
493 /* some systems have an hdmi and vga port with a shared ddc line */
494 bool shared_ddc;
495 bool use_digital;
496 /* we need to mind the EDID between detect
497 and get modes due to analog/digital/tvencoder */
498 struct edid *edid;
499 void *con_priv;
500 bool dac_load_detect;
501 bool detected_by_load; /* if the connection status was determined by load */
502 uint16_t connector_object_id;
503 struct radeon_hpd hpd;
504 struct radeon_router router;
505 struct radeon_i2c_chan *router_bus;
506 enum radeon_connector_audio audio;
507 enum radeon_connector_dither dither;
508};
509
510struct radeon_framebuffer {
511 struct drm_framebuffer base;
512 struct drm_gem_object *obj;
513};
514
515#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
516 ((em) == ATOM_ENCODER_MODE_DP_MST))
517
518struct atom_clock_dividers {
519 u32 post_div;
520 union {
521 struct {
522#ifdef __BIG_ENDIAN
523 u32 reserved : 6;
524 u32 whole_fb_div : 12;
525 u32 frac_fb_div : 14;
526#else
527 u32 frac_fb_div : 14;
528 u32 whole_fb_div : 12;
529 u32 reserved : 6;
530#endif
531 };
532 u32 fb_div;
533 };
534 u32 ref_div;
535 bool enable_post_div;
536 bool enable_dithen;
537 u32 vco_mode;
538 u32 real_clock;
539 /* added for CI */
540 u32 post_divider;
541 u32 flags;
542};
543
544struct atom_mpll_param {
545 union {
546 struct {
547#ifdef __BIG_ENDIAN
548 u32 reserved : 8;
549 u32 clkfrac : 12;
550 u32 clkf : 12;
551#else
552 u32 clkf : 12;
553 u32 clkfrac : 12;
554 u32 reserved : 8;
555#endif
556 };
557 u32 fb_div;
558 };
559 u32 post_div;
560 u32 bwcntl;
561 u32 dll_speed;
562 u32 vco_mode;
563 u32 yclk_sel;
564 u32 qdr;
565 u32 half_rate;
566};
567
568#define MEM_TYPE_GDDR5 0x50
569#define MEM_TYPE_GDDR4 0x40
570#define MEM_TYPE_GDDR3 0x30
571#define MEM_TYPE_DDR2 0x20
572#define MEM_TYPE_GDDR1 0x10
573#define MEM_TYPE_DDR3 0xb0
574#define MEM_TYPE_MASK 0xf0
575
576struct atom_memory_info {
577 u8 mem_vendor;
578 u8 mem_type;
579};
580
581#define MAX_AC_TIMING_ENTRIES 16
582
583struct atom_memory_clock_range_table
584{
585 u8 num_entries;
586 u8 rsv[3];
587 u32 mclk[MAX_AC_TIMING_ENTRIES];
588};
589
590#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
591#define VBIOS_MAX_AC_TIMING_ENTRIES 20
592
593struct atom_mc_reg_entry {
594 u32 mclk_max;
595 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
596};
597
598struct atom_mc_register_address {
599 u16 s1;
600 u8 pre_reg_data;
601};
602
603struct atom_mc_reg_table {
604 u8 last;
605 u8 num_entries;
606 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
607 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
608};
609
610#define MAX_VOLTAGE_ENTRIES 32
611
612struct atom_voltage_table_entry
613{
614 u16 value;
615 u32 smio_low;
616};
617
618struct atom_voltage_table
619{
620 u32 count;
621 u32 mask_low;
622 u32 phase_delay;
623 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
624};
625
626
627extern void
628radeon_add_atom_connector(struct drm_device *dev,
629 uint32_t connector_id,
630 uint32_t supported_device,
631 int connector_type,
632 struct radeon_i2c_bus_rec *i2c_bus,
633 uint32_t igp_lane_info,
634 uint16_t connector_object_id,
635 struct radeon_hpd *hpd,
636 struct radeon_router *router);
637extern void
638radeon_add_legacy_connector(struct drm_device *dev,
639 uint32_t connector_id,
640 uint32_t supported_device,
641 int connector_type,
642 struct radeon_i2c_bus_rec *i2c_bus,
643 uint16_t connector_object_id,
644 struct radeon_hpd *hpd);
645extern uint32_t
646radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
647 uint8_t dac);
648extern void radeon_link_encoder_connector(struct drm_device *dev);
649
650extern enum radeon_tv_std
651radeon_combios_get_tv_info(struct radeon_device *rdev);
652extern enum radeon_tv_std
653radeon_atombios_get_tv_info(struct radeon_device *rdev);
654extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
655 u16 *vddc, u16 *vddci, u16 *mvdd);
656
657extern void
658radeon_combios_connected_scratch_regs(struct drm_connector *connector,
659 struct drm_encoder *encoder,
660 bool connected);
661extern void
662radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
663 struct drm_encoder *encoder,
664 bool connected);
665
666extern struct drm_connector *
667radeon_get_connector_for_encoder(struct drm_encoder *encoder);
668extern struct drm_connector *
669radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
670extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
671 u32 pixel_clock);
672
673extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
674extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
675extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
676extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
677extern int radeon_get_monitor_bpc(struct drm_connector *connector);
678
679extern void radeon_connector_hotplug(struct drm_connector *connector);
680extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
681 struct drm_display_mode *mode);
682extern void radeon_dp_set_link_config(struct drm_connector *connector,
683 const struct drm_display_mode *mode);
684extern void radeon_dp_link_train(struct drm_encoder *encoder,
685 struct drm_connector *connector);
686extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
687extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
688extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
689extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
690 struct drm_connector *connector);
691extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
692 u8 power_state);
693extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
694extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
695extern void radeon_atom_encoder_init(struct radeon_device *rdev);
696extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
697extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
698 int action, uint8_t lane_num,
699 uint8_t lane_set);
700extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
701extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
702void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
703
704extern void radeon_i2c_init(struct radeon_device *rdev);
705extern void radeon_i2c_fini(struct radeon_device *rdev);
706extern void radeon_combios_i2c_init(struct radeon_device *rdev);
707extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
708extern void radeon_i2c_add(struct radeon_device *rdev,
709 struct radeon_i2c_bus_rec *rec,
710 const char *name);
711extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
712 struct radeon_i2c_bus_rec *i2c_bus);
713extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
714 struct radeon_i2c_bus_rec *rec,
715 const char *name);
716extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
717extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
718 u8 slave_addr,
719 u8 addr,
720 u8 *val);
721extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
722 u8 slave_addr,
723 u8 addr,
724 u8 val);
725extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
726extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
727extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
728extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
729
730extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
731
732extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
733 struct radeon_atom_ss *ss,
734 int id);
735extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
736 struct radeon_atom_ss *ss,
737 int id, u32 clock);
738
739extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
740 uint64_t freq,
741 uint32_t *dot_clock_p,
742 uint32_t *fb_div_p,
743 uint32_t *frac_fb_div_p,
744 uint32_t *ref_div_p,
745 uint32_t *post_div_p);
746
747extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
748 u32 freq,
749 u32 *dot_clock_p,
750 u32 *fb_div_p,
751 u32 *frac_fb_div_p,
752 u32 *ref_div_p,
753 u32 *post_div_p);
754
755extern void radeon_setup_encoder_clones(struct drm_device *dev);
756
757struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
758struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
759struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
760struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
761struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
762extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
763extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
764extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
765extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
766extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
767
768extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
769extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
770 struct drm_framebuffer *old_fb);
771extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
772 struct drm_framebuffer *fb,
773 int x, int y,
774 enum mode_set_atomic state);
775extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
776 struct drm_display_mode *mode,
777 struct drm_display_mode *adjusted_mode,
778 int x, int y,
779 struct drm_framebuffer *old_fb);
780extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
781
782extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
783 struct drm_framebuffer *old_fb);
784extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
785 struct drm_framebuffer *fb,
786 int x, int y,
787 enum mode_set_atomic state);
788extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
789 struct drm_framebuffer *fb,
790 int x, int y, int atomic);
791extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
792 struct drm_file *file_priv,
793 uint32_t handle,
794 uint32_t width,
795 uint32_t height);
796extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
797 int x, int y);
798
799extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
800 unsigned int flags,
801 int *vpos, int *hpos, ktime_t *stime,
802 ktime_t *etime);
803
804extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
805extern struct edid *
806radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
807extern bool radeon_atom_get_clock_info(struct drm_device *dev);
808extern bool radeon_combios_get_clock_info(struct drm_device *dev);
809extern struct radeon_encoder_atom_dig *
810radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
811extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
812 struct radeon_encoder_int_tmds *tmds);
813extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
814 struct radeon_encoder_int_tmds *tmds);
815extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
816 struct radeon_encoder_int_tmds *tmds);
817extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
818 struct radeon_encoder_ext_tmds *tmds);
819extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
820 struct radeon_encoder_ext_tmds *tmds);
821extern struct radeon_encoder_primary_dac *
822radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
823extern struct radeon_encoder_tv_dac *
824radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
825extern struct radeon_encoder_lvds *
826radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
827extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
828extern struct radeon_encoder_tv_dac *
829radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
830extern struct radeon_encoder_primary_dac *
831radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
832extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
833extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
834extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
835extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
836extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
837extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
838extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
839extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
840extern void
841radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
842extern void
843radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
844extern void
845radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
846extern void
847radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
848extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
849 u16 blue, int regno);
850extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
851 u16 *blue, int regno);
852int radeon_framebuffer_init(struct drm_device *dev,
853 struct radeon_framebuffer *rfb,
854 struct drm_mode_fb_cmd2 *mode_cmd,
855 struct drm_gem_object *obj);
856
857int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
858bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
859bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
860void radeon_atombios_init_crtc(struct drm_device *dev,
861 struct radeon_crtc *radeon_crtc);
862void radeon_legacy_init_crtc(struct drm_device *dev,
863 struct radeon_crtc *radeon_crtc);
864
865void radeon_get_clock_info(struct drm_device *dev);
866
867extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
868extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
869
870void radeon_enc_destroy(struct drm_encoder *encoder);
871void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
872void radeon_combios_asic_init(struct drm_device *dev);
873bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
874 const struct drm_display_mode *mode,
875 struct drm_display_mode *adjusted_mode);
876void radeon_panel_mode_fixup(struct drm_encoder *encoder,
877 struct drm_display_mode *adjusted_mode);
878void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
879
880/* legacy tv */
881void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
882 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
883 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
884void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
885 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
886 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
887void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
888 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
889 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
890void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
891 struct drm_display_mode *mode,
892 struct drm_display_mode *adjusted_mode);
893
894/* fmt blocks */
895void avivo_program_fmt(struct drm_encoder *encoder);
896void dce3_program_fmt(struct drm_encoder *encoder);
897void dce4_program_fmt(struct drm_encoder *encoder);
898void dce8_program_fmt(struct drm_encoder *encoder);
899
900/* fbdev layer */
901int radeon_fbdev_init(struct radeon_device *rdev);
902void radeon_fbdev_fini(struct radeon_device *rdev);
903void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
904int radeon_fbdev_total_size(struct radeon_device *rdev);
905bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
906
907void radeon_fb_output_poll_changed(struct radeon_device *rdev);
908
909void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
910
911int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
912#endif