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1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include <drm/drmP.h>
31#include "i915_drv.h"
32#include <drm/i915_drm.h>
33#include "i915_trace.h"
34#include "intel_drv.h"
35
36static inline int ring_space(struct intel_ring_buffer *ring)
37{
38 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
39 if (space < 0)
40 space += ring->size;
41 return space;
42}
43
44void __intel_ring_advance(struct intel_ring_buffer *ring)
45{
46 struct drm_i915_private *dev_priv = ring->dev->dev_private;
47
48 ring->tail &= ring->size - 1;
49 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
50 return;
51 ring->write_tail(ring, ring->tail);
52}
53
54static int
55gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58{
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78}
79
80static int
81gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84{
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136}
137
138/**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175static int
176intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177{
178 u32 scratch_addr = ring->scratch.gtt_offset + 128;
179 int ret;
180
181
182 ret = intel_ring_begin(ring, 6);
183 if (ret)
184 return ret;
185
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
194
195 ret = intel_ring_begin(ring, 6);
196 if (ret)
197 return ret;
198
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
206
207 return 0;
208}
209
210static int
211gen6_render_ring_flush(struct intel_ring_buffer *ring,
212 u32 invalidate_domains, u32 flush_domains)
213{
214 u32 flags = 0;
215 u32 scratch_addr = ring->scratch.gtt_offset + 128;
216 int ret;
217
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret = intel_emit_post_sync_nonzero_flush(ring);
220 if (ret)
221 return ret;
222
223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
225 * impact.
226 */
227 if (flush_domains) {
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
230 /*
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
233 */
234 flags |= PIPE_CONTROL_CS_STALL;
235 }
236 if (invalidate_domains) {
237 flags |= PIPE_CONTROL_TLB_INVALIDATE;
238 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
243 /*
244 * TLB invalidate requires a post-sync write.
245 */
246 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
247 }
248
249 ret = intel_ring_begin(ring, 4);
250 if (ret)
251 return ret;
252
253 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
254 intel_ring_emit(ring, flags);
255 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
256 intel_ring_emit(ring, 0);
257 intel_ring_advance(ring);
258
259 return 0;
260}
261
262static int
263gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
264{
265 int ret;
266
267 ret = intel_ring_begin(ring, 4);
268 if (ret)
269 return ret;
270
271 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
273 PIPE_CONTROL_STALL_AT_SCOREBOARD);
274 intel_ring_emit(ring, 0);
275 intel_ring_emit(ring, 0);
276 intel_ring_advance(ring);
277
278 return 0;
279}
280
281static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
282{
283 int ret;
284
285 if (!ring->fbc_dirty)
286 return 0;
287
288 ret = intel_ring_begin(ring, 6);
289 if (ret)
290 return ret;
291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring, MSG_FBC_REND_STATE);
294 intel_ring_emit(ring, value);
295 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
298 intel_ring_advance(ring);
299
300 ring->fbc_dirty = false;
301 return 0;
302}
303
304static int
305gen7_render_ring_flush(struct intel_ring_buffer *ring,
306 u32 invalidate_domains, u32 flush_domains)
307{
308 u32 flags = 0;
309 u32 scratch_addr = ring->scratch.gtt_offset + 128;
310 int ret;
311
312 /*
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
315 *
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
319 */
320 flags |= PIPE_CONTROL_CS_STALL;
321
322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
324 * impact.
325 */
326 if (flush_domains) {
327 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
328 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
329 }
330 if (invalidate_domains) {
331 flags |= PIPE_CONTROL_TLB_INVALIDATE;
332 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
333 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
337 /*
338 * TLB invalidate requires a post-sync write.
339 */
340 flags |= PIPE_CONTROL_QW_WRITE;
341 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
342
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring);
347 }
348
349 ret = intel_ring_begin(ring, 4);
350 if (ret)
351 return ret;
352
353 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring, flags);
355 intel_ring_emit(ring, scratch_addr);
356 intel_ring_emit(ring, 0);
357 intel_ring_advance(ring);
358
359 if (!invalidate_domains && flush_domains)
360 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
361
362 return 0;
363}
364
365static int
366gen8_render_ring_flush(struct intel_ring_buffer *ring,
367 u32 invalidate_domains, u32 flush_domains)
368{
369 u32 flags = 0;
370 u32 scratch_addr = ring->scratch.gtt_offset + 128;
371 int ret;
372
373 flags |= PIPE_CONTROL_CS_STALL;
374
375 if (flush_domains) {
376 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
377 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
378 }
379 if (invalidate_domains) {
380 flags |= PIPE_CONTROL_TLB_INVALIDATE;
381 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
382 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
383 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
384 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
385 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
386 flags |= PIPE_CONTROL_QW_WRITE;
387 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
388 }
389
390 ret = intel_ring_begin(ring, 6);
391 if (ret)
392 return ret;
393
394 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring, flags);
396 intel_ring_emit(ring, scratch_addr);
397 intel_ring_emit(ring, 0);
398 intel_ring_emit(ring, 0);
399 intel_ring_emit(ring, 0);
400 intel_ring_advance(ring);
401
402 return 0;
403
404}
405
406static void ring_write_tail(struct intel_ring_buffer *ring,
407 u32 value)
408{
409 struct drm_i915_private *dev_priv = ring->dev->dev_private;
410 I915_WRITE_TAIL(ring, value);
411}
412
413u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
414{
415 struct drm_i915_private *dev_priv = ring->dev->dev_private;
416 u64 acthd;
417
418 if (INTEL_INFO(ring->dev)->gen >= 8)
419 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
420 RING_ACTHD_UDW(ring->mmio_base));
421 else if (INTEL_INFO(ring->dev)->gen >= 4)
422 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
423 else
424 acthd = I915_READ(ACTHD);
425
426 return acthd;
427}
428
429static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
430{
431 struct drm_i915_private *dev_priv = ring->dev->dev_private;
432 u32 addr;
433
434 addr = dev_priv->status_page_dmah->busaddr;
435 if (INTEL_INFO(ring->dev)->gen >= 4)
436 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
437 I915_WRITE(HWS_PGA, addr);
438}
439
440static bool stop_ring(struct intel_ring_buffer *ring)
441{
442 struct drm_i915_private *dev_priv = to_i915(ring->dev);
443
444 if (!IS_GEN2(ring->dev)) {
445 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
446 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
447 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
448 return false;
449 }
450 }
451
452 I915_WRITE_CTL(ring, 0);
453 I915_WRITE_HEAD(ring, 0);
454 ring->write_tail(ring, 0);
455
456 if (!IS_GEN2(ring->dev)) {
457 (void)I915_READ_CTL(ring);
458 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
459 }
460
461 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
462}
463
464static int init_ring_common(struct intel_ring_buffer *ring)
465{
466 struct drm_device *dev = ring->dev;
467 struct drm_i915_private *dev_priv = dev->dev_private;
468 struct drm_i915_gem_object *obj = ring->obj;
469 int ret = 0;
470
471 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
472
473 if (!stop_ring(ring)) {
474 /* G45 ring initialization often fails to reset head to zero */
475 DRM_DEBUG_KMS("%s head not reset to zero "
476 "ctl %08x head %08x tail %08x start %08x\n",
477 ring->name,
478 I915_READ_CTL(ring),
479 I915_READ_HEAD(ring),
480 I915_READ_TAIL(ring),
481 I915_READ_START(ring));
482
483 if (!stop_ring(ring)) {
484 DRM_ERROR("failed to set %s head to zero "
485 "ctl %08x head %08x tail %08x start %08x\n",
486 ring->name,
487 I915_READ_CTL(ring),
488 I915_READ_HEAD(ring),
489 I915_READ_TAIL(ring),
490 I915_READ_START(ring));
491 ret = -EIO;
492 goto out;
493 }
494 }
495
496 if (I915_NEED_GFX_HWS(dev))
497 intel_ring_setup_status_page(ring);
498 else
499 ring_setup_phys_status_page(ring);
500
501 /* Initialize the ring. This must happen _after_ we've cleared the ring
502 * registers with the above sequence (the readback of the HEAD registers
503 * also enforces ordering), otherwise the hw might lose the new ring
504 * register values. */
505 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
506 I915_WRITE_CTL(ring,
507 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
508 | RING_VALID);
509
510 /* If the head is still not zero, the ring is dead */
511 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
512 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
513 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
514 DRM_ERROR("%s initialization failed "
515 "ctl %08x head %08x tail %08x start %08x\n",
516 ring->name,
517 I915_READ_CTL(ring),
518 I915_READ_HEAD(ring),
519 I915_READ_TAIL(ring),
520 I915_READ_START(ring));
521 ret = -EIO;
522 goto out;
523 }
524
525 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
526 i915_kernel_lost_context(ring->dev);
527 else {
528 ring->head = I915_READ_HEAD(ring);
529 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
530 ring->space = ring_space(ring);
531 ring->last_retired_head = -1;
532 }
533
534 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
535
536out:
537 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
538
539 return ret;
540}
541
542static int
543init_pipe_control(struct intel_ring_buffer *ring)
544{
545 int ret;
546
547 if (ring->scratch.obj)
548 return 0;
549
550 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
551 if (ring->scratch.obj == NULL) {
552 DRM_ERROR("Failed to allocate seqno page\n");
553 ret = -ENOMEM;
554 goto err;
555 }
556
557 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
558 if (ret)
559 goto err_unref;
560
561 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
562 if (ret)
563 goto err_unref;
564
565 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
566 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
567 if (ring->scratch.cpu_page == NULL) {
568 ret = -ENOMEM;
569 goto err_unpin;
570 }
571
572 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
573 ring->name, ring->scratch.gtt_offset);
574 return 0;
575
576err_unpin:
577 i915_gem_object_ggtt_unpin(ring->scratch.obj);
578err_unref:
579 drm_gem_object_unreference(&ring->scratch.obj->base);
580err:
581 return ret;
582}
583
584static int init_render_ring(struct intel_ring_buffer *ring)
585{
586 struct drm_device *dev = ring->dev;
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 int ret = init_ring_common(ring);
589
590 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
591 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
592 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
593
594 /* We need to disable the AsyncFlip performance optimisations in order
595 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
596 * programmed to '1' on all products.
597 *
598 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
599 */
600 if (INTEL_INFO(dev)->gen >= 6)
601 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
602
603 /* Required for the hardware to program scanline values for waiting */
604 if (INTEL_INFO(dev)->gen == 6)
605 I915_WRITE(GFX_MODE,
606 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
607
608 if (IS_GEN7(dev))
609 I915_WRITE(GFX_MODE_GEN7,
610 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
611 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
612
613 if (INTEL_INFO(dev)->gen >= 5) {
614 ret = init_pipe_control(ring);
615 if (ret)
616 return ret;
617 }
618
619 if (IS_GEN6(dev)) {
620 /* From the Sandybridge PRM, volume 1 part 3, page 24:
621 * "If this bit is set, STCunit will have LRA as replacement
622 * policy. [...] This bit must be reset. LRA replacement
623 * policy is not supported."
624 */
625 I915_WRITE(CACHE_MODE_0,
626 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
627
628 /* This is not explicitly set for GEN6, so read the register.
629 * see intel_ring_mi_set_context() for why we care.
630 * TODO: consider explicitly setting the bit for GEN5
631 */
632 ring->itlb_before_ctx_switch =
633 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
634 }
635
636 if (INTEL_INFO(dev)->gen >= 6)
637 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
638
639 if (HAS_L3_DPF(dev))
640 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
641
642 return ret;
643}
644
645static void render_ring_cleanup(struct intel_ring_buffer *ring)
646{
647 struct drm_device *dev = ring->dev;
648
649 if (ring->scratch.obj == NULL)
650 return;
651
652 if (INTEL_INFO(dev)->gen >= 5) {
653 kunmap(sg_page(ring->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(ring->scratch.obj);
655 }
656
657 drm_gem_object_unreference(&ring->scratch.obj->base);
658 ring->scratch.obj = NULL;
659}
660
661static void
662update_mboxes(struct intel_ring_buffer *ring,
663 u32 mmio_offset)
664{
665/* NB: In order to be able to do semaphore MBOX updates for varying number
666 * of rings, it's easiest if we round up each individual update to a
667 * multiple of 2 (since ring updates must always be a multiple of 2)
668 * even though the actual update only requires 3 dwords.
669 */
670#define MBOX_UPDATE_DWORDS 4
671 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
672 intel_ring_emit(ring, mmio_offset);
673 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
674 intel_ring_emit(ring, MI_NOOP);
675}
676
677/**
678 * gen6_add_request - Update the semaphore mailbox registers
679 *
680 * @ring - ring that is adding a request
681 * @seqno - return seqno stuck into the ring
682 *
683 * Update the mailbox registers in the *other* rings with the current seqno.
684 * This acts like a signal in the canonical semaphore.
685 */
686static int
687gen6_add_request(struct intel_ring_buffer *ring)
688{
689 struct drm_device *dev = ring->dev;
690 struct drm_i915_private *dev_priv = dev->dev_private;
691 struct intel_ring_buffer *useless;
692 int i, ret, num_dwords = 4;
693
694 if (i915_semaphore_is_enabled(dev))
695 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
696#undef MBOX_UPDATE_DWORDS
697
698 ret = intel_ring_begin(ring, num_dwords);
699 if (ret)
700 return ret;
701
702 if (i915_semaphore_is_enabled(dev)) {
703 for_each_ring(useless, dev_priv, i) {
704 u32 mbox_reg = ring->signal_mbox[i];
705 if (mbox_reg != GEN6_NOSYNC)
706 update_mboxes(ring, mbox_reg);
707 }
708 }
709
710 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
711 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
712 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
713 intel_ring_emit(ring, MI_USER_INTERRUPT);
714 __intel_ring_advance(ring);
715
716 return 0;
717}
718
719static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
720 u32 seqno)
721{
722 struct drm_i915_private *dev_priv = dev->dev_private;
723 return dev_priv->last_seqno < seqno;
724}
725
726/**
727 * intel_ring_sync - sync the waiter to the signaller on seqno
728 *
729 * @waiter - ring that is waiting
730 * @signaller - ring which has, or will signal
731 * @seqno - seqno which the waiter will block on
732 */
733static int
734gen6_ring_sync(struct intel_ring_buffer *waiter,
735 struct intel_ring_buffer *signaller,
736 u32 seqno)
737{
738 int ret;
739 u32 dw1 = MI_SEMAPHORE_MBOX |
740 MI_SEMAPHORE_COMPARE |
741 MI_SEMAPHORE_REGISTER;
742
743 /* Throughout all of the GEM code, seqno passed implies our current
744 * seqno is >= the last seqno executed. However for hardware the
745 * comparison is strictly greater than.
746 */
747 seqno -= 1;
748
749 WARN_ON(signaller->semaphore_register[waiter->id] ==
750 MI_SEMAPHORE_SYNC_INVALID);
751
752 ret = intel_ring_begin(waiter, 4);
753 if (ret)
754 return ret;
755
756 /* If seqno wrap happened, omit the wait with no-ops */
757 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
758 intel_ring_emit(waiter,
759 dw1 |
760 signaller->semaphore_register[waiter->id]);
761 intel_ring_emit(waiter, seqno);
762 intel_ring_emit(waiter, 0);
763 intel_ring_emit(waiter, MI_NOOP);
764 } else {
765 intel_ring_emit(waiter, MI_NOOP);
766 intel_ring_emit(waiter, MI_NOOP);
767 intel_ring_emit(waiter, MI_NOOP);
768 intel_ring_emit(waiter, MI_NOOP);
769 }
770 intel_ring_advance(waiter);
771
772 return 0;
773}
774
775#define PIPE_CONTROL_FLUSH(ring__, addr__) \
776do { \
777 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
778 PIPE_CONTROL_DEPTH_STALL); \
779 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
780 intel_ring_emit(ring__, 0); \
781 intel_ring_emit(ring__, 0); \
782} while (0)
783
784static int
785pc_render_add_request(struct intel_ring_buffer *ring)
786{
787 u32 scratch_addr = ring->scratch.gtt_offset + 128;
788 int ret;
789
790 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
791 * incoherent with writes to memory, i.e. completely fubar,
792 * so we need to use PIPE_NOTIFY instead.
793 *
794 * However, we also need to workaround the qword write
795 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
796 * memory before requesting an interrupt.
797 */
798 ret = intel_ring_begin(ring, 32);
799 if (ret)
800 return ret;
801
802 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
803 PIPE_CONTROL_WRITE_FLUSH |
804 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
805 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
806 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
807 intel_ring_emit(ring, 0);
808 PIPE_CONTROL_FLUSH(ring, scratch_addr);
809 scratch_addr += 128; /* write to separate cachelines */
810 PIPE_CONTROL_FLUSH(ring, scratch_addr);
811 scratch_addr += 128;
812 PIPE_CONTROL_FLUSH(ring, scratch_addr);
813 scratch_addr += 128;
814 PIPE_CONTROL_FLUSH(ring, scratch_addr);
815 scratch_addr += 128;
816 PIPE_CONTROL_FLUSH(ring, scratch_addr);
817 scratch_addr += 128;
818 PIPE_CONTROL_FLUSH(ring, scratch_addr);
819
820 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
821 PIPE_CONTROL_WRITE_FLUSH |
822 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
823 PIPE_CONTROL_NOTIFY);
824 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
825 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
826 intel_ring_emit(ring, 0);
827 __intel_ring_advance(ring);
828
829 return 0;
830}
831
832static u32
833gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
834{
835 /* Workaround to force correct ordering between irq and seqno writes on
836 * ivb (and maybe also on snb) by reading from a CS register (like
837 * ACTHD) before reading the status page. */
838 if (!lazy_coherency) {
839 struct drm_i915_private *dev_priv = ring->dev->dev_private;
840 POSTING_READ(RING_ACTHD(ring->mmio_base));
841 }
842
843 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
844}
845
846static u32
847ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
848{
849 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
850}
851
852static void
853ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
854{
855 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
856}
857
858static u32
859pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
860{
861 return ring->scratch.cpu_page[0];
862}
863
864static void
865pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
866{
867 ring->scratch.cpu_page[0] = seqno;
868}
869
870static bool
871gen5_ring_get_irq(struct intel_ring_buffer *ring)
872{
873 struct drm_device *dev = ring->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 unsigned long flags;
876
877 if (!dev->irq_enabled)
878 return false;
879
880 spin_lock_irqsave(&dev_priv->irq_lock, flags);
881 if (ring->irq_refcount++ == 0)
882 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
883 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
884
885 return true;
886}
887
888static void
889gen5_ring_put_irq(struct intel_ring_buffer *ring)
890{
891 struct drm_device *dev = ring->dev;
892 struct drm_i915_private *dev_priv = dev->dev_private;
893 unsigned long flags;
894
895 spin_lock_irqsave(&dev_priv->irq_lock, flags);
896 if (--ring->irq_refcount == 0)
897 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
898 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
899}
900
901static bool
902i9xx_ring_get_irq(struct intel_ring_buffer *ring)
903{
904 struct drm_device *dev = ring->dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 unsigned long flags;
907
908 if (!dev->irq_enabled)
909 return false;
910
911 spin_lock_irqsave(&dev_priv->irq_lock, flags);
912 if (ring->irq_refcount++ == 0) {
913 dev_priv->irq_mask &= ~ring->irq_enable_mask;
914 I915_WRITE(IMR, dev_priv->irq_mask);
915 POSTING_READ(IMR);
916 }
917 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
918
919 return true;
920}
921
922static void
923i9xx_ring_put_irq(struct intel_ring_buffer *ring)
924{
925 struct drm_device *dev = ring->dev;
926 struct drm_i915_private *dev_priv = dev->dev_private;
927 unsigned long flags;
928
929 spin_lock_irqsave(&dev_priv->irq_lock, flags);
930 if (--ring->irq_refcount == 0) {
931 dev_priv->irq_mask |= ring->irq_enable_mask;
932 I915_WRITE(IMR, dev_priv->irq_mask);
933 POSTING_READ(IMR);
934 }
935 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
936}
937
938static bool
939i8xx_ring_get_irq(struct intel_ring_buffer *ring)
940{
941 struct drm_device *dev = ring->dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
943 unsigned long flags;
944
945 if (!dev->irq_enabled)
946 return false;
947
948 spin_lock_irqsave(&dev_priv->irq_lock, flags);
949 if (ring->irq_refcount++ == 0) {
950 dev_priv->irq_mask &= ~ring->irq_enable_mask;
951 I915_WRITE16(IMR, dev_priv->irq_mask);
952 POSTING_READ16(IMR);
953 }
954 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
955
956 return true;
957}
958
959static void
960i8xx_ring_put_irq(struct intel_ring_buffer *ring)
961{
962 struct drm_device *dev = ring->dev;
963 struct drm_i915_private *dev_priv = dev->dev_private;
964 unsigned long flags;
965
966 spin_lock_irqsave(&dev_priv->irq_lock, flags);
967 if (--ring->irq_refcount == 0) {
968 dev_priv->irq_mask |= ring->irq_enable_mask;
969 I915_WRITE16(IMR, dev_priv->irq_mask);
970 POSTING_READ16(IMR);
971 }
972 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
973}
974
975void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
976{
977 struct drm_device *dev = ring->dev;
978 struct drm_i915_private *dev_priv = ring->dev->dev_private;
979 u32 mmio = 0;
980
981 /* The ring status page addresses are no longer next to the rest of
982 * the ring registers as of gen7.
983 */
984 if (IS_GEN7(dev)) {
985 switch (ring->id) {
986 case RCS:
987 mmio = RENDER_HWS_PGA_GEN7;
988 break;
989 case BCS:
990 mmio = BLT_HWS_PGA_GEN7;
991 break;
992 case VCS:
993 mmio = BSD_HWS_PGA_GEN7;
994 break;
995 case VECS:
996 mmio = VEBOX_HWS_PGA_GEN7;
997 break;
998 }
999 } else if (IS_GEN6(ring->dev)) {
1000 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1001 } else {
1002 /* XXX: gen8 returns to sanity */
1003 mmio = RING_HWS_PGA(ring->mmio_base);
1004 }
1005
1006 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1007 POSTING_READ(mmio);
1008
1009 /*
1010 * Flush the TLB for this page
1011 *
1012 * FIXME: These two bits have disappeared on gen8, so a question
1013 * arises: do we still need this and if so how should we go about
1014 * invalidating the TLB?
1015 */
1016 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1017 u32 reg = RING_INSTPM(ring->mmio_base);
1018
1019 /* ring should be idle before issuing a sync flush*/
1020 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1021
1022 I915_WRITE(reg,
1023 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1024 INSTPM_SYNC_FLUSH));
1025 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1026 1000))
1027 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1028 ring->name);
1029 }
1030}
1031
1032static int
1033bsd_ring_flush(struct intel_ring_buffer *ring,
1034 u32 invalidate_domains,
1035 u32 flush_domains)
1036{
1037 int ret;
1038
1039 ret = intel_ring_begin(ring, 2);
1040 if (ret)
1041 return ret;
1042
1043 intel_ring_emit(ring, MI_FLUSH);
1044 intel_ring_emit(ring, MI_NOOP);
1045 intel_ring_advance(ring);
1046 return 0;
1047}
1048
1049static int
1050i9xx_add_request(struct intel_ring_buffer *ring)
1051{
1052 int ret;
1053
1054 ret = intel_ring_begin(ring, 4);
1055 if (ret)
1056 return ret;
1057
1058 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1059 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1060 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1061 intel_ring_emit(ring, MI_USER_INTERRUPT);
1062 __intel_ring_advance(ring);
1063
1064 return 0;
1065}
1066
1067static bool
1068gen6_ring_get_irq(struct intel_ring_buffer *ring)
1069{
1070 struct drm_device *dev = ring->dev;
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 unsigned long flags;
1073
1074 if (!dev->irq_enabled)
1075 return false;
1076
1077 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1078 if (ring->irq_refcount++ == 0) {
1079 if (HAS_L3_DPF(dev) && ring->id == RCS)
1080 I915_WRITE_IMR(ring,
1081 ~(ring->irq_enable_mask |
1082 GT_PARITY_ERROR(dev)));
1083 else
1084 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1085 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1086 }
1087 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1088
1089 return true;
1090}
1091
1092static void
1093gen6_ring_put_irq(struct intel_ring_buffer *ring)
1094{
1095 struct drm_device *dev = ring->dev;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 unsigned long flags;
1098
1099 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1100 if (--ring->irq_refcount == 0) {
1101 if (HAS_L3_DPF(dev) && ring->id == RCS)
1102 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1103 else
1104 I915_WRITE_IMR(ring, ~0);
1105 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1106 }
1107 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1108}
1109
1110static bool
1111hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1112{
1113 struct drm_device *dev = ring->dev;
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 unsigned long flags;
1116
1117 if (!dev->irq_enabled)
1118 return false;
1119
1120 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1121 if (ring->irq_refcount++ == 0) {
1122 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1123 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1124 }
1125 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1126
1127 return true;
1128}
1129
1130static void
1131hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1132{
1133 struct drm_device *dev = ring->dev;
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135 unsigned long flags;
1136
1137 if (!dev->irq_enabled)
1138 return;
1139
1140 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1141 if (--ring->irq_refcount == 0) {
1142 I915_WRITE_IMR(ring, ~0);
1143 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1144 }
1145 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1146}
1147
1148static bool
1149gen8_ring_get_irq(struct intel_ring_buffer *ring)
1150{
1151 struct drm_device *dev = ring->dev;
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 unsigned long flags;
1154
1155 if (!dev->irq_enabled)
1156 return false;
1157
1158 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1159 if (ring->irq_refcount++ == 0) {
1160 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1161 I915_WRITE_IMR(ring,
1162 ~(ring->irq_enable_mask |
1163 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1164 } else {
1165 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1166 }
1167 POSTING_READ(RING_IMR(ring->mmio_base));
1168 }
1169 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1170
1171 return true;
1172}
1173
1174static void
1175gen8_ring_put_irq(struct intel_ring_buffer *ring)
1176{
1177 struct drm_device *dev = ring->dev;
1178 struct drm_i915_private *dev_priv = dev->dev_private;
1179 unsigned long flags;
1180
1181 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1182 if (--ring->irq_refcount == 0) {
1183 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1184 I915_WRITE_IMR(ring,
1185 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1186 } else {
1187 I915_WRITE_IMR(ring, ~0);
1188 }
1189 POSTING_READ(RING_IMR(ring->mmio_base));
1190 }
1191 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1192}
1193
1194static int
1195i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1196 u32 offset, u32 length,
1197 unsigned flags)
1198{
1199 int ret;
1200
1201 ret = intel_ring_begin(ring, 2);
1202 if (ret)
1203 return ret;
1204
1205 intel_ring_emit(ring,
1206 MI_BATCH_BUFFER_START |
1207 MI_BATCH_GTT |
1208 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1209 intel_ring_emit(ring, offset);
1210 intel_ring_advance(ring);
1211
1212 return 0;
1213}
1214
1215/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1216#define I830_BATCH_LIMIT (256*1024)
1217static int
1218i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1219 u32 offset, u32 len,
1220 unsigned flags)
1221{
1222 int ret;
1223
1224 if (flags & I915_DISPATCH_PINNED) {
1225 ret = intel_ring_begin(ring, 4);
1226 if (ret)
1227 return ret;
1228
1229 intel_ring_emit(ring, MI_BATCH_BUFFER);
1230 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1231 intel_ring_emit(ring, offset + len - 8);
1232 intel_ring_emit(ring, MI_NOOP);
1233 intel_ring_advance(ring);
1234 } else {
1235 u32 cs_offset = ring->scratch.gtt_offset;
1236
1237 if (len > I830_BATCH_LIMIT)
1238 return -ENOSPC;
1239
1240 ret = intel_ring_begin(ring, 9+3);
1241 if (ret)
1242 return ret;
1243 /* Blit the batch (which has now all relocs applied) to the stable batch
1244 * scratch bo area (so that the CS never stumbles over its tlb
1245 * invalidation bug) ... */
1246 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1247 XY_SRC_COPY_BLT_WRITE_ALPHA |
1248 XY_SRC_COPY_BLT_WRITE_RGB);
1249 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1250 intel_ring_emit(ring, 0);
1251 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1252 intel_ring_emit(ring, cs_offset);
1253 intel_ring_emit(ring, 0);
1254 intel_ring_emit(ring, 4096);
1255 intel_ring_emit(ring, offset);
1256 intel_ring_emit(ring, MI_FLUSH);
1257
1258 /* ... and execute it. */
1259 intel_ring_emit(ring, MI_BATCH_BUFFER);
1260 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1261 intel_ring_emit(ring, cs_offset + len - 8);
1262 intel_ring_advance(ring);
1263 }
1264
1265 return 0;
1266}
1267
1268static int
1269i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1270 u32 offset, u32 len,
1271 unsigned flags)
1272{
1273 int ret;
1274
1275 ret = intel_ring_begin(ring, 2);
1276 if (ret)
1277 return ret;
1278
1279 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1280 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1281 intel_ring_advance(ring);
1282
1283 return 0;
1284}
1285
1286static void cleanup_status_page(struct intel_ring_buffer *ring)
1287{
1288 struct drm_i915_gem_object *obj;
1289
1290 obj = ring->status_page.obj;
1291 if (obj == NULL)
1292 return;
1293
1294 kunmap(sg_page(obj->pages->sgl));
1295 i915_gem_object_ggtt_unpin(obj);
1296 drm_gem_object_unreference(&obj->base);
1297 ring->status_page.obj = NULL;
1298}
1299
1300static int init_status_page(struct intel_ring_buffer *ring)
1301{
1302 struct drm_device *dev = ring->dev;
1303 struct drm_i915_gem_object *obj;
1304 int ret;
1305
1306 obj = i915_gem_alloc_object(dev, 4096);
1307 if (obj == NULL) {
1308 DRM_ERROR("Failed to allocate status page\n");
1309 ret = -ENOMEM;
1310 goto err;
1311 }
1312
1313 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1314 if (ret)
1315 goto err_unref;
1316
1317 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1318 if (ret)
1319 goto err_unref;
1320
1321 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1322 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1323 if (ring->status_page.page_addr == NULL) {
1324 ret = -ENOMEM;
1325 goto err_unpin;
1326 }
1327 ring->status_page.obj = obj;
1328 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1329
1330 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1331 ring->name, ring->status_page.gfx_addr);
1332
1333 return 0;
1334
1335err_unpin:
1336 i915_gem_object_ggtt_unpin(obj);
1337err_unref:
1338 drm_gem_object_unreference(&obj->base);
1339err:
1340 return ret;
1341}
1342
1343static int init_phys_status_page(struct intel_ring_buffer *ring)
1344{
1345 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1346
1347 if (!dev_priv->status_page_dmah) {
1348 dev_priv->status_page_dmah =
1349 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1350 if (!dev_priv->status_page_dmah)
1351 return -ENOMEM;
1352 }
1353
1354 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1355 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1356
1357 return 0;
1358}
1359
1360static int intel_init_ring_buffer(struct drm_device *dev,
1361 struct intel_ring_buffer *ring)
1362{
1363 struct drm_i915_gem_object *obj;
1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 int ret;
1366
1367 ring->dev = dev;
1368 INIT_LIST_HEAD(&ring->active_list);
1369 INIT_LIST_HEAD(&ring->request_list);
1370 ring->size = 32 * PAGE_SIZE;
1371 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1372
1373 init_waitqueue_head(&ring->irq_queue);
1374
1375 if (I915_NEED_GFX_HWS(dev)) {
1376 ret = init_status_page(ring);
1377 if (ret)
1378 return ret;
1379 } else {
1380 BUG_ON(ring->id != RCS);
1381 ret = init_phys_status_page(ring);
1382 if (ret)
1383 return ret;
1384 }
1385
1386 obj = NULL;
1387 if (!HAS_LLC(dev))
1388 obj = i915_gem_object_create_stolen(dev, ring->size);
1389 if (obj == NULL)
1390 obj = i915_gem_alloc_object(dev, ring->size);
1391 if (obj == NULL) {
1392 DRM_ERROR("Failed to allocate ringbuffer\n");
1393 ret = -ENOMEM;
1394 goto err_hws;
1395 }
1396
1397 ring->obj = obj;
1398
1399 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1400 if (ret)
1401 goto err_unref;
1402
1403 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1404 if (ret)
1405 goto err_unpin;
1406
1407 ring->virtual_start =
1408 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1409 ring->size);
1410 if (ring->virtual_start == NULL) {
1411 DRM_ERROR("Failed to map ringbuffer.\n");
1412 ret = -EINVAL;
1413 goto err_unpin;
1414 }
1415
1416 ret = ring->init(ring);
1417 if (ret)
1418 goto err_unmap;
1419
1420 /* Workaround an erratum on the i830 which causes a hang if
1421 * the TAIL pointer points to within the last 2 cachelines
1422 * of the buffer.
1423 */
1424 ring->effective_size = ring->size;
1425 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1426 ring->effective_size -= 128;
1427
1428 i915_cmd_parser_init_ring(ring);
1429
1430 return 0;
1431
1432err_unmap:
1433 iounmap(ring->virtual_start);
1434err_unpin:
1435 i915_gem_object_ggtt_unpin(obj);
1436err_unref:
1437 drm_gem_object_unreference(&obj->base);
1438 ring->obj = NULL;
1439err_hws:
1440 cleanup_status_page(ring);
1441 return ret;
1442}
1443
1444void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1445{
1446 struct drm_i915_private *dev_priv;
1447 int ret;
1448
1449 if (ring->obj == NULL)
1450 return;
1451
1452 /* Disable the ring buffer. The ring must be idle at this point */
1453 dev_priv = ring->dev->dev_private;
1454 ret = intel_ring_idle(ring);
1455 if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1456 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1457 ring->name, ret);
1458
1459 I915_WRITE_CTL(ring, 0);
1460
1461 iounmap(ring->virtual_start);
1462
1463 i915_gem_object_ggtt_unpin(ring->obj);
1464 drm_gem_object_unreference(&ring->obj->base);
1465 ring->obj = NULL;
1466 ring->preallocated_lazy_request = NULL;
1467 ring->outstanding_lazy_seqno = 0;
1468
1469 if (ring->cleanup)
1470 ring->cleanup(ring);
1471
1472 cleanup_status_page(ring);
1473}
1474
1475static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1476{
1477 struct drm_i915_gem_request *request;
1478 u32 seqno = 0, tail;
1479 int ret;
1480
1481 if (ring->last_retired_head != -1) {
1482 ring->head = ring->last_retired_head;
1483 ring->last_retired_head = -1;
1484
1485 ring->space = ring_space(ring);
1486 if (ring->space >= n)
1487 return 0;
1488 }
1489
1490 list_for_each_entry(request, &ring->request_list, list) {
1491 int space;
1492
1493 if (request->tail == -1)
1494 continue;
1495
1496 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1497 if (space < 0)
1498 space += ring->size;
1499 if (space >= n) {
1500 seqno = request->seqno;
1501 tail = request->tail;
1502 break;
1503 }
1504
1505 /* Consume this request in case we need more space than
1506 * is available and so need to prevent a race between
1507 * updating last_retired_head and direct reads of
1508 * I915_RING_HEAD. It also provides a nice sanity check.
1509 */
1510 request->tail = -1;
1511 }
1512
1513 if (seqno == 0)
1514 return -ENOSPC;
1515
1516 ret = i915_wait_seqno(ring, seqno);
1517 if (ret)
1518 return ret;
1519
1520 ring->head = tail;
1521 ring->space = ring_space(ring);
1522 if (WARN_ON(ring->space < n))
1523 return -ENOSPC;
1524
1525 return 0;
1526}
1527
1528static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1529{
1530 struct drm_device *dev = ring->dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 unsigned long end;
1533 int ret;
1534
1535 ret = intel_ring_wait_request(ring, n);
1536 if (ret != -ENOSPC)
1537 return ret;
1538
1539 /* force the tail write in case we have been skipping them */
1540 __intel_ring_advance(ring);
1541
1542 trace_i915_ring_wait_begin(ring);
1543 /* With GEM the hangcheck timer should kick us out of the loop,
1544 * leaving it early runs the risk of corrupting GEM state (due
1545 * to running on almost untested codepaths). But on resume
1546 * timers don't work yet, so prevent a complete hang in that
1547 * case by choosing an insanely large timeout. */
1548 end = jiffies + 60 * HZ;
1549
1550 do {
1551 ring->head = I915_READ_HEAD(ring);
1552 ring->space = ring_space(ring);
1553 if (ring->space >= n) {
1554 trace_i915_ring_wait_end(ring);
1555 return 0;
1556 }
1557
1558 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1559 dev->primary->master) {
1560 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1561 if (master_priv->sarea_priv)
1562 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1563 }
1564
1565 msleep(1);
1566
1567 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1568 dev_priv->mm.interruptible);
1569 if (ret)
1570 return ret;
1571 } while (!time_after(jiffies, end));
1572 trace_i915_ring_wait_end(ring);
1573 return -EBUSY;
1574}
1575
1576static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1577{
1578 uint32_t __iomem *virt;
1579 int rem = ring->size - ring->tail;
1580
1581 if (ring->space < rem) {
1582 int ret = ring_wait_for_space(ring, rem);
1583 if (ret)
1584 return ret;
1585 }
1586
1587 virt = ring->virtual_start + ring->tail;
1588 rem /= 4;
1589 while (rem--)
1590 iowrite32(MI_NOOP, virt++);
1591
1592 ring->tail = 0;
1593 ring->space = ring_space(ring);
1594
1595 return 0;
1596}
1597
1598int intel_ring_idle(struct intel_ring_buffer *ring)
1599{
1600 u32 seqno;
1601 int ret;
1602
1603 /* We need to add any requests required to flush the objects and ring */
1604 if (ring->outstanding_lazy_seqno) {
1605 ret = i915_add_request(ring, NULL);
1606 if (ret)
1607 return ret;
1608 }
1609
1610 /* Wait upon the last request to be completed */
1611 if (list_empty(&ring->request_list))
1612 return 0;
1613
1614 seqno = list_entry(ring->request_list.prev,
1615 struct drm_i915_gem_request,
1616 list)->seqno;
1617
1618 return i915_wait_seqno(ring, seqno);
1619}
1620
1621static int
1622intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1623{
1624 if (ring->outstanding_lazy_seqno)
1625 return 0;
1626
1627 if (ring->preallocated_lazy_request == NULL) {
1628 struct drm_i915_gem_request *request;
1629
1630 request = kmalloc(sizeof(*request), GFP_KERNEL);
1631 if (request == NULL)
1632 return -ENOMEM;
1633
1634 ring->preallocated_lazy_request = request;
1635 }
1636
1637 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1638}
1639
1640static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1641 int bytes)
1642{
1643 int ret;
1644
1645 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1646 ret = intel_wrap_ring_buffer(ring);
1647 if (unlikely(ret))
1648 return ret;
1649 }
1650
1651 if (unlikely(ring->space < bytes)) {
1652 ret = ring_wait_for_space(ring, bytes);
1653 if (unlikely(ret))
1654 return ret;
1655 }
1656
1657 return 0;
1658}
1659
1660int intel_ring_begin(struct intel_ring_buffer *ring,
1661 int num_dwords)
1662{
1663 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1664 int ret;
1665
1666 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1667 dev_priv->mm.interruptible);
1668 if (ret)
1669 return ret;
1670
1671 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1672 if (ret)
1673 return ret;
1674
1675 /* Preallocate the olr before touching the ring */
1676 ret = intel_ring_alloc_seqno(ring);
1677 if (ret)
1678 return ret;
1679
1680 ring->space -= num_dwords * sizeof(uint32_t);
1681 return 0;
1682}
1683
1684/* Align the ring tail to a cacheline boundary */
1685int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1686{
1687 int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1688 int ret;
1689
1690 if (num_dwords == 0)
1691 return 0;
1692
1693 ret = intel_ring_begin(ring, num_dwords);
1694 if (ret)
1695 return ret;
1696
1697 while (num_dwords--)
1698 intel_ring_emit(ring, MI_NOOP);
1699
1700 intel_ring_advance(ring);
1701
1702 return 0;
1703}
1704
1705void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1706{
1707 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1708
1709 BUG_ON(ring->outstanding_lazy_seqno);
1710
1711 if (INTEL_INFO(ring->dev)->gen >= 6) {
1712 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1713 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1714 if (HAS_VEBOX(ring->dev))
1715 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1716 }
1717
1718 ring->set_seqno(ring, seqno);
1719 ring->hangcheck.seqno = seqno;
1720}
1721
1722static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1723 u32 value)
1724{
1725 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1726
1727 /* Every tail move must follow the sequence below */
1728
1729 /* Disable notification that the ring is IDLE. The GT
1730 * will then assume that it is busy and bring it out of rc6.
1731 */
1732 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1733 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1734
1735 /* Clear the context id. Here be magic! */
1736 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1737
1738 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1739 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1740 GEN6_BSD_SLEEP_INDICATOR) == 0,
1741 50))
1742 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1743
1744 /* Now that the ring is fully powered up, update the tail */
1745 I915_WRITE_TAIL(ring, value);
1746 POSTING_READ(RING_TAIL(ring->mmio_base));
1747
1748 /* Let the ring send IDLE messages to the GT again,
1749 * and so let it sleep to conserve power when idle.
1750 */
1751 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1752 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1753}
1754
1755static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1756 u32 invalidate, u32 flush)
1757{
1758 uint32_t cmd;
1759 int ret;
1760
1761 ret = intel_ring_begin(ring, 4);
1762 if (ret)
1763 return ret;
1764
1765 cmd = MI_FLUSH_DW;
1766 if (INTEL_INFO(ring->dev)->gen >= 8)
1767 cmd += 1;
1768 /*
1769 * Bspec vol 1c.5 - video engine command streamer:
1770 * "If ENABLED, all TLBs will be invalidated once the flush
1771 * operation is complete. This bit is only valid when the
1772 * Post-Sync Operation field is a value of 1h or 3h."
1773 */
1774 if (invalidate & I915_GEM_GPU_DOMAINS)
1775 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1776 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1777 intel_ring_emit(ring, cmd);
1778 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1779 if (INTEL_INFO(ring->dev)->gen >= 8) {
1780 intel_ring_emit(ring, 0); /* upper addr */
1781 intel_ring_emit(ring, 0); /* value */
1782 } else {
1783 intel_ring_emit(ring, 0);
1784 intel_ring_emit(ring, MI_NOOP);
1785 }
1786 intel_ring_advance(ring);
1787 return 0;
1788}
1789
1790static int
1791gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1792 u32 offset, u32 len,
1793 unsigned flags)
1794{
1795 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1796 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1797 !(flags & I915_DISPATCH_SECURE);
1798 int ret;
1799
1800 ret = intel_ring_begin(ring, 4);
1801 if (ret)
1802 return ret;
1803
1804 /* FIXME(BDW): Address space and security selectors. */
1805 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1806 intel_ring_emit(ring, offset);
1807 intel_ring_emit(ring, 0);
1808 intel_ring_emit(ring, MI_NOOP);
1809 intel_ring_advance(ring);
1810
1811 return 0;
1812}
1813
1814static int
1815hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1816 u32 offset, u32 len,
1817 unsigned flags)
1818{
1819 int ret;
1820
1821 ret = intel_ring_begin(ring, 2);
1822 if (ret)
1823 return ret;
1824
1825 intel_ring_emit(ring,
1826 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1827 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1828 /* bit0-7 is the length on GEN6+ */
1829 intel_ring_emit(ring, offset);
1830 intel_ring_advance(ring);
1831
1832 return 0;
1833}
1834
1835static int
1836gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1837 u32 offset, u32 len,
1838 unsigned flags)
1839{
1840 int ret;
1841
1842 ret = intel_ring_begin(ring, 2);
1843 if (ret)
1844 return ret;
1845
1846 intel_ring_emit(ring,
1847 MI_BATCH_BUFFER_START |
1848 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1849 /* bit0-7 is the length on GEN6+ */
1850 intel_ring_emit(ring, offset);
1851 intel_ring_advance(ring);
1852
1853 return 0;
1854}
1855
1856/* Blitter support (SandyBridge+) */
1857
1858static int gen6_ring_flush(struct intel_ring_buffer *ring,
1859 u32 invalidate, u32 flush)
1860{
1861 struct drm_device *dev = ring->dev;
1862 uint32_t cmd;
1863 int ret;
1864
1865 ret = intel_ring_begin(ring, 4);
1866 if (ret)
1867 return ret;
1868
1869 cmd = MI_FLUSH_DW;
1870 if (INTEL_INFO(ring->dev)->gen >= 8)
1871 cmd += 1;
1872 /*
1873 * Bspec vol 1c.3 - blitter engine command streamer:
1874 * "If ENABLED, all TLBs will be invalidated once the flush
1875 * operation is complete. This bit is only valid when the
1876 * Post-Sync Operation field is a value of 1h or 3h."
1877 */
1878 if (invalidate & I915_GEM_DOMAIN_RENDER)
1879 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1880 MI_FLUSH_DW_OP_STOREDW;
1881 intel_ring_emit(ring, cmd);
1882 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1883 if (INTEL_INFO(ring->dev)->gen >= 8) {
1884 intel_ring_emit(ring, 0); /* upper addr */
1885 intel_ring_emit(ring, 0); /* value */
1886 } else {
1887 intel_ring_emit(ring, 0);
1888 intel_ring_emit(ring, MI_NOOP);
1889 }
1890 intel_ring_advance(ring);
1891
1892 if (IS_GEN7(dev) && !invalidate && flush)
1893 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1894
1895 return 0;
1896}
1897
1898int intel_init_render_ring_buffer(struct drm_device *dev)
1899{
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1902
1903 ring->name = "render ring";
1904 ring->id = RCS;
1905 ring->mmio_base = RENDER_RING_BASE;
1906
1907 if (INTEL_INFO(dev)->gen >= 6) {
1908 ring->add_request = gen6_add_request;
1909 ring->flush = gen7_render_ring_flush;
1910 if (INTEL_INFO(dev)->gen == 6)
1911 ring->flush = gen6_render_ring_flush;
1912 if (INTEL_INFO(dev)->gen >= 8) {
1913 ring->flush = gen8_render_ring_flush;
1914 ring->irq_get = gen8_ring_get_irq;
1915 ring->irq_put = gen8_ring_put_irq;
1916 } else {
1917 ring->irq_get = gen6_ring_get_irq;
1918 ring->irq_put = gen6_ring_put_irq;
1919 }
1920 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1921 ring->get_seqno = gen6_ring_get_seqno;
1922 ring->set_seqno = ring_set_seqno;
1923 ring->sync_to = gen6_ring_sync;
1924 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1925 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1926 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1927 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1928 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1929 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1930 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1931 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1932 } else if (IS_GEN5(dev)) {
1933 ring->add_request = pc_render_add_request;
1934 ring->flush = gen4_render_ring_flush;
1935 ring->get_seqno = pc_render_get_seqno;
1936 ring->set_seqno = pc_render_set_seqno;
1937 ring->irq_get = gen5_ring_get_irq;
1938 ring->irq_put = gen5_ring_put_irq;
1939 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1940 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1941 } else {
1942 ring->add_request = i9xx_add_request;
1943 if (INTEL_INFO(dev)->gen < 4)
1944 ring->flush = gen2_render_ring_flush;
1945 else
1946 ring->flush = gen4_render_ring_flush;
1947 ring->get_seqno = ring_get_seqno;
1948 ring->set_seqno = ring_set_seqno;
1949 if (IS_GEN2(dev)) {
1950 ring->irq_get = i8xx_ring_get_irq;
1951 ring->irq_put = i8xx_ring_put_irq;
1952 } else {
1953 ring->irq_get = i9xx_ring_get_irq;
1954 ring->irq_put = i9xx_ring_put_irq;
1955 }
1956 ring->irq_enable_mask = I915_USER_INTERRUPT;
1957 }
1958 ring->write_tail = ring_write_tail;
1959 if (IS_HASWELL(dev))
1960 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1961 else if (IS_GEN8(dev))
1962 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1963 else if (INTEL_INFO(dev)->gen >= 6)
1964 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1965 else if (INTEL_INFO(dev)->gen >= 4)
1966 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1967 else if (IS_I830(dev) || IS_845G(dev))
1968 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1969 else
1970 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1971 ring->init = init_render_ring;
1972 ring->cleanup = render_ring_cleanup;
1973
1974 /* Workaround batchbuffer to combat CS tlb bug. */
1975 if (HAS_BROKEN_CS_TLB(dev)) {
1976 struct drm_i915_gem_object *obj;
1977 int ret;
1978
1979 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1980 if (obj == NULL) {
1981 DRM_ERROR("Failed to allocate batch bo\n");
1982 return -ENOMEM;
1983 }
1984
1985 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1986 if (ret != 0) {
1987 drm_gem_object_unreference(&obj->base);
1988 DRM_ERROR("Failed to ping batch bo\n");
1989 return ret;
1990 }
1991
1992 ring->scratch.obj = obj;
1993 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1994 }
1995
1996 return intel_init_ring_buffer(dev, ring);
1997}
1998
1999int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2000{
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2003 int ret;
2004
2005 ring->name = "render ring";
2006 ring->id = RCS;
2007 ring->mmio_base = RENDER_RING_BASE;
2008
2009 if (INTEL_INFO(dev)->gen >= 6) {
2010 /* non-kms not supported on gen6+ */
2011 return -ENODEV;
2012 }
2013
2014 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2015 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2016 * the special gen5 functions. */
2017 ring->add_request = i9xx_add_request;
2018 if (INTEL_INFO(dev)->gen < 4)
2019 ring->flush = gen2_render_ring_flush;
2020 else
2021 ring->flush = gen4_render_ring_flush;
2022 ring->get_seqno = ring_get_seqno;
2023 ring->set_seqno = ring_set_seqno;
2024 if (IS_GEN2(dev)) {
2025 ring->irq_get = i8xx_ring_get_irq;
2026 ring->irq_put = i8xx_ring_put_irq;
2027 } else {
2028 ring->irq_get = i9xx_ring_get_irq;
2029 ring->irq_put = i9xx_ring_put_irq;
2030 }
2031 ring->irq_enable_mask = I915_USER_INTERRUPT;
2032 ring->write_tail = ring_write_tail;
2033 if (INTEL_INFO(dev)->gen >= 4)
2034 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2035 else if (IS_I830(dev) || IS_845G(dev))
2036 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2037 else
2038 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2039 ring->init = init_render_ring;
2040 ring->cleanup = render_ring_cleanup;
2041
2042 ring->dev = dev;
2043 INIT_LIST_HEAD(&ring->active_list);
2044 INIT_LIST_HEAD(&ring->request_list);
2045
2046 ring->size = size;
2047 ring->effective_size = ring->size;
2048 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2049 ring->effective_size -= 128;
2050
2051 ring->virtual_start = ioremap_wc(start, size);
2052 if (ring->virtual_start == NULL) {
2053 DRM_ERROR("can not ioremap virtual address for"
2054 " ring buffer\n");
2055 return -ENOMEM;
2056 }
2057
2058 if (!I915_NEED_GFX_HWS(dev)) {
2059 ret = init_phys_status_page(ring);
2060 if (ret)
2061 return ret;
2062 }
2063
2064 return 0;
2065}
2066
2067int intel_init_bsd_ring_buffer(struct drm_device *dev)
2068{
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2071
2072 ring->name = "bsd ring";
2073 ring->id = VCS;
2074
2075 ring->write_tail = ring_write_tail;
2076 if (INTEL_INFO(dev)->gen >= 6) {
2077 ring->mmio_base = GEN6_BSD_RING_BASE;
2078 /* gen6 bsd needs a special wa for tail updates */
2079 if (IS_GEN6(dev))
2080 ring->write_tail = gen6_bsd_ring_write_tail;
2081 ring->flush = gen6_bsd_ring_flush;
2082 ring->add_request = gen6_add_request;
2083 ring->get_seqno = gen6_ring_get_seqno;
2084 ring->set_seqno = ring_set_seqno;
2085 if (INTEL_INFO(dev)->gen >= 8) {
2086 ring->irq_enable_mask =
2087 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2088 ring->irq_get = gen8_ring_get_irq;
2089 ring->irq_put = gen8_ring_put_irq;
2090 ring->dispatch_execbuffer =
2091 gen8_ring_dispatch_execbuffer;
2092 } else {
2093 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2094 ring->irq_get = gen6_ring_get_irq;
2095 ring->irq_put = gen6_ring_put_irq;
2096 ring->dispatch_execbuffer =
2097 gen6_ring_dispatch_execbuffer;
2098 }
2099 ring->sync_to = gen6_ring_sync;
2100 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2101 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2102 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2103 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2104 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2105 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2106 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2107 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2108 } else {
2109 ring->mmio_base = BSD_RING_BASE;
2110 ring->flush = bsd_ring_flush;
2111 ring->add_request = i9xx_add_request;
2112 ring->get_seqno = ring_get_seqno;
2113 ring->set_seqno = ring_set_seqno;
2114 if (IS_GEN5(dev)) {
2115 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2116 ring->irq_get = gen5_ring_get_irq;
2117 ring->irq_put = gen5_ring_put_irq;
2118 } else {
2119 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2120 ring->irq_get = i9xx_ring_get_irq;
2121 ring->irq_put = i9xx_ring_put_irq;
2122 }
2123 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2124 }
2125 ring->init = init_ring_common;
2126
2127 return intel_init_ring_buffer(dev, ring);
2128}
2129
2130int intel_init_blt_ring_buffer(struct drm_device *dev)
2131{
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2134
2135 ring->name = "blitter ring";
2136 ring->id = BCS;
2137
2138 ring->mmio_base = BLT_RING_BASE;
2139 ring->write_tail = ring_write_tail;
2140 ring->flush = gen6_ring_flush;
2141 ring->add_request = gen6_add_request;
2142 ring->get_seqno = gen6_ring_get_seqno;
2143 ring->set_seqno = ring_set_seqno;
2144 if (INTEL_INFO(dev)->gen >= 8) {
2145 ring->irq_enable_mask =
2146 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2147 ring->irq_get = gen8_ring_get_irq;
2148 ring->irq_put = gen8_ring_put_irq;
2149 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2150 } else {
2151 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2152 ring->irq_get = gen6_ring_get_irq;
2153 ring->irq_put = gen6_ring_put_irq;
2154 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2155 }
2156 ring->sync_to = gen6_ring_sync;
2157 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2158 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2159 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2160 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2161 ring->signal_mbox[RCS] = GEN6_RBSYNC;
2162 ring->signal_mbox[VCS] = GEN6_VBSYNC;
2163 ring->signal_mbox[BCS] = GEN6_NOSYNC;
2164 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2165 ring->init = init_ring_common;
2166
2167 return intel_init_ring_buffer(dev, ring);
2168}
2169
2170int intel_init_vebox_ring_buffer(struct drm_device *dev)
2171{
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2174
2175 ring->name = "video enhancement ring";
2176 ring->id = VECS;
2177
2178 ring->mmio_base = VEBOX_RING_BASE;
2179 ring->write_tail = ring_write_tail;
2180 ring->flush = gen6_ring_flush;
2181 ring->add_request = gen6_add_request;
2182 ring->get_seqno = gen6_ring_get_seqno;
2183 ring->set_seqno = ring_set_seqno;
2184
2185 if (INTEL_INFO(dev)->gen >= 8) {
2186 ring->irq_enable_mask =
2187 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2188 ring->irq_get = gen8_ring_get_irq;
2189 ring->irq_put = gen8_ring_put_irq;
2190 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2191 } else {
2192 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2193 ring->irq_get = hsw_vebox_get_irq;
2194 ring->irq_put = hsw_vebox_put_irq;
2195 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2196 }
2197 ring->sync_to = gen6_ring_sync;
2198 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2199 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2200 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2201 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2202 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2203 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2204 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2205 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2206 ring->init = init_ring_common;
2207
2208 return intel_init_ring_buffer(dev, ring);
2209}
2210
2211int
2212intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2213{
2214 int ret;
2215
2216 if (!ring->gpu_caches_dirty)
2217 return 0;
2218
2219 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2220 if (ret)
2221 return ret;
2222
2223 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2224
2225 ring->gpu_caches_dirty = false;
2226 return 0;
2227}
2228
2229int
2230intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2231{
2232 uint32_t flush_domains;
2233 int ret;
2234
2235 flush_domains = 0;
2236 if (ring->gpu_caches_dirty)
2237 flush_domains = I915_GEM_GPU_DOMAINS;
2238
2239 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2240 if (ret)
2241 return ret;
2242
2243 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2244
2245 ring->gpu_caches_dirty = false;
2246 return 0;
2247}