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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5#include <linux/bits.h>
6#include <linux/gpio/driver.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13
14#define PCH_EDGE_FALLING 0
15#define PCH_EDGE_RISING 1
16#define PCH_LEVEL_L 2
17#define PCH_LEVEL_H 3
18#define PCH_EDGE_BOTH 4
19#define PCH_IM_MASK GENMASK(2, 0)
20
21#define PCH_IRQ_BASE 24
22
23struct pch_regs {
24 u32 ien;
25 u32 istatus;
26 u32 idisp;
27 u32 iclr;
28 u32 imask;
29 u32 imaskclr;
30 u32 po;
31 u32 pi;
32 u32 pm;
33 u32 im0;
34 u32 im1;
35 u32 reserved[3];
36 u32 gpio_use_sel;
37 u32 reset;
38};
39
40#define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803
41#define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014
42#define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043
43#define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803
44
45enum pch_type_t {
46 INTEL_EG20T_PCH,
47 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
48 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
49};
50
51/* Specifies number of GPIO PINS */
52static int gpio_pins[] = {
53 [INTEL_EG20T_PCH] = 12,
54 [OKISEMI_ML7223m_IOH] = 8,
55 [OKISEMI_ML7223n_IOH] = 8,
56};
57
58/**
59 * struct pch_gpio_reg_data - The register store data.
60 * @ien_reg: To store contents of IEN register.
61 * @imask_reg: To store contents of IMASK register.
62 * @po_reg: To store contents of PO register.
63 * @pm_reg: To store contents of PM register.
64 * @im0_reg: To store contents of IM0 register.
65 * @im1_reg: To store contents of IM1 register.
66 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
67 * (Only ML7223 Bus-n)
68 */
69struct pch_gpio_reg_data {
70 u32 ien_reg;
71 u32 imask_reg;
72 u32 po_reg;
73 u32 pm_reg;
74 u32 im0_reg;
75 u32 im1_reg;
76 u32 gpio_use_sel_reg;
77};
78
79/**
80 * struct pch_gpio - GPIO private data structure.
81 * @base: PCI base address of Memory mapped I/O register.
82 * @reg: Memory mapped PCH GPIO register list.
83 * @dev: Pointer to device structure.
84 * @gpio: Data for GPIO infrastructure.
85 * @pch_gpio_reg: Memory mapped Register data is saved here
86 * when suspend.
87 * @irq_base: Save base of IRQ number for interrupt
88 * @ioh: IOH ID
89 * @spinlock: Used for register access protection
90 */
91struct pch_gpio {
92 void __iomem *base;
93 struct pch_regs __iomem *reg;
94 struct device *dev;
95 struct gpio_chip gpio;
96 struct pch_gpio_reg_data pch_gpio_reg;
97 int irq_base;
98 enum pch_type_t ioh;
99 spinlock_t spinlock;
100};
101
102static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
103{
104 u32 reg_val;
105 struct pch_gpio *chip = gpiochip_get_data(gpio);
106 unsigned long flags;
107
108 spin_lock_irqsave(&chip->spinlock, flags);
109 reg_val = ioread32(&chip->reg->po);
110 if (val)
111 reg_val |= BIT(nr);
112 else
113 reg_val &= ~BIT(nr);
114
115 iowrite32(reg_val, &chip->reg->po);
116 spin_unlock_irqrestore(&chip->spinlock, flags);
117}
118
119static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
120{
121 struct pch_gpio *chip = gpiochip_get_data(gpio);
122
123 return !!(ioread32(&chip->reg->pi) & BIT(nr));
124}
125
126static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
127 int val)
128{
129 struct pch_gpio *chip = gpiochip_get_data(gpio);
130 u32 pm;
131 u32 reg_val;
132 unsigned long flags;
133
134 spin_lock_irqsave(&chip->spinlock, flags);
135
136 reg_val = ioread32(&chip->reg->po);
137 if (val)
138 reg_val |= BIT(nr);
139 else
140 reg_val &= ~BIT(nr);
141 iowrite32(reg_val, &chip->reg->po);
142
143 pm = ioread32(&chip->reg->pm);
144 pm &= BIT(gpio_pins[chip->ioh]) - 1;
145 pm |= BIT(nr);
146 iowrite32(pm, &chip->reg->pm);
147
148 spin_unlock_irqrestore(&chip->spinlock, flags);
149
150 return 0;
151}
152
153static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
154{
155 struct pch_gpio *chip = gpiochip_get_data(gpio);
156 u32 pm;
157 unsigned long flags;
158
159 spin_lock_irqsave(&chip->spinlock, flags);
160 pm = ioread32(&chip->reg->pm);
161 pm &= BIT(gpio_pins[chip->ioh]) - 1;
162 pm &= ~BIT(nr);
163 iowrite32(pm, &chip->reg->pm);
164 spin_unlock_irqrestore(&chip->spinlock, flags);
165
166 return 0;
167}
168
169/*
170 * Save register configuration and disable interrupts.
171 */
172static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
173{
174 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
175 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
176 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
177 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
178 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
179 if (chip->ioh == INTEL_EG20T_PCH)
180 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
181 if (chip->ioh == OKISEMI_ML7223n_IOH)
182 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
183}
184
185/*
186 * This function restores the register configuration of the GPIO device.
187 */
188static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
189{
190 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
191 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
192 /* to store contents of PO register */
193 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
194 /* to store contents of PM register */
195 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
196 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
197 if (chip->ioh == INTEL_EG20T_PCH)
198 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
199 if (chip->ioh == OKISEMI_ML7223n_IOH)
200 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
201}
202
203static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
204{
205 struct pch_gpio *chip = gpiochip_get_data(gpio);
206
207 return chip->irq_base + offset;
208}
209
210static void pch_gpio_setup(struct pch_gpio *chip)
211{
212 struct gpio_chip *gpio = &chip->gpio;
213
214 gpio->label = dev_name(chip->dev);
215 gpio->parent = chip->dev;
216 gpio->owner = THIS_MODULE;
217 gpio->direction_input = pch_gpio_direction_input;
218 gpio->get = pch_gpio_get;
219 gpio->direction_output = pch_gpio_direction_output;
220 gpio->set = pch_gpio_set;
221 gpio->base = -1;
222 gpio->ngpio = gpio_pins[chip->ioh];
223 gpio->can_sleep = false;
224 gpio->to_irq = pch_gpio_to_irq;
225}
226
227static int pch_irq_type(struct irq_data *d, unsigned int type)
228{
229 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
230 struct pch_gpio *chip = gc->private;
231 u32 im, im_pos, val;
232 u32 __iomem *im_reg;
233 unsigned long flags;
234 int ch, irq = d->irq;
235
236 ch = irq - chip->irq_base;
237 if (irq < chip->irq_base + 8) {
238 im_reg = &chip->reg->im0;
239 im_pos = ch - 0;
240 } else {
241 im_reg = &chip->reg->im1;
242 im_pos = ch - 8;
243 }
244 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
245
246 switch (type) {
247 case IRQ_TYPE_EDGE_RISING:
248 val = PCH_EDGE_RISING;
249 break;
250 case IRQ_TYPE_EDGE_FALLING:
251 val = PCH_EDGE_FALLING;
252 break;
253 case IRQ_TYPE_EDGE_BOTH:
254 val = PCH_EDGE_BOTH;
255 break;
256 case IRQ_TYPE_LEVEL_HIGH:
257 val = PCH_LEVEL_H;
258 break;
259 case IRQ_TYPE_LEVEL_LOW:
260 val = PCH_LEVEL_L;
261 break;
262 default:
263 return 0;
264 }
265
266 spin_lock_irqsave(&chip->spinlock, flags);
267
268 /* Set interrupt mode */
269 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
270 iowrite32(im | (val << (im_pos * 4)), im_reg);
271
272 /* And the handler */
273 if (type & IRQ_TYPE_LEVEL_MASK)
274 irq_set_handler_locked(d, handle_level_irq);
275 else if (type & IRQ_TYPE_EDGE_BOTH)
276 irq_set_handler_locked(d, handle_edge_irq);
277
278 spin_unlock_irqrestore(&chip->spinlock, flags);
279 return 0;
280}
281
282static void pch_irq_unmask(struct irq_data *d)
283{
284 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
285 struct pch_gpio *chip = gc->private;
286
287 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
288}
289
290static void pch_irq_mask(struct irq_data *d)
291{
292 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
293 struct pch_gpio *chip = gc->private;
294
295 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
296}
297
298static void pch_irq_ack(struct irq_data *d)
299{
300 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
301 struct pch_gpio *chip = gc->private;
302
303 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
304}
305
306static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
307{
308 struct pch_gpio *chip = dev_id;
309 unsigned long reg_val = ioread32(&chip->reg->istatus);
310 int i;
311
312 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
313
314 reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
315
316 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
317 generic_handle_irq(chip->irq_base + i);
318
319 return IRQ_RETVAL(reg_val);
320}
321
322static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
323 unsigned int irq_start,
324 unsigned int num)
325{
326 struct irq_chip_generic *gc;
327 struct irq_chip_type *ct;
328 int rv;
329
330 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
331 chip->base, handle_simple_irq);
332 if (!gc)
333 return -ENOMEM;
334
335 gc->private = chip;
336 ct = gc->chip_types;
337
338 ct->chip.irq_ack = pch_irq_ack;
339 ct->chip.irq_mask = pch_irq_mask;
340 ct->chip.irq_unmask = pch_irq_unmask;
341 ct->chip.irq_set_type = pch_irq_type;
342
343 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
344 IRQ_GC_INIT_MASK_CACHE,
345 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
346
347 return rv;
348}
349
350static int pch_gpio_probe(struct pci_dev *pdev,
351 const struct pci_device_id *id)
352{
353 struct device *dev = &pdev->dev;
354 s32 ret;
355 struct pch_gpio *chip;
356 int irq_base;
357
358 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
359 if (chip == NULL)
360 return -ENOMEM;
361
362 chip->dev = dev;
363 ret = pcim_enable_device(pdev);
364 if (ret)
365 return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
366
367 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
368 if (ret)
369 return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
370
371 chip->base = pcim_iomap_table(pdev)[1];
372 chip->ioh = id->driver_data;
373 chip->reg = chip->base;
374 pci_set_drvdata(pdev, chip);
375 spin_lock_init(&chip->spinlock);
376 pch_gpio_setup(chip);
377
378 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
379 if (ret)
380 return dev_err_probe(dev, ret, "Failed to register GPIO\n");
381
382 irq_base = devm_irq_alloc_descs(dev, -1, 0,
383 gpio_pins[chip->ioh], NUMA_NO_NODE);
384 if (irq_base < 0) {
385 dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
386 chip->irq_base = -1;
387 return 0;
388 }
389 chip->irq_base = irq_base;
390
391 /* Mask all interrupts, but enable them */
392 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
393 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
394
395 ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
396 IRQF_SHARED, KBUILD_MODNAME, chip);
397 if (ret)
398 return dev_err_probe(dev, ret, "Failed to request IRQ\n");
399
400 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
401}
402
403static int __maybe_unused pch_gpio_suspend(struct device *dev)
404{
405 struct pch_gpio *chip = dev_get_drvdata(dev);
406 unsigned long flags;
407
408 spin_lock_irqsave(&chip->spinlock, flags);
409 pch_gpio_save_reg_conf(chip);
410 spin_unlock_irqrestore(&chip->spinlock, flags);
411
412 return 0;
413}
414
415static int __maybe_unused pch_gpio_resume(struct device *dev)
416{
417 struct pch_gpio *chip = dev_get_drvdata(dev);
418 unsigned long flags;
419
420 spin_lock_irqsave(&chip->spinlock, flags);
421 iowrite32(0x01, &chip->reg->reset);
422 iowrite32(0x00, &chip->reg->reset);
423 pch_gpio_restore_reg_conf(chip);
424 spin_unlock_irqrestore(&chip->spinlock, flags);
425
426 return 0;
427}
428
429static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
430
431static const struct pci_device_id pch_gpio_pcidev_id[] = {
432 { PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
433 { PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
434 { PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
435 { PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
436 { }
437};
438MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
439
440static struct pci_driver pch_gpio_driver = {
441 .name = "pch_gpio",
442 .id_table = pch_gpio_pcidev_id,
443 .probe = pch_gpio_probe,
444 .driver = {
445 .pm = &pch_gpio_pm_ops,
446 },
447};
448
449module_pci_driver(pch_gpio_driver);
450
451MODULE_DESCRIPTION("PCH GPIO PCI Driver");
452MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/gpio.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23
24#define PCH_EDGE_FALLING 0
25#define PCH_EDGE_RISING BIT(0)
26#define PCH_LEVEL_L BIT(1)
27#define PCH_LEVEL_H (BIT(0) | BIT(1))
28#define PCH_EDGE_BOTH BIT(2)
29#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
30
31#define PCH_IRQ_BASE 24
32
33struct pch_regs {
34 u32 ien;
35 u32 istatus;
36 u32 idisp;
37 u32 iclr;
38 u32 imask;
39 u32 imaskclr;
40 u32 po;
41 u32 pi;
42 u32 pm;
43 u32 im0;
44 u32 im1;
45 u32 reserved[3];
46 u32 gpio_use_sel;
47 u32 reset;
48};
49
50enum pch_type_t {
51 INTEL_EG20T_PCH,
52 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
53 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
54};
55
56/* Specifies number of GPIO PINS */
57static int gpio_pins[] = {
58 [INTEL_EG20T_PCH] = 12,
59 [OKISEMI_ML7223m_IOH] = 8,
60 [OKISEMI_ML7223n_IOH] = 8,
61};
62
63/**
64 * struct pch_gpio_reg_data - The register store data.
65 * @ien_reg: To store contents of IEN register.
66 * @imask_reg: To store contents of IMASK register.
67 * @po_reg: To store contents of PO register.
68 * @pm_reg: To store contents of PM register.
69 * @im0_reg: To store contents of IM0 register.
70 * @im1_reg: To store contents of IM1 register.
71 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
72 * (Only ML7223 Bus-n)
73 */
74struct pch_gpio_reg_data {
75 u32 ien_reg;
76 u32 imask_reg;
77 u32 po_reg;
78 u32 pm_reg;
79 u32 im0_reg;
80 u32 im1_reg;
81 u32 gpio_use_sel_reg;
82};
83
84/**
85 * struct pch_gpio - GPIO private data structure.
86 * @base: PCI base address of Memory mapped I/O register.
87 * @reg: Memory mapped PCH GPIO register list.
88 * @dev: Pointer to device structure.
89 * @gpio: Data for GPIO infrastructure.
90 * @pch_gpio_reg: Memory mapped Register data is saved here
91 * when suspend.
92 * @lock: Used for register access protection
93 * @irq_base: Save base of IRQ number for interrupt
94 * @ioh: IOH ID
95 * @spinlock: Used for register access protection
96 */
97struct pch_gpio {
98 void __iomem *base;
99 struct pch_regs __iomem *reg;
100 struct device *dev;
101 struct gpio_chip gpio;
102 struct pch_gpio_reg_data pch_gpio_reg;
103 int irq_base;
104 enum pch_type_t ioh;
105 spinlock_t spinlock;
106};
107
108static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
109{
110 u32 reg_val;
111 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
112 unsigned long flags;
113
114 spin_lock_irqsave(&chip->spinlock, flags);
115 reg_val = ioread32(&chip->reg->po);
116 if (val)
117 reg_val |= (1 << nr);
118 else
119 reg_val &= ~(1 << nr);
120
121 iowrite32(reg_val, &chip->reg->po);
122 spin_unlock_irqrestore(&chip->spinlock, flags);
123}
124
125static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
126{
127 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
128
129 return ioread32(&chip->reg->pi) & (1 << nr);
130}
131
132static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
133 int val)
134{
135 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
136 u32 pm;
137 u32 reg_val;
138 unsigned long flags;
139
140 spin_lock_irqsave(&chip->spinlock, flags);
141
142 reg_val = ioread32(&chip->reg->po);
143 if (val)
144 reg_val |= (1 << nr);
145 else
146 reg_val &= ~(1 << nr);
147 iowrite32(reg_val, &chip->reg->po);
148
149 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
150 pm |= (1 << nr);
151 iowrite32(pm, &chip->reg->pm);
152
153 spin_unlock_irqrestore(&chip->spinlock, flags);
154
155 return 0;
156}
157
158static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
159{
160 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
161 u32 pm;
162 unsigned long flags;
163
164 spin_lock_irqsave(&chip->spinlock, flags);
165 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
166 pm &= ~(1 << nr);
167 iowrite32(pm, &chip->reg->pm);
168 spin_unlock_irqrestore(&chip->spinlock, flags);
169
170 return 0;
171}
172
173/*
174 * Save register configuration and disable interrupts.
175 */
176static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
177{
178 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
179 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
180 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
181 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
182 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
183 if (chip->ioh == INTEL_EG20T_PCH)
184 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
185 if (chip->ioh == OKISEMI_ML7223n_IOH)
186 chip->pch_gpio_reg.gpio_use_sel_reg =\
187 ioread32(&chip->reg->gpio_use_sel);
188}
189
190/*
191 * This function restores the register configuration of the GPIO device.
192 */
193static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
194{
195 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
196 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
197 /* to store contents of PO register */
198 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
199 /* to store contents of PM register */
200 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
201 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
202 if (chip->ioh == INTEL_EG20T_PCH)
203 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
204 if (chip->ioh == OKISEMI_ML7223n_IOH)
205 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
206 &chip->reg->gpio_use_sel);
207}
208
209static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
210{
211 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
212 return chip->irq_base + offset;
213}
214
215static void pch_gpio_setup(struct pch_gpio *chip)
216{
217 struct gpio_chip *gpio = &chip->gpio;
218
219 gpio->label = dev_name(chip->dev);
220 gpio->dev = chip->dev;
221 gpio->owner = THIS_MODULE;
222 gpio->direction_input = pch_gpio_direction_input;
223 gpio->get = pch_gpio_get;
224 gpio->direction_output = pch_gpio_direction_output;
225 gpio->set = pch_gpio_set;
226 gpio->dbg_show = NULL;
227 gpio->base = -1;
228 gpio->ngpio = gpio_pins[chip->ioh];
229 gpio->can_sleep = false;
230 gpio->to_irq = pch_gpio_to_irq;
231}
232
233static int pch_irq_type(struct irq_data *d, unsigned int type)
234{
235 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
236 struct pch_gpio *chip = gc->private;
237 u32 im, im_pos, val;
238 u32 __iomem *im_reg;
239 unsigned long flags;
240 int ch, irq = d->irq;
241
242 ch = irq - chip->irq_base;
243 if (irq <= chip->irq_base + 7) {
244 im_reg = &chip->reg->im0;
245 im_pos = ch;
246 } else {
247 im_reg = &chip->reg->im1;
248 im_pos = ch - 8;
249 }
250 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
251 __func__, irq, type, ch, im_pos);
252
253 spin_lock_irqsave(&chip->spinlock, flags);
254
255 switch (type) {
256 case IRQ_TYPE_EDGE_RISING:
257 val = PCH_EDGE_RISING;
258 break;
259 case IRQ_TYPE_EDGE_FALLING:
260 val = PCH_EDGE_FALLING;
261 break;
262 case IRQ_TYPE_EDGE_BOTH:
263 val = PCH_EDGE_BOTH;
264 break;
265 case IRQ_TYPE_LEVEL_HIGH:
266 val = PCH_LEVEL_H;
267 break;
268 case IRQ_TYPE_LEVEL_LOW:
269 val = PCH_LEVEL_L;
270 break;
271 default:
272 goto unlock;
273 }
274
275 /* Set interrupt mode */
276 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
277 iowrite32(im | (val << (im_pos * 4)), im_reg);
278
279 /* And the handler */
280 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
281 __irq_set_handler_locked(d->irq, handle_level_irq);
282 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
283 __irq_set_handler_locked(d->irq, handle_edge_irq);
284
285unlock:
286 spin_unlock_irqrestore(&chip->spinlock, flags);
287 return 0;
288}
289
290static void pch_irq_unmask(struct irq_data *d)
291{
292 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
293 struct pch_gpio *chip = gc->private;
294
295 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
296}
297
298static void pch_irq_mask(struct irq_data *d)
299{
300 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
301 struct pch_gpio *chip = gc->private;
302
303 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
304}
305
306static void pch_irq_ack(struct irq_data *d)
307{
308 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
309 struct pch_gpio *chip = gc->private;
310
311 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
312}
313
314static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
315{
316 struct pch_gpio *chip = dev_id;
317 u32 reg_val = ioread32(&chip->reg->istatus);
318 int i, ret = IRQ_NONE;
319
320 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
321 if (reg_val & BIT(i)) {
322 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
323 __func__, i, irq, reg_val);
324 generic_handle_irq(chip->irq_base + i);
325 ret = IRQ_HANDLED;
326 }
327 }
328 return ret;
329}
330
331static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
332 unsigned int irq_start, unsigned int num)
333{
334 struct irq_chip_generic *gc;
335 struct irq_chip_type *ct;
336
337 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
338 handle_simple_irq);
339 gc->private = chip;
340 ct = gc->chip_types;
341
342 ct->chip.irq_ack = pch_irq_ack;
343 ct->chip.irq_mask = pch_irq_mask;
344 ct->chip.irq_unmask = pch_irq_unmask;
345 ct->chip.irq_set_type = pch_irq_type;
346
347 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
348 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
349}
350
351static int pch_gpio_probe(struct pci_dev *pdev,
352 const struct pci_device_id *id)
353{
354 s32 ret;
355 struct pch_gpio *chip;
356 int irq_base;
357 u32 msk;
358
359 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
360 if (chip == NULL)
361 return -ENOMEM;
362
363 chip->dev = &pdev->dev;
364 ret = pci_enable_device(pdev);
365 if (ret) {
366 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
367 goto err_pci_enable;
368 }
369
370 ret = pci_request_regions(pdev, KBUILD_MODNAME);
371 if (ret) {
372 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
373 goto err_request_regions;
374 }
375
376 chip->base = pci_iomap(pdev, 1, 0);
377 if (!chip->base) {
378 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
379 ret = -ENOMEM;
380 goto err_iomap;
381 }
382
383 if (pdev->device == 0x8803)
384 chip->ioh = INTEL_EG20T_PCH;
385 else if (pdev->device == 0x8014)
386 chip->ioh = OKISEMI_ML7223m_IOH;
387 else if (pdev->device == 0x8043)
388 chip->ioh = OKISEMI_ML7223n_IOH;
389
390 chip->reg = chip->base;
391 pci_set_drvdata(pdev, chip);
392 spin_lock_init(&chip->spinlock);
393 pch_gpio_setup(chip);
394 ret = gpiochip_add(&chip->gpio);
395 if (ret) {
396 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
397 goto err_gpiochip_add;
398 }
399
400 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
401 if (irq_base < 0) {
402 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
403 chip->irq_base = -1;
404 goto end;
405 }
406 chip->irq_base = irq_base;
407
408 /* Mask all interrupts, but enable them */
409 msk = (1 << gpio_pins[chip->ioh]) - 1;
410 iowrite32(msk, &chip->reg->imask);
411 iowrite32(msk, &chip->reg->ien);
412
413 ret = request_irq(pdev->irq, pch_gpio_handler,
414 IRQF_SHARED, KBUILD_MODNAME, chip);
415 if (ret != 0) {
416 dev_err(&pdev->dev,
417 "%s request_irq failed\n", __func__);
418 goto err_request_irq;
419 }
420
421 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
422
423end:
424 return 0;
425
426err_request_irq:
427 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
428
429 if (gpiochip_remove(&chip->gpio))
430 dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
431
432err_gpiochip_add:
433 pci_iounmap(pdev, chip->base);
434
435err_iomap:
436 pci_release_regions(pdev);
437
438err_request_regions:
439 pci_disable_device(pdev);
440
441err_pci_enable:
442 kfree(chip);
443 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
444 return ret;
445}
446
447static void pch_gpio_remove(struct pci_dev *pdev)
448{
449 int err;
450 struct pch_gpio *chip = pci_get_drvdata(pdev);
451
452 if (chip->irq_base != -1) {
453 free_irq(pdev->irq, chip);
454
455 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
456 }
457
458 err = gpiochip_remove(&chip->gpio);
459 if (err)
460 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
461
462 pci_iounmap(pdev, chip->base);
463 pci_release_regions(pdev);
464 pci_disable_device(pdev);
465 kfree(chip);
466}
467
468#ifdef CONFIG_PM
469static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
470{
471 s32 ret;
472 struct pch_gpio *chip = pci_get_drvdata(pdev);
473 unsigned long flags;
474
475 spin_lock_irqsave(&chip->spinlock, flags);
476 pch_gpio_save_reg_conf(chip);
477 spin_unlock_irqrestore(&chip->spinlock, flags);
478
479 ret = pci_save_state(pdev);
480 if (ret) {
481 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
482 return ret;
483 }
484 pci_disable_device(pdev);
485 pci_set_power_state(pdev, PCI_D0);
486 ret = pci_enable_wake(pdev, PCI_D0, 1);
487 if (ret)
488 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
489
490 return 0;
491}
492
493static int pch_gpio_resume(struct pci_dev *pdev)
494{
495 s32 ret;
496 struct pch_gpio *chip = pci_get_drvdata(pdev);
497 unsigned long flags;
498
499 ret = pci_enable_wake(pdev, PCI_D0, 0);
500
501 pci_set_power_state(pdev, PCI_D0);
502 ret = pci_enable_device(pdev);
503 if (ret) {
504 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
505 return ret;
506 }
507 pci_restore_state(pdev);
508
509 spin_lock_irqsave(&chip->spinlock, flags);
510 iowrite32(0x01, &chip->reg->reset);
511 iowrite32(0x00, &chip->reg->reset);
512 pch_gpio_restore_reg_conf(chip);
513 spin_unlock_irqrestore(&chip->spinlock, flags);
514
515 return 0;
516}
517#else
518#define pch_gpio_suspend NULL
519#define pch_gpio_resume NULL
520#endif
521
522#define PCI_VENDOR_ID_ROHM 0x10DB
523static const struct pci_device_id pch_gpio_pcidev_id[] = {
524 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
525 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
526 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
527 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
528 { 0, }
529};
530MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
531
532static struct pci_driver pch_gpio_driver = {
533 .name = "pch_gpio",
534 .id_table = pch_gpio_pcidev_id,
535 .probe = pch_gpio_probe,
536 .remove = pch_gpio_remove,
537 .suspend = pch_gpio_suspend,
538 .resume = pch_gpio_resume
539};
540
541module_pci_driver(pch_gpio_driver);
542
543MODULE_DESCRIPTION("PCH GPIO PCI Driver");
544MODULE_LICENSE("GPL");