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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
4 *
5 * Copyright (C) 2011-2012 International Business Machines Inc.
6 *
7 * Author: Kent Yoder <yoder1@us.ibm.com>
8 */
9
10#include <crypto/internal/hash.h>
11#include <crypto/sha2.h>
12#include <linux/module.h>
13#include <asm/vio.h>
14
15#include "nx_csbcpb.h"
16#include "nx.h"
17
18struct sha512_state_be {
19 __be64 state[SHA512_DIGEST_SIZE / 8];
20 u64 count[2];
21 u8 buf[SHA512_BLOCK_SIZE];
22};
23
24static int nx_crypto_ctx_sha512_init(struct crypto_tfm *tfm)
25{
26 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
27 int err;
28
29 err = nx_crypto_ctx_sha_init(tfm);
30 if (err)
31 return err;
32
33 nx_ctx_init(nx_ctx, HCOP_FC_SHA);
34
35 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
36
37 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
38
39 return 0;
40}
41
42static int nx_sha512_init(struct shash_desc *desc)
43{
44 struct sha512_state_be *sctx = shash_desc_ctx(desc);
45
46 memset(sctx, 0, sizeof *sctx);
47
48 sctx->state[0] = __cpu_to_be64(SHA512_H0);
49 sctx->state[1] = __cpu_to_be64(SHA512_H1);
50 sctx->state[2] = __cpu_to_be64(SHA512_H2);
51 sctx->state[3] = __cpu_to_be64(SHA512_H3);
52 sctx->state[4] = __cpu_to_be64(SHA512_H4);
53 sctx->state[5] = __cpu_to_be64(SHA512_H5);
54 sctx->state[6] = __cpu_to_be64(SHA512_H6);
55 sctx->state[7] = __cpu_to_be64(SHA512_H7);
56 sctx->count[0] = 0;
57
58 return 0;
59}
60
61static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
62 unsigned int len)
63{
64 struct sha512_state_be *sctx = shash_desc_ctx(desc);
65 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
66 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
67 struct nx_sg *out_sg;
68 u64 to_process, leftover = 0, total;
69 unsigned long irq_flags;
70 int rc = 0;
71 int data_len;
72 u32 max_sg_len;
73 u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);
74
75 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
76
77 /* 2 cases for total data len:
78 * 1: < SHA512_BLOCK_SIZE: copy into state, return 0
79 * 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
80 */
81 total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
82 if (total < SHA512_BLOCK_SIZE) {
83 memcpy(sctx->buf + buf_len, data, len);
84 sctx->count[0] += len;
85 goto out;
86 }
87
88 memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
89 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
90 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
91
92 max_sg_len = min_t(u64, nx_ctx->ap->sglen,
93 nx_driver.of.max_sg_len/sizeof(struct nx_sg));
94 max_sg_len = min_t(u64, max_sg_len,
95 nx_ctx->ap->databytelen/NX_PAGE_SIZE);
96
97 data_len = SHA512_DIGEST_SIZE;
98 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
99 &data_len, max_sg_len);
100 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
101
102 if (data_len != SHA512_DIGEST_SIZE) {
103 rc = -EINVAL;
104 goto out;
105 }
106
107 do {
108 int used_sgs = 0;
109 struct nx_sg *in_sg = nx_ctx->in_sg;
110
111 if (buf_len) {
112 data_len = buf_len;
113 in_sg = nx_build_sg_list(in_sg,
114 (u8 *) sctx->buf,
115 &data_len, max_sg_len);
116
117 if (data_len != buf_len) {
118 rc = -EINVAL;
119 goto out;
120 }
121 used_sgs = in_sg - nx_ctx->in_sg;
122 }
123
124 /* to_process: SHA512_BLOCK_SIZE aligned chunk to be
125 * processed in this iteration. This value is restricted
126 * by sg list limits and number of sgs we already used
127 * for leftover data. (see above)
128 * In ideal case, we could allow NX_PAGE_SIZE * max_sg_len,
129 * but because data may not be aligned, we need to account
130 * for that too. */
131 to_process = min_t(u64, total,
132 (max_sg_len - 1 - used_sgs) * NX_PAGE_SIZE);
133 to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
134
135 data_len = to_process - buf_len;
136 in_sg = nx_build_sg_list(in_sg, (u8 *) data,
137 &data_len, max_sg_len);
138
139 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
140
141 if (data_len != (to_process - buf_len)) {
142 rc = -EINVAL;
143 goto out;
144 }
145
146 to_process = data_len + buf_len;
147 leftover = total - to_process;
148
149 /*
150 * we've hit the nx chip previously and we're updating
151 * again, so copy over the partial digest.
152 */
153 memcpy(csbcpb->cpb.sha512.input_partial_digest,
154 csbcpb->cpb.sha512.message_digest,
155 SHA512_DIGEST_SIZE);
156
157 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
158 rc = -EINVAL;
159 goto out;
160 }
161
162 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
163 if (rc)
164 goto out;
165
166 atomic_inc(&(nx_ctx->stats->sha512_ops));
167
168 total -= to_process;
169 data += to_process - buf_len;
170 buf_len = 0;
171
172 } while (leftover >= SHA512_BLOCK_SIZE);
173
174 /* copy the leftover back into the state struct */
175 if (leftover)
176 memcpy(sctx->buf, data, leftover);
177 sctx->count[0] += len;
178 memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
179out:
180 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
181 return rc;
182}
183
184static int nx_sha512_final(struct shash_desc *desc, u8 *out)
185{
186 struct sha512_state_be *sctx = shash_desc_ctx(desc);
187 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
188 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
189 struct nx_sg *in_sg, *out_sg;
190 u32 max_sg_len;
191 u64 count0;
192 unsigned long irq_flags;
193 int rc = 0;
194 int len;
195
196 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
197
198 max_sg_len = min_t(u64, nx_ctx->ap->sglen,
199 nx_driver.of.max_sg_len/sizeof(struct nx_sg));
200 max_sg_len = min_t(u64, max_sg_len,
201 nx_ctx->ap->databytelen/NX_PAGE_SIZE);
202
203 /* final is represented by continuing the operation and indicating that
204 * this is not an intermediate operation */
205 if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
206 /* we've hit the nx chip previously, now we're finalizing,
207 * so copy over the partial digest */
208 memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
209 SHA512_DIGEST_SIZE);
210 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
211 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
212 } else {
213 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
214 NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
215 }
216
217 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
218
219 count0 = sctx->count[0] * 8;
220
221 csbcpb->cpb.sha512.message_bit_length_lo = count0;
222
223 len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
224 in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, &len,
225 max_sg_len);
226
227 if (len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1))) {
228 rc = -EINVAL;
229 goto out;
230 }
231
232 len = SHA512_DIGEST_SIZE;
233 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, &len,
234 max_sg_len);
235
236 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
237 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
238
239 if (!nx_ctx->op.outlen) {
240 rc = -EINVAL;
241 goto out;
242 }
243
244 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op, 0);
245 if (rc)
246 goto out;
247
248 atomic_inc(&(nx_ctx->stats->sha512_ops));
249 atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));
250
251 memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
252out:
253 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
254 return rc;
255}
256
257static int nx_sha512_export(struct shash_desc *desc, void *out)
258{
259 struct sha512_state_be *sctx = shash_desc_ctx(desc);
260
261 memcpy(out, sctx, sizeof(*sctx));
262
263 return 0;
264}
265
266static int nx_sha512_import(struct shash_desc *desc, const void *in)
267{
268 struct sha512_state_be *sctx = shash_desc_ctx(desc);
269
270 memcpy(sctx, in, sizeof(*sctx));
271
272 return 0;
273}
274
275struct shash_alg nx_shash_sha512_alg = {
276 .digestsize = SHA512_DIGEST_SIZE,
277 .init = nx_sha512_init,
278 .update = nx_sha512_update,
279 .final = nx_sha512_final,
280 .export = nx_sha512_export,
281 .import = nx_sha512_import,
282 .descsize = sizeof(struct sha512_state_be),
283 .statesize = sizeof(struct sha512_state_be),
284 .base = {
285 .cra_name = "sha512",
286 .cra_driver_name = "sha512-nx",
287 .cra_priority = 300,
288 .cra_blocksize = SHA512_BLOCK_SIZE,
289 .cra_module = THIS_MODULE,
290 .cra_ctxsize = sizeof(struct nx_crypto_ctx),
291 .cra_init = nx_crypto_ctx_sha512_init,
292 .cra_exit = nx_crypto_ctx_exit,
293 }
294};
1/**
2 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
3 *
4 * Copyright (C) 2011-2012 International Business Machines Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 only.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Author: Kent Yoder <yoder1@us.ibm.com>
20 */
21
22#include <crypto/internal/hash.h>
23#include <crypto/sha.h>
24#include <linux/module.h>
25#include <asm/vio.h>
26
27#include "nx_csbcpb.h"
28#include "nx.h"
29
30
31static int nx_sha512_init(struct shash_desc *desc)
32{
33 struct sha512_state *sctx = shash_desc_ctx(desc);
34 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
35 struct nx_sg *out_sg;
36
37 nx_ctx_init(nx_ctx, HCOP_FC_SHA);
38
39 memset(sctx, 0, sizeof *sctx);
40
41 nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
42
43 NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
44 out_sg = nx_build_sg_list(nx_ctx->out_sg, (u8 *)sctx->state,
45 SHA512_DIGEST_SIZE, nx_ctx->ap->sglen);
46 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
47
48 return 0;
49}
50
51static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
52 unsigned int len)
53{
54 struct sha512_state *sctx = shash_desc_ctx(desc);
55 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
56 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
57 struct nx_sg *in_sg;
58 u64 to_process, leftover, total, spbc_bits;
59 u32 max_sg_len;
60 unsigned long irq_flags;
61 int rc = 0;
62
63 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
64
65 /* 2 cases for total data len:
66 * 1: < SHA512_BLOCK_SIZE: copy into state, return 0
67 * 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
68 */
69 total = sctx->count[0] + len;
70 if (total < SHA512_BLOCK_SIZE) {
71 memcpy(sctx->buf + sctx->count[0], data, len);
72 sctx->count[0] += len;
73 goto out;
74 }
75
76 in_sg = nx_ctx->in_sg;
77 max_sg_len = min_t(u32, nx_driver.of.max_sg_len/sizeof(struct nx_sg),
78 nx_ctx->ap->sglen);
79
80 do {
81 /*
82 * to_process: the SHA512_BLOCK_SIZE data chunk to process in
83 * this update. This value is also restricted by the sg list
84 * limits.
85 */
86 to_process = min_t(u64, total, nx_ctx->ap->databytelen);
87 to_process = min_t(u64, to_process,
88 NX_PAGE_SIZE * (max_sg_len - 1));
89 to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
90 leftover = total - to_process;
91
92 if (sctx->count[0]) {
93 in_sg = nx_build_sg_list(nx_ctx->in_sg,
94 (u8 *) sctx->buf,
95 sctx->count[0], max_sg_len);
96 }
97 in_sg = nx_build_sg_list(in_sg, (u8 *) data,
98 to_process - sctx->count[0],
99 max_sg_len);
100 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) *
101 sizeof(struct nx_sg);
102
103 if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
104 /*
105 * we've hit the nx chip previously and we're updating
106 * again, so copy over the partial digest.
107 */
108 memcpy(csbcpb->cpb.sha512.input_partial_digest,
109 csbcpb->cpb.sha512.message_digest,
110 SHA512_DIGEST_SIZE);
111 }
112
113 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
114 if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
115 rc = -EINVAL;
116 goto out;
117 }
118
119 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
120 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
121 if (rc)
122 goto out;
123
124 atomic_inc(&(nx_ctx->stats->sha512_ops));
125 spbc_bits = csbcpb->cpb.sha512.spbc * 8;
126 csbcpb->cpb.sha512.message_bit_length_lo += spbc_bits;
127 if (csbcpb->cpb.sha512.message_bit_length_lo < spbc_bits)
128 csbcpb->cpb.sha512.message_bit_length_hi++;
129
130 /* everything after the first update is continuation */
131 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
132
133 total -= to_process;
134 data += to_process - sctx->count[0];
135 sctx->count[0] = 0;
136 in_sg = nx_ctx->in_sg;
137 } while (leftover >= SHA512_BLOCK_SIZE);
138
139 /* copy the leftover back into the state struct */
140 if (leftover)
141 memcpy(sctx->buf, data, leftover);
142 sctx->count[0] = leftover;
143out:
144 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
145 return rc;
146}
147
148static int nx_sha512_final(struct shash_desc *desc, u8 *out)
149{
150 struct sha512_state *sctx = shash_desc_ctx(desc);
151 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
152 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
153 struct nx_sg *in_sg, *out_sg;
154 u32 max_sg_len;
155 u64 count0;
156 unsigned long irq_flags;
157 int rc;
158
159 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
160
161 max_sg_len = min_t(u32, nx_driver.of.max_sg_len, nx_ctx->ap->sglen);
162
163 if (NX_CPB_FDM(csbcpb) & NX_FDM_CONTINUATION) {
164 /* we've hit the nx chip previously, now we're finalizing,
165 * so copy over the partial digest */
166 memcpy(csbcpb->cpb.sha512.input_partial_digest,
167 csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
168 }
169
170 /* final is represented by continuing the operation and indicating that
171 * this is not an intermediate operation */
172 NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
173
174 count0 = sctx->count[0] * 8;
175
176 csbcpb->cpb.sha512.message_bit_length_lo += count0;
177 if (csbcpb->cpb.sha512.message_bit_length_lo < count0)
178 csbcpb->cpb.sha512.message_bit_length_hi++;
179
180 in_sg = nx_build_sg_list(nx_ctx->in_sg, sctx->buf, sctx->count[0],
181 max_sg_len);
182 out_sg = nx_build_sg_list(nx_ctx->out_sg, out, SHA512_DIGEST_SIZE,
183 max_sg_len);
184 nx_ctx->op.inlen = (nx_ctx->in_sg - in_sg) * sizeof(struct nx_sg);
185 nx_ctx->op.outlen = (nx_ctx->out_sg - out_sg) * sizeof(struct nx_sg);
186
187 if (!nx_ctx->op.outlen) {
188 rc = -EINVAL;
189 goto out;
190 }
191
192 rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
193 desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
194 if (rc)
195 goto out;
196
197 atomic_inc(&(nx_ctx->stats->sha512_ops));
198 atomic64_add(csbcpb->cpb.sha512.message_bit_length_lo / 8,
199 &(nx_ctx->stats->sha512_bytes));
200
201 memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
202out:
203 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
204 return rc;
205}
206
207static int nx_sha512_export(struct shash_desc *desc, void *out)
208{
209 struct sha512_state *sctx = shash_desc_ctx(desc);
210 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
211 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
212 struct sha512_state *octx = out;
213 unsigned long irq_flags;
214
215 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
216
217 /* move message_bit_length (128 bits) into count and convert its value
218 * to bytes */
219 octx->count[0] = csbcpb->cpb.sha512.message_bit_length_lo >> 3 |
220 ((csbcpb->cpb.sha512.message_bit_length_hi & 7) << 61);
221 octx->count[1] = csbcpb->cpb.sha512.message_bit_length_hi >> 3;
222
223 octx->count[0] += sctx->count[0];
224 if (octx->count[0] < sctx->count[0])
225 octx->count[1]++;
226
227 memcpy(octx->buf, sctx->buf, sizeof(octx->buf));
228
229 /* if no data has been processed yet, we need to export SHA512's
230 * initial data, in case this context gets imported into a software
231 * context */
232 if (csbcpb->cpb.sha512.message_bit_length_hi ||
233 csbcpb->cpb.sha512.message_bit_length_lo)
234 memcpy(octx->state, csbcpb->cpb.sha512.message_digest,
235 SHA512_DIGEST_SIZE);
236 else {
237 octx->state[0] = SHA512_H0;
238 octx->state[1] = SHA512_H1;
239 octx->state[2] = SHA512_H2;
240 octx->state[3] = SHA512_H3;
241 octx->state[4] = SHA512_H4;
242 octx->state[5] = SHA512_H5;
243 octx->state[6] = SHA512_H6;
244 octx->state[7] = SHA512_H7;
245 }
246
247 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
248 return 0;
249}
250
251static int nx_sha512_import(struct shash_desc *desc, const void *in)
252{
253 struct sha512_state *sctx = shash_desc_ctx(desc);
254 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
255 struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
256 const struct sha512_state *ictx = in;
257 unsigned long irq_flags;
258
259 spin_lock_irqsave(&nx_ctx->lock, irq_flags);
260
261 memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf));
262 sctx->count[0] = ictx->count[0] & 0x3f;
263 csbcpb->cpb.sha512.message_bit_length_lo = (ictx->count[0] & ~0x3f)
264 << 3;
265 csbcpb->cpb.sha512.message_bit_length_hi = ictx->count[1] << 3 |
266 ictx->count[0] >> 61;
267
268 if (csbcpb->cpb.sha512.message_bit_length_hi ||
269 csbcpb->cpb.sha512.message_bit_length_lo) {
270 memcpy(csbcpb->cpb.sha512.message_digest, ictx->state,
271 SHA512_DIGEST_SIZE);
272
273 NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
274 NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
275 }
276
277 spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
278 return 0;
279}
280
281struct shash_alg nx_shash_sha512_alg = {
282 .digestsize = SHA512_DIGEST_SIZE,
283 .init = nx_sha512_init,
284 .update = nx_sha512_update,
285 .final = nx_sha512_final,
286 .export = nx_sha512_export,
287 .import = nx_sha512_import,
288 .descsize = sizeof(struct sha512_state),
289 .statesize = sizeof(struct sha512_state),
290 .base = {
291 .cra_name = "sha512",
292 .cra_driver_name = "sha512-nx",
293 .cra_priority = 300,
294 .cra_flags = CRYPTO_ALG_TYPE_SHASH,
295 .cra_blocksize = SHA512_BLOCK_SIZE,
296 .cra_module = THIS_MODULE,
297 .cra_ctxsize = sizeof(struct nx_crypto_ctx),
298 .cra_init = nx_crypto_ctx_sha_init,
299 .cra_exit = nx_crypto_ctx_exit,
300 }
301};