1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * arch/arm/mach-tegra/reset.h
 4 *
 5 * CPU reset dispatcher.
 6 *
 7 * Copyright (c) 2011, NVIDIA Corporation.
 
 
 
 
 
 
 
 
 
 
 8 */
 9
10#ifndef __MACH_TEGRA_RESET_H
11#define __MACH_TEGRA_RESET_H
12
13#define TEGRA_RESET_MASK_PRESENT	0
14#define TEGRA_RESET_MASK_LP1		1
15#define TEGRA_RESET_MASK_LP2		2
16#define TEGRA_RESET_STARTUP_SECONDARY	3
17#define TEGRA_RESET_STARTUP_LP2		4
18#define TEGRA_RESET_STARTUP_LP1		5
19#define TEGRA_RESET_TF_PRESENT		6
20#define TEGRA_RESET_DATA_SIZE		7
21
22#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
23
24#ifndef __ASSEMBLY__
25
26#include "irammap.h"
27
28extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
29
30void __tegra_cpu_reset_handler_start(void);
31void __tegra_cpu_reset_handler(void);
32void __tegra20_cpu1_resettable_status_offset(void);
33void __tegra_cpu_reset_handler_end(void);
 
34
35#ifdef CONFIG_PM_SLEEP
36#define tegra_cpu_lp1_mask \
37	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
38	((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
39	 (u32)__tegra_cpu_reset_handler_start)))
40#define tegra_cpu_lp2_mask \
41	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
42	((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
43	 (u32)__tegra_cpu_reset_handler_start)))
44#endif
45
46#define tegra_cpu_reset_handler_offset \
47		((u32)__tegra_cpu_reset_handler - \
48		 (u32)__tegra_cpu_reset_handler_start)
49
50#define tegra_cpu_reset_handler_size \
51		(__tegra_cpu_reset_handler_end - \
52		 __tegra_cpu_reset_handler_start)
53
54void __init tegra_cpu_reset_handler_init(void);
55
56#endif
57#endif

 
 1/*
 2 * arch/arm/mach-tegra/reset.h
 3 *
 4 * CPU reset dispatcher.
 5 *
 6 * Copyright (c) 2011, NVIDIA Corporation.
 7 *
 8 * This software is licensed under the terms of the GNU General Public
 9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef __MACH_TEGRA_RESET_H
20#define __MACH_TEGRA_RESET_H
21
22#define TEGRA_RESET_MASK_PRESENT	0
23#define TEGRA_RESET_MASK_LP1		1
24#define TEGRA_RESET_MASK_LP2		2
25#define TEGRA_RESET_STARTUP_SECONDARY	3
26#define TEGRA_RESET_STARTUP_LP2		4
27#define TEGRA_RESET_STARTUP_LP1		5
28#define TEGRA_RESET_DATA_SIZE		6
 
 
 
29
30#ifndef __ASSEMBLY__
31
32#include "irammap.h"
33
34extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
35
36void __tegra_cpu_reset_handler_start(void);
37void __tegra_cpu_reset_handler(void);
 
38void __tegra_cpu_reset_handler_end(void);
39void tegra_secondary_startup(void);
40
41#ifdef CONFIG_PM_SLEEP
42#define tegra_cpu_lp1_mask \
43	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
44	((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
45	 (u32)__tegra_cpu_reset_handler_start)))
46#define tegra_cpu_lp2_mask \
47	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
48	((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
49	 (u32)__tegra_cpu_reset_handler_start)))
50#endif
51
52#define tegra_cpu_reset_handler_offset \
53		((u32)__tegra_cpu_reset_handler - \
54		 (u32)__tegra_cpu_reset_handler_start)
55
56#define tegra_cpu_reset_handler_size \
57		(__tegra_cpu_reset_handler_end - \
58		 __tegra_cpu_reset_handler_start)
59
60void __init tegra_cpu_reset_handler_init(void);
61
62#endif
63#endif