1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  4 */
  5
 
 
 
 
 
  6
  7#ifndef __ASM_ARCH_MXC_COMMON_H__
  8#define __ASM_ARCH_MXC_COMMON_H__
  9
 10#include <linux/reboot.h>
 11
 12struct irq_data;
 13struct platform_device;
 14struct pt_regs;
 15struct clk;
 16struct device_node;
 17enum mxc_cpu_pwr_mode;
 18struct of_device_id;
 19
 
 
 
 
 20void mx31_map_io(void);
 21void mx35_map_io(void);
 
 
 
 22void imx21_init_early(void);
 
 
 23void imx31_init_early(void);
 24void imx35_init_early(void);
 
 
 
 
 
 
 
 
 25void mx31_init_irq(void);
 26void mx35_init_irq(void);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 27void mxc_set_cpu_type(unsigned int type);
 28void mxc_restart(enum reboot_mode, const char *);
 29void mxc_arch_reset_init(void __iomem *);
 30void imx1_reset_init(void __iomem *);
 
 31void imx_set_aips(void __iomem *);
 32void imx_aips_allow_unprivileged_access(const char *compat);
 33int mxc_device_init(void);
 34void imx_set_soc_revision(unsigned int rev);
 
 35void imx_init_revision_from_anatop(void);
 36void imx6_enable_rbc(bool enable);
 37void imx_gpc_check_dt(void);
 38void imx_gpc_set_arm_power_in_lpm(bool power_off);
 39void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
 40void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 41void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
 42void imx25_pm_init(void);
 43void imx27_pm_init(void);
 44void imx5_pmu_init(void);
 45
 46enum mxc_cpu_pwr_mode {
 47	WAIT_CLOCKED,		/* wfi only */
 48	WAIT_UNCLOCKED,		/* WAIT */
 49	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
 50	STOP_POWER_ON,		/* just STOP */
 51	STOP_POWER_OFF,		/* STOP + SRPG */
 52};
 53
 54enum ulp_cpu_pwr_mode {
 55	ULP_PM_HSRUN,    /* High speed run mode */
 56	ULP_PM_RUN,      /* Run mode */
 57	ULP_PM_WAIT,     /* Wait mode */
 58	ULP_PM_STOP,     /* Stop mode */
 59	ULP_PM_VLPS,     /* Very low power stop mode */
 60	ULP_PM_VLLS,     /* very low leakage stop mode */
 61};
 62
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 63void imx_enable_cpu(int cpu, bool enable);
 64void imx_set_cpu_jump(int cpu, void *jump_addr);
 65u32 imx_get_cpu_arg(int cpu);
 66void imx_set_cpu_arg(int cpu, u32 arg);
 67#ifdef CONFIG_SMP
 68void v7_secondary_startup(void);
 69void imx_scu_map_io(void);
 70void imx_smp_prepare(void);
 
 71#else
 72static inline void imx_scu_map_io(void) {}
 73static inline void imx_smp_prepare(void) {}
 
 74#endif
 75void imx_src_init(void);
 76void imx7_src_init(void);
 77void imx_gpc_pre_suspend(bool arm_power_off);
 78void imx_gpc_post_resume(void);
 79void imx_gpc_mask_all(void);
 80void imx_gpc_restore_all(void);
 81void imx_gpc_hwirq_mask(unsigned int hwirq);
 82void imx_gpc_hwirq_unmask(unsigned int hwirq);
 83void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn);
 84void imx_anatop_init(void);
 85void imx_anatop_pre_suspend(void);
 86void imx_anatop_post_resume(void);
 87int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 88void imx6_set_int_mem_clk_lpm(bool enable);
 89int imx_mmdc_get_ddr_type(void);
 90int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
 91
 92void imx_cpu_die(unsigned int cpu);
 93int imx_cpu_kill(unsigned int cpu);
 94
 95#ifdef CONFIG_SUSPEND
 96void imx53_suspend(void __iomem *ocram_vbase);
 97extern const u32 imx53_suspend_sz;
 98void imx6_suspend(void __iomem *ocram_vbase);
 99#else
100static inline void imx53_suspend(void __iomem *ocram_vbase) {}
101static const u32 imx53_suspend_sz;
102static inline void imx6_suspend(void __iomem *ocram_vbase) {}
103#endif
104
105void v7_cpu_resume(void);
106
107void imx6_pm_ccm_init(const char *ccm_compat);
108void imx6q_pm_init(void);
109void imx6dl_pm_init(void);
110void imx6sl_pm_init(void);
111void imx6sx_pm_init(void);
112void imx6ul_pm_init(void);
113void imx7ulp_pm_init(void);
114
115#ifdef CONFIG_PM
116void imx51_pm_init(void);
117void imx53_pm_init(void);
118#else
119static inline void imx51_pm_init(void) {}
120static inline void imx53_pm_init(void) {}
121#endif
122
123#ifdef CONFIG_NEON
124int mx51_neon_fixup(void);
125#else
126static inline int mx51_neon_fixup(void) { return 0; }
127#endif
128
129#ifdef CONFIG_CACHE_L2X0
130void imx_init_l2cache(void);
131#else
132static inline void imx_init_l2cache(void) {}
133#endif
134
135extern const struct smp_operations imx_smp_ops;
136extern const struct smp_operations imx7_smp_ops;
137extern const struct smp_operations ls1021a_smp_ops;
138
139#endif

 
  1/*
  2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  3 */
  4
  5/*
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10
 11#ifndef __ASM_ARCH_MXC_COMMON_H__
 12#define __ASM_ARCH_MXC_COMMON_H__
 13
 14#include <linux/reboot.h>
 15
 16struct irq_data;
 17struct platform_device;
 18struct pt_regs;
 19struct clk;
 
 20enum mxc_cpu_pwr_mode;
 
 21
 22void mx1_map_io(void);
 23void mx21_map_io(void);
 24void mx25_map_io(void);
 25void mx27_map_io(void);
 26void mx31_map_io(void);
 27void mx35_map_io(void);
 28void mx51_map_io(void);
 29void mx53_map_io(void);
 30void imx1_init_early(void);
 31void imx21_init_early(void);
 32void imx25_init_early(void);
 33void imx27_init_early(void);
 34void imx31_init_early(void);
 35void imx35_init_early(void);
 36void imx51_init_early(void);
 37void imx53_init_early(void);
 38void mxc_init_irq(void __iomem *);
 39void tzic_init_irq(void __iomem *);
 40void mx1_init_irq(void);
 41void mx21_init_irq(void);
 42void mx25_init_irq(void);
 43void mx27_init_irq(void);
 44void mx31_init_irq(void);
 45void mx35_init_irq(void);
 46void mx51_init_irq(void);
 47void mx53_init_irq(void);
 48void imx1_soc_init(void);
 49void imx21_soc_init(void);
 50void imx25_soc_init(void);
 51void imx27_soc_init(void);
 52void imx31_soc_init(void);
 53void imx35_soc_init(void);
 54void imx51_soc_init(void);
 55void imx51_init_late(void);
 56void imx53_init_late(void);
 57void epit_timer_init(void __iomem *base, int irq);
 58void mxc_timer_init(void __iomem *, int);
 59int mx1_clocks_init(unsigned long fref);
 60int mx21_clocks_init(unsigned long lref, unsigned long fref);
 61int mx25_clocks_init(void);
 62int mx27_clocks_init(unsigned long fref);
 63int mx31_clocks_init(unsigned long fref);
 64int mx35_clocks_init(void);
 65int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 66			unsigned long ckih1, unsigned long ckih2);
 67int mx25_clocks_init_dt(void);
 68int mx27_clocks_init_dt(void);
 69int mx31_clocks_init_dt(void);
 70struct platform_device *mxc_register_gpio(char *name, int id,
 71	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 72void mxc_set_cpu_type(unsigned int type);
 73void mxc_restart(enum reboot_mode, const char *);
 74void mxc_arch_reset_init(void __iomem *);
 75void mxc_arch_reset_init_dt(void);
 76int mx53_revision(void);
 77void imx_set_aips(void __iomem *);
 
 78int mxc_device_init(void);
 79void imx_set_soc_revision(unsigned int rev);
 80unsigned int imx_get_soc_revision(void);
 81void imx_init_revision_from_anatop(void);
 82struct device *imx_soc_device_init(void);
 
 
 
 
 
 
 
 
 83
 84enum mxc_cpu_pwr_mode {
 85	WAIT_CLOCKED,		/* wfi only */
 86	WAIT_UNCLOCKED,		/* WAIT */
 87	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
 88	STOP_POWER_ON,		/* just STOP */
 89	STOP_POWER_OFF,		/* STOP + SRPG */
 90};
 91
 92enum mx3_cpu_pwr_mode {
 93	MX3_RUN,
 94	MX3_WAIT,
 95	MX3_DOZE,
 96	MX3_SLEEP,
 
 
 97};
 98
 99void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
100void imx_print_silicon_rev(const char *cpu, int srev);
101
102void avic_handle_irq(struct pt_regs *);
103void tzic_handle_irq(struct pt_regs *);
104
105#define imx1_handle_irq avic_handle_irq
106#define imx21_handle_irq avic_handle_irq
107#define imx25_handle_irq avic_handle_irq
108#define imx27_handle_irq avic_handle_irq
109#define imx31_handle_irq avic_handle_irq
110#define imx35_handle_irq avic_handle_irq
111#define imx50_handle_irq tzic_handle_irq
112#define imx51_handle_irq tzic_handle_irq
113#define imx53_handle_irq tzic_handle_irq
114
115void imx_enable_cpu(int cpu, bool enable);
116void imx_set_cpu_jump(int cpu, void *jump_addr);
117u32 imx_get_cpu_arg(int cpu);
118void imx_set_cpu_arg(int cpu, u32 arg);
119#ifdef CONFIG_SMP
120void v7_secondary_startup(void);
121void imx_scu_map_io(void);
122void imx_smp_prepare(void);
123void imx_scu_standby_enable(void);
124#else
125static inline void imx_scu_map_io(void) {}
126static inline void imx_smp_prepare(void) {}
127static inline void imx_scu_standby_enable(void) {}
128#endif
129void imx_src_init(void);
130void imx_gpc_init(void);
131void imx_gpc_pre_suspend(void);
132void imx_gpc_post_resume(void);
133void imx_gpc_mask_all(void);
134void imx_gpc_restore_all(void);
135void imx_gpc_irq_mask(struct irq_data *d);
136void imx_gpc_irq_unmask(struct irq_data *d);
 
137void imx_anatop_init(void);
138void imx_anatop_pre_suspend(void);
139void imx_anatop_post_resume(void);
140int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
141void imx6q_set_int_mem_clk_lpm(void);
142void imx6sl_set_wait_clk(bool enter);
 
143
144void imx_cpu_die(unsigned int cpu);
145int imx_cpu_kill(unsigned int cpu);
146
147#ifdef CONFIG_SUSPEND
148void v7_cpu_resume(void);
 
149void imx6_suspend(void __iomem *ocram_vbase);
150#else
151static inline void v7_cpu_resume(void) {}
 
152static inline void imx6_suspend(void __iomem *ocram_vbase) {}
153#endif
154
 
 
 
155void imx6q_pm_init(void);
156void imx6dl_pm_init(void);
157void imx6sl_pm_init(void);
158void imx6q_pm_set_ccm_base(void __iomem *base);
 
 
159
160#ifdef CONFIG_PM
161void imx5_pm_init(void);
 
162#else
163static inline void imx5_pm_init(void) {}
 
164#endif
165
166#ifdef CONFIG_NEON
167int mx51_neon_fixup(void);
168#else
169static inline int mx51_neon_fixup(void) { return 0; }
170#endif
171
172#ifdef CONFIG_CACHE_L2X0
173void imx_init_l2cache(void);
174#else
175static inline void imx_init_l2cache(void) {}
176#endif
177
178extern struct smp_operations imx_smp_ops;
 
 
179
180#endif