1/*
  2 *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 * This program is distributed in the hope that it will be useful,
  9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 11 * GNU General Public License for more details.
 12 *
 13 * You should have received a copy of the GNU General Public License along
 14 * with this program; if not, write to the Free Software Foundation, Inc.,
 15 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 16 */
 17
 18#include <linux/kernel.h>
 19#include <linux/init.h>
 20#include <linux/clk.h>
 21#include <linux/io.h>
 22#include <linux/clkdev.h>
 23#include <linux/err.h>
 24
 25#include "clk.h"
 26#include "common.h"
 27#include "hardware.h"
 28
 29/* CCM register addresses */
 30#define IO_ADDR_CCM(off)	(MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
 31
 32#define CCM_CSCR	IO_ADDR_CCM(0x0)
 33#define CCM_MPCTL0	IO_ADDR_CCM(0x4)
 34#define CCM_SPCTL0	IO_ADDR_CCM(0xc)
 35#define CCM_PCDR	IO_ADDR_CCM(0x20)
 36
 37/* SCM register addresses */
 38#define IO_ADDR_SCM(off)	(MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
 39
 40#define SCM_GCCR	IO_ADDR_SCM(0xc)
 41
 42static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
 43static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
 44				"fclk", };
 45enum imx1_clks {
 46	dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
 47	fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
 48	mma_gate, usbd_gate, clk_max
 49};
 50
 51static struct clk *clk[clk_max];
 52
 53int __init mx1_clocks_init(unsigned long fref)
 54{
 55	int i;
 56
 57	clk[dummy] = imx_clk_fixed("dummy", 0);
 58	clk[clk32] = imx_clk_fixed("clk32", fref);
 59	clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
 60	clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
 61	clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
 62	clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
 63			ARRAY_SIZE(prem_sel_clks));
 64	clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
 65	clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
 66	clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
 67	clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
 68	clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
 69	clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
 70	clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
 71	clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
 72	clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
 73	clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
 74			ARRAY_SIZE(clko_sel_clks));
 75	clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
 76	clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
 77	clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
 78	clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
 79
 80	for (i = 0; i < ARRAY_SIZE(clk); i++)
 81		if (IS_ERR(clk[i]))
 82			pr_err("imx1 clk %d: register failed with %ld\n",
 83				i, PTR_ERR(clk[i]));
 84
 85	clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
 86	clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
 87	clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
 88	clk_register_clkdev(clk[mma_gate], "mma", NULL);
 89	clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
 90	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
 91	clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
 92	clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
 93	clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
 94	clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
 95	clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
 96	clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
 97	clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
 98	clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
 99	clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
100	clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
101	clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
102	clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
103	clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
104	clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
105	clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
106	clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
107	clk_register_clkdev(clk[hclk], "mshc", NULL);
108	clk_register_clkdev(clk[per3], "ssi", NULL);
109	clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0");
110	clk_register_clkdev(clk[clko], "clko", NULL);
111
112	mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
113
114	return 0;
115}