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1/*
2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4 *
5 * Under GPLv2
6 */
7
8#include <linux/module.h>
9#include <linux/io.h>
10#include <linux/mm.h>
11#include <linux/pm.h>
12#include <linux/of_address.h>
13#include <linux/pinctrl/machine.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/system_misc.h>
17#include <asm/mach/map.h>
18
19#include <mach/hardware.h>
20#include <mach/cpu.h>
21#include <mach/at91_dbgu.h>
22
23#include "at91_shdwc.h"
24#include "soc.h"
25#include "generic.h"
26#include "pm.h"
27
28struct at91_init_soc __initdata at91_boot_soc;
29
30struct at91_socinfo at91_soc_initdata;
31EXPORT_SYMBOL(at91_soc_initdata);
32
33void __init at91rm9200_set_type(int type)
34{
35 if (type == ARCH_REVISON_9200_PQFP)
36 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
37 else
38 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
39
40 pr_info("AT91: filled in soc subtype: %s\n",
41 at91_get_soc_subtype(&at91_soc_initdata));
42}
43
44void __init at91_init_irq_default(void)
45{
46 at91_init_interrupts(at91_boot_soc.default_irq_priority);
47}
48
49void __init at91_init_interrupts(unsigned int *priority)
50{
51 /* Initialize the AIC interrupt controller */
52 at91_aic_init(priority, at91_boot_soc.extern_irq);
53
54 /* Enable GPIO interrupts */
55 at91_gpio_irq_setup();
56}
57
58void __iomem *at91_ramc_base[2];
59EXPORT_SYMBOL_GPL(at91_ramc_base);
60
61void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
62{
63 if (id < 0 || id > 1) {
64 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
65 BUG();
66 }
67 at91_ramc_base[id] = ioremap(addr, size);
68 if (!at91_ramc_base[id])
69 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
70}
71
72static struct map_desc sram_desc[2] __initdata;
73
74void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
75{
76 struct map_desc *desc = &sram_desc[bank];
77
78 desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
79 if (bank > 0)
80 desc->virtual -= sram_desc[bank - 1].length;
81
82 desc->pfn = __phys_to_pfn(base);
83 desc->length = length;
84 desc->type = MT_MEMORY_RWX_NONCACHED;
85
86 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
87 base, length, desc->virtual);
88
89 iotable_init(desc, 1);
90}
91
92static struct map_desc at91_io_desc __initdata __maybe_unused = {
93 .virtual = (unsigned long)AT91_VA_BASE_SYS,
94 .pfn = __phys_to_pfn(AT91_BASE_SYS),
95 .length = SZ_16K,
96 .type = MT_DEVICE,
97};
98
99static void __init soc_detect(u32 dbgu_base)
100{
101 u32 cidr, socid;
102
103 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
104 socid = cidr & ~AT91_CIDR_VERSION;
105
106 switch (socid) {
107 case ARCH_ID_AT91RM9200:
108 at91_soc_initdata.type = AT91_SOC_RM9200;
109 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
110 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
111 at91_boot_soc = at91rm9200_soc;
112 break;
113
114 case ARCH_ID_AT91SAM9260:
115 at91_soc_initdata.type = AT91_SOC_SAM9260;
116 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
117 at91_boot_soc = at91sam9260_soc;
118 break;
119
120 case ARCH_ID_AT91SAM9261:
121 at91_soc_initdata.type = AT91_SOC_SAM9261;
122 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
123 at91_boot_soc = at91sam9261_soc;
124 break;
125
126 case ARCH_ID_AT91SAM9263:
127 at91_soc_initdata.type = AT91_SOC_SAM9263;
128 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
129 at91_boot_soc = at91sam9263_soc;
130 break;
131
132 case ARCH_ID_AT91SAM9G20:
133 at91_soc_initdata.type = AT91_SOC_SAM9G20;
134 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
135 at91_boot_soc = at91sam9260_soc;
136 break;
137
138 case ARCH_ID_AT91SAM9G45:
139 at91_soc_initdata.type = AT91_SOC_SAM9G45;
140 if (cidr == ARCH_ID_AT91SAM9G45ES)
141 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
142 at91_boot_soc = at91sam9g45_soc;
143 break;
144
145 case ARCH_ID_AT91SAM9RL64:
146 at91_soc_initdata.type = AT91_SOC_SAM9RL;
147 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
148 at91_boot_soc = at91sam9rl_soc;
149 break;
150
151 case ARCH_ID_AT91SAM9X5:
152 at91_soc_initdata.type = AT91_SOC_SAM9X5;
153 at91_boot_soc = at91sam9x5_soc;
154 break;
155
156 case ARCH_ID_AT91SAM9N12:
157 at91_soc_initdata.type = AT91_SOC_SAM9N12;
158 at91_boot_soc = at91sam9n12_soc;
159 break;
160
161 case ARCH_ID_SAMA5D3:
162 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
163 at91_boot_soc = sama5d3_soc;
164 break;
165 }
166
167 /* at91sam9g10 */
168 if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
169 at91_soc_initdata.type = AT91_SOC_SAM9G10;
170 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
171 at91_boot_soc = at91sam9261_soc;
172 }
173 /* at91sam9xe */
174 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
175 at91_soc_initdata.type = AT91_SOC_SAM9260;
176 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
177 at91_boot_soc = at91sam9260_soc;
178 }
179
180 if (!at91_soc_is_detected())
181 return;
182
183 at91_soc_initdata.cidr = cidr;
184
185 /* sub version of soc */
186 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
187
188 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
189 switch (at91_soc_initdata.exid) {
190 case ARCH_EXID_AT91SAM9M10:
191 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
192 break;
193 case ARCH_EXID_AT91SAM9G46:
194 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
195 break;
196 case ARCH_EXID_AT91SAM9M11:
197 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
198 break;
199 }
200 }
201
202 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
203 switch (at91_soc_initdata.exid) {
204 case ARCH_EXID_AT91SAM9G15:
205 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
206 break;
207 case ARCH_EXID_AT91SAM9G35:
208 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
209 break;
210 case ARCH_EXID_AT91SAM9X35:
211 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
212 break;
213 case ARCH_EXID_AT91SAM9G25:
214 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
215 break;
216 case ARCH_EXID_AT91SAM9X25:
217 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
218 break;
219 }
220 }
221
222 if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
223 switch (at91_soc_initdata.exid) {
224 case ARCH_EXID_SAMA5D31:
225 at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
226 break;
227 case ARCH_EXID_SAMA5D33:
228 at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
229 break;
230 case ARCH_EXID_SAMA5D34:
231 at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
232 break;
233 case ARCH_EXID_SAMA5D35:
234 at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
235 break;
236 case ARCH_EXID_SAMA5D36:
237 at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
238 break;
239 }
240 }
241}
242
243static const char *soc_name[] = {
244 [AT91_SOC_RM9200] = "at91rm9200",
245 [AT91_SOC_SAM9260] = "at91sam9260",
246 [AT91_SOC_SAM9261] = "at91sam9261",
247 [AT91_SOC_SAM9263] = "at91sam9263",
248 [AT91_SOC_SAM9G10] = "at91sam9g10",
249 [AT91_SOC_SAM9G20] = "at91sam9g20",
250 [AT91_SOC_SAM9G45] = "at91sam9g45",
251 [AT91_SOC_SAM9RL] = "at91sam9rl",
252 [AT91_SOC_SAM9X5] = "at91sam9x5",
253 [AT91_SOC_SAM9N12] = "at91sam9n12",
254 [AT91_SOC_SAMA5D3] = "sama5d3",
255 [AT91_SOC_UNKNOWN] = "Unknown",
256};
257
258const char *at91_get_soc_type(struct at91_socinfo *c)
259{
260 return soc_name[c->type];
261}
262EXPORT_SYMBOL(at91_get_soc_type);
263
264static const char *soc_subtype_name[] = {
265 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
266 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
267 [AT91_SOC_SAM9XE] = "at91sam9xe",
268 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
269 [AT91_SOC_SAM9M10] = "at91sam9m10",
270 [AT91_SOC_SAM9G46] = "at91sam9g46",
271 [AT91_SOC_SAM9M11] = "at91sam9m11",
272 [AT91_SOC_SAM9G15] = "at91sam9g15",
273 [AT91_SOC_SAM9G35] = "at91sam9g35",
274 [AT91_SOC_SAM9X35] = "at91sam9x35",
275 [AT91_SOC_SAM9G25] = "at91sam9g25",
276 [AT91_SOC_SAM9X25] = "at91sam9x25",
277 [AT91_SOC_SAMA5D31] = "sama5d31",
278 [AT91_SOC_SAMA5D33] = "sama5d33",
279 [AT91_SOC_SAMA5D34] = "sama5d34",
280 [AT91_SOC_SAMA5D35] = "sama5d35",
281 [AT91_SOC_SAMA5D36] = "sama5d36",
282 [AT91_SOC_SUBTYPE_NONE] = "None",
283 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
284};
285
286const char *at91_get_soc_subtype(struct at91_socinfo *c)
287{
288 return soc_subtype_name[c->subtype];
289}
290EXPORT_SYMBOL(at91_get_soc_subtype);
291
292void __init at91_map_io(void)
293{
294 /* Map peripherals */
295 iotable_init(&at91_io_desc, 1);
296
297 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
298 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
299
300 soc_detect(AT91_BASE_DBGU0);
301 if (!at91_soc_is_detected())
302 soc_detect(AT91_BASE_DBGU1);
303
304 if (!at91_soc_is_detected())
305 panic("AT91: Impossible to detect the SOC type");
306
307 pr_info("AT91: Detected soc type: %s\n",
308 at91_get_soc_type(&at91_soc_initdata));
309 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
310 pr_info("AT91: Detected soc subtype: %s\n",
311 at91_get_soc_subtype(&at91_soc_initdata));
312
313 if (!at91_soc_is_enabled())
314 panic("AT91: Soc not enabled");
315
316 if (at91_boot_soc.map_io)
317 at91_boot_soc.map_io();
318}
319
320void __iomem *at91_shdwc_base = NULL;
321
322static void at91sam9_poweroff(void)
323{
324 at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
325}
326
327void __init at91_ioremap_shdwc(u32 base_addr)
328{
329 at91_shdwc_base = ioremap(base_addr, 16);
330 if (!at91_shdwc_base)
331 panic("Impossible to ioremap at91_shdwc_base\n");
332 pm_power_off = at91sam9_poweroff;
333}
334
335void __iomem *at91_rstc_base;
336
337void __init at91_ioremap_rstc(u32 base_addr)
338{
339 at91_rstc_base = ioremap(base_addr, 16);
340 if (!at91_rstc_base)
341 panic("Impossible to ioremap at91_rstc_base\n");
342}
343
344void __iomem *at91_matrix_base;
345EXPORT_SYMBOL_GPL(at91_matrix_base);
346
347void __init at91_ioremap_matrix(u32 base_addr)
348{
349 at91_matrix_base = ioremap(base_addr, 512);
350 if (!at91_matrix_base)
351 panic("Impossible to ioremap at91_matrix_base\n");
352}
353
354#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
355static struct of_device_id rstc_ids[] = {
356 { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
357 { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
358 { /*sentinel*/ }
359};
360
361static void at91_dt_rstc(void)
362{
363 struct device_node *np;
364 const struct of_device_id *of_id;
365
366 np = of_find_matching_node(NULL, rstc_ids);
367 if (!np)
368 panic("unable to find compatible rstc node in dtb\n");
369
370 at91_rstc_base = of_iomap(np, 0);
371 if (!at91_rstc_base)
372 panic("unable to map rstc cpu registers\n");
373
374 of_id = of_match_node(rstc_ids, np);
375 if (!of_id)
376 panic("AT91: rtsc no restart function available\n");
377
378 arm_pm_restart = of_id->data;
379
380 of_node_put(np);
381}
382
383static struct of_device_id ramc_ids[] = {
384 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
385 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
386 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
387 { /*sentinel*/ }
388};
389
390static void at91_dt_ramc(void)
391{
392 struct device_node *np;
393 const struct of_device_id *of_id;
394
395 np = of_find_matching_node(NULL, ramc_ids);
396 if (!np)
397 panic("unable to find compatible ram controller node in dtb\n");
398
399 at91_ramc_base[0] = of_iomap(np, 0);
400 if (!at91_ramc_base[0])
401 panic("unable to map ramc[0] cpu registers\n");
402 /* the controller may have 2 banks */
403 at91_ramc_base[1] = of_iomap(np, 1);
404
405 of_id = of_match_node(ramc_ids, np);
406 if (!of_id)
407 pr_warn("AT91: ramc no standby function available\n");
408 else
409 at91_pm_set_standby(of_id->data);
410
411 of_node_put(np);
412}
413
414static struct of_device_id shdwc_ids[] = {
415 { .compatible = "atmel,at91sam9260-shdwc", },
416 { .compatible = "atmel,at91sam9rl-shdwc", },
417 { .compatible = "atmel,at91sam9x5-shdwc", },
418 { /*sentinel*/ }
419};
420
421static const char *shdwc_wakeup_modes[] = {
422 [AT91_SHDW_WKMODE0_NONE] = "none",
423 [AT91_SHDW_WKMODE0_HIGH] = "high",
424 [AT91_SHDW_WKMODE0_LOW] = "low",
425 [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
426};
427
428const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
429{
430 const char *pm;
431 int err, i;
432
433 err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
434 if (err < 0)
435 return AT91_SHDW_WKMODE0_ANYLEVEL;
436
437 for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
438 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
439 return i;
440
441 return -ENODEV;
442}
443
444static void at91_dt_shdwc(void)
445{
446 struct device_node *np;
447 int wakeup_mode;
448 u32 reg;
449 u32 mode = 0;
450
451 np = of_find_matching_node(NULL, shdwc_ids);
452 if (!np) {
453 pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
454 return;
455 }
456
457 at91_shdwc_base = of_iomap(np, 0);
458 if (!at91_shdwc_base)
459 panic("AT91: unable to map shdwc cpu registers\n");
460
461 wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
462 if (wakeup_mode < 0) {
463 pr_warn("AT91: shdwc unknown wakeup mode\n");
464 goto end;
465 }
466
467 if (!of_property_read_u32(np, "atmel,wakeup-counter", ®)) {
468 if (reg > AT91_SHDW_CPTWK0_MAX) {
469 pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
470 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
471 reg = AT91_SHDW_CPTWK0_MAX;
472 }
473 mode |= AT91_SHDW_CPTWK0_(reg);
474 }
475
476 if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
477 mode |= AT91_SHDW_RTCWKEN;
478
479 if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
480 mode |= AT91_SHDW_RTTWKEN;
481
482 at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
483
484end:
485 pm_power_off = at91sam9_poweroff;
486
487 of_node_put(np);
488}
489
490void __init at91rm9200_dt_initialize(void)
491{
492 at91_dt_ramc();
493
494 /* Init clock subsystem */
495 at91_dt_clock_init();
496
497 /* Register the processor-specific clocks */
498 if (at91_boot_soc.register_clocks)
499 at91_boot_soc.register_clocks();
500
501 at91_boot_soc.init();
502}
503
504void __init at91_dt_initialize(void)
505{
506 at91_dt_rstc();
507 at91_dt_ramc();
508 at91_dt_shdwc();
509
510 /* Init clock subsystem */
511 at91_dt_clock_init();
512
513 /* Register the processor-specific clocks */
514 if (at91_boot_soc.register_clocks)
515 at91_boot_soc.register_clocks();
516
517 if (at91_boot_soc.init)
518 at91_boot_soc.init();
519}
520#endif
521
522void __init at91_initialize(unsigned long main_clock)
523{
524 at91_boot_soc.ioremap_registers();
525
526 /* Init clock subsystem */
527 at91_clock_init(main_clock);
528
529 /* Register the processor-specific clocks */
530 at91_boot_soc.register_clocks();
531
532 at91_boot_soc.init();
533
534 pinctrl_provide_dummies();
535}