1/dts-v1/;
  2
  3#include "skeleton.dtsi"
  4
  5#include <dt-bindings/clock/qcom,gcc-msm8974.h>
  6
  7/ {
  8	model = "Qualcomm MSM8974";
  9	compatible = "qcom,msm8974";
 10	interrupt-parent = <&intc>;
 11
 12	cpus {
 13		#address-cells = <1>;
 14		#size-cells = <0>;
 15		interrupts = <1 9 0xf04>;
 16		compatible = "qcom,krait";
 17		enable-method = "qcom,kpss-acc-v2";
 18
 19		cpu@0 {
 20			device_type = "cpu";
 21			reg = <0>;
 22			next-level-cache = <&L2>;
 23			qcom,acc = <&acc0>;
 24		};
 25
 26		cpu@1 {
 27			device_type = "cpu";
 28			reg = <1>;
 29			next-level-cache = <&L2>;
 30			qcom,acc = <&acc1>;
 31		};
 32
 33		cpu@2 {
 34			device_type = "cpu";
 35			reg = <2>;
 36			next-level-cache = <&L2>;
 37			qcom,acc = <&acc2>;
 38		};
 39
 40		cpu@3 {
 41			device_type = "cpu";
 42			reg = <3>;
 43			next-level-cache = <&L2>;
 44			qcom,acc = <&acc3>;
 45		};
 46
 47		L2: l2-cache {
 48			compatible = "cache";
 49			cache-level = <2>;
 50			interrupts = <0 2 0x4>;
 51			qcom,saw = <&saw_l2>;
 52		};
 53	};
 54
 55	cpu-pmu {
 56		compatible = "qcom,krait-pmu";
 57		interrupts = <1 7 0xf04>;
 58	};
 59
 60	soc: soc {
 61		#address-cells = <1>;
 62		#size-cells = <1>;
 63		ranges;
 64		compatible = "simple-bus";
 65
 66		intc: interrupt-controller@f9000000 {
 67			compatible = "qcom,msm-qgic2";
 68			interrupt-controller;
 69			#interrupt-cells = <3>;
 70			reg = <0xf9000000 0x1000>,
 71			      <0xf9002000 0x1000>;
 72		};
 73
 74		timer {
 75			compatible = "arm,armv7-timer";
 76			interrupts = <1 2 0xf08>,
 77				     <1 3 0xf08>,
 78				     <1 4 0xf08>,
 79				     <1 1 0xf08>;
 80			clock-frequency = <19200000>;
 81		};
 82
 83		timer@f9020000 {
 84			#address-cells = <1>;
 85			#size-cells = <1>;
 86			ranges;
 87			compatible = "arm,armv7-timer-mem";
 88			reg = <0xf9020000 0x1000>;
 89			clock-frequency = <19200000>;
 90
 91			frame@f9021000 {
 92				frame-number = <0>;
 93				interrupts = <0 8 0x4>,
 94					     <0 7 0x4>;
 95				reg = <0xf9021000 0x1000>,
 96				      <0xf9022000 0x1000>;
 97			};
 98
 99			frame@f9023000 {
100				frame-number = <1>;
101				interrupts = <0 9 0x4>;
102				reg = <0xf9023000 0x1000>;
103				status = "disabled";
104			};
105
106			frame@f9024000 {
107				frame-number = <2>;
108				interrupts = <0 10 0x4>;
109				reg = <0xf9024000 0x1000>;
110				status = "disabled";
111			};
112
113			frame@f9025000 {
114				frame-number = <3>;
115				interrupts = <0 11 0x4>;
116				reg = <0xf9025000 0x1000>;
117				status = "disabled";
118			};
119
120			frame@f9026000 {
121				frame-number = <4>;
122				interrupts = <0 12 0x4>;
123				reg = <0xf9026000 0x1000>;
124				status = "disabled";
125			};
126
127			frame@f9027000 {
128				frame-number = <5>;
129				interrupts = <0 13 0x4>;
130				reg = <0xf9027000 0x1000>;
131				status = "disabled";
132			};
133
134			frame@f9028000 {
135				frame-number = <6>;
136				interrupts = <0 14 0x4>;
137				reg = <0xf9028000 0x1000>;
138				status = "disabled";
139			};
140		};
141
142		saw_l2: regulator@f9012000 {
143			compatible = "qcom,saw2";
144			reg = <0xf9012000 0x1000>;
145			regulator;
146		};
147
148		acc0: clock-controller@f9088000 {
149			compatible = "qcom,kpss-acc-v2";
150			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
151		};
152
153		acc1: clock-controller@f9098000 {
154			compatible = "qcom,kpss-acc-v2";
155			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
156		};
157
158		acc2: clock-controller@f90a8000 {
159			compatible = "qcom,kpss-acc-v2";
160			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
161		};
162
163		acc3: clock-controller@f90b8000 {
164			compatible = "qcom,kpss-acc-v2";
165			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
166		};
167
168		restart@fc4ab000 {
169			compatible = "qcom,pshold";
170			reg = <0xfc4ab000 0x4>;
171		};
172
173		gcc: clock-controller@fc400000 {
174			compatible = "qcom,gcc-msm8974";
175			#clock-cells = <1>;
176			#reset-cells = <1>;
177			reg = <0xfc400000 0x4000>;
178		};
179
180		mmcc: clock-controller@fd8c0000 {
181			compatible = "qcom,mmcc-msm8974";
182			#clock-cells = <1>;
183			#reset-cells = <1>;
184			reg = <0xfd8c0000 0x6000>;
185		};
186
187		serial@f991e000 {
188			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
189			reg = <0xf991e000 0x1000>;
190			interrupts = <0 108 0x0>;
191			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
192			clock-names = "core", "iface";
193		};
194
195		rng@f9bff000 {
196			compatible = "qcom,prng";
197			reg = <0xf9bff000 0x200>;
198			clocks = <&gcc GCC_PRNG_AHB_CLK>;
199			clock-names = "core";
200		};
201	};
202};