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1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include "skeleton.dtsi"
14#include "imx51-pinfunc.h"
15#include <dt-bindings/clock/imx5-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21 aliases {
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 mmc0 = &esdhc1;
29 mmc1 = &esdhc2;
30 mmc2 = &esdhc3;
31 mmc3 = &esdhc4;
32 serial0 = &uart1;
33 serial1 = &uart2;
34 serial2 = &uart3;
35 spi0 = &ecspi1;
36 spi1 = &ecspi2;
37 spi2 = &cspi;
38 };
39
40 tzic: tz-interrupt-controller@e0000000 {
41 compatible = "fsl,imx51-tzic", "fsl,tzic";
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 reg = <0xe0000000 0x4000>;
45 };
46
47 clocks {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 ckil {
52 compatible = "fsl,imx-ckil", "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <32768>;
55 };
56
57 ckih1 {
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <0>;
61 };
62
63 ckih2 {
64 compatible = "fsl,imx-ckih2", "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
67 };
68
69 osc {
70 compatible = "fsl,imx-osc", "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
73 };
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 cpu: cpu@0 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a8";
82 reg = <0>;
83 clock-latency = <62500>;
84 clocks = <&clks IMX5_CLK_CPU_PODF>;
85 clock-names = "cpu";
86 operating-points = <
87 166000 1000000
88 600000 1050000
89 800000 1100000
90 >;
91 voltage-tolerance = <5>;
92 };
93 };
94
95 usbphy {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "simple-bus";
99
100 usbphy0: usbphy@0 {
101 compatible = "usb-nop-xceiv";
102 reg = <0>;
103 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
104 clock-names = "main_clk";
105 };
106 };
107
108 display-subsystem {
109 compatible = "fsl,imx-display-subsystem";
110 ports = <&ipu_di0>, <&ipu_di1>;
111 };
112
113 soc {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "simple-bus";
117 interrupt-parent = <&tzic>;
118 ranges;
119
120 iram: iram@1ffe0000 {
121 compatible = "mmio-sram";
122 reg = <0x1ffe0000 0x20000>;
123 };
124
125 ipu: ipu@40000000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "fsl,imx51-ipu";
129 reg = <0x40000000 0x20000000>;
130 interrupts = <11 10>;
131 clocks = <&clks IMX5_CLK_IPU_GATE>,
132 <&clks IMX5_CLK_IPU_DI0_GATE>,
133 <&clks IMX5_CLK_IPU_DI1_GATE>;
134 clock-names = "bus", "di0", "di1";
135 resets = <&src 2>;
136
137 ipu_di0: port@2 {
138 reg = <2>;
139
140 ipu_di0_disp0: endpoint {
141 };
142 };
143
144 ipu_di1: port@3 {
145 reg = <3>;
146
147 ipu_di1_disp1: endpoint {
148 };
149 };
150 };
151
152 aips@70000000 { /* AIPS1 */
153 compatible = "fsl,aips-bus", "simple-bus";
154 #address-cells = <1>;
155 #size-cells = <1>;
156 reg = <0x70000000 0x10000000>;
157 ranges;
158
159 spba@70000000 {
160 compatible = "fsl,spba-bus", "simple-bus";
161 #address-cells = <1>;
162 #size-cells = <1>;
163 reg = <0x70000000 0x40000>;
164 ranges;
165
166 esdhc1: esdhc@70004000 {
167 compatible = "fsl,imx51-esdhc";
168 reg = <0x70004000 0x4000>;
169 interrupts = <1>;
170 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
171 <&clks IMX5_CLK_DUMMY>,
172 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
173 clock-names = "ipg", "ahb", "per";
174 status = "disabled";
175 };
176
177 esdhc2: esdhc@70008000 {
178 compatible = "fsl,imx51-esdhc";
179 reg = <0x70008000 0x4000>;
180 interrupts = <2>;
181 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
184 clock-names = "ipg", "ahb", "per";
185 bus-width = <4>;
186 status = "disabled";
187 };
188
189 uart3: serial@7000c000 {
190 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
191 reg = <0x7000c000 0x4000>;
192 interrupts = <33>;
193 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
194 <&clks IMX5_CLK_UART3_PER_GATE>;
195 clock-names = "ipg", "per";
196 status = "disabled";
197 };
198
199 ecspi1: ecspi@70010000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "fsl,imx51-ecspi";
203 reg = <0x70010000 0x4000>;
204 interrupts = <36>;
205 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
206 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
210
211 ssi2: ssi@70014000 {
212 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
213 reg = <0x70014000 0x4000>;
214 interrupts = <30>;
215 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
216 dmas = <&sdma 24 1 0>,
217 <&sdma 25 1 0>;
218 dma-names = "rx", "tx";
219 fsl,fifo-depth = <15>;
220 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
221 status = "disabled";
222 };
223
224 esdhc3: esdhc@70020000 {
225 compatible = "fsl,imx51-esdhc";
226 reg = <0x70020000 0x4000>;
227 interrupts = <3>;
228 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
229 <&clks IMX5_CLK_DUMMY>,
230 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
231 clock-names = "ipg", "ahb", "per";
232 bus-width = <4>;
233 status = "disabled";
234 };
235
236 esdhc4: esdhc@70024000 {
237 compatible = "fsl,imx51-esdhc";
238 reg = <0x70024000 0x4000>;
239 interrupts = <4>;
240 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
241 <&clks IMX5_CLK_DUMMY>,
242 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
243 clock-names = "ipg", "ahb", "per";
244 bus-width = <4>;
245 status = "disabled";
246 };
247 };
248
249 usbotg: usb@73f80000 {
250 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
251 reg = <0x73f80000 0x0200>;
252 interrupts = <18>;
253 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
254 fsl,usbmisc = <&usbmisc 0>;
255 fsl,usbphy = <&usbphy0>;
256 status = "disabled";
257 };
258
259 usbh1: usb@73f80200 {
260 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
261 reg = <0x73f80200 0x0200>;
262 interrupts = <14>;
263 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
264 fsl,usbmisc = <&usbmisc 1>;
265 status = "disabled";
266 };
267
268 usbh2: usb@73f80400 {
269 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
270 reg = <0x73f80400 0x0200>;
271 interrupts = <16>;
272 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
273 fsl,usbmisc = <&usbmisc 2>;
274 status = "disabled";
275 };
276
277 usbh3: usb@73f80600 {
278 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
279 reg = <0x73f80600 0x0200>;
280 interrupts = <17>;
281 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
282 fsl,usbmisc = <&usbmisc 3>;
283 status = "disabled";
284 };
285
286 usbmisc: usbmisc@73f80800 {
287 #index-cells = <1>;
288 compatible = "fsl,imx51-usbmisc";
289 reg = <0x73f80800 0x200>;
290 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
291 };
292
293 gpio1: gpio@73f84000 {
294 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
295 reg = <0x73f84000 0x4000>;
296 interrupts = <50 51>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
302
303 gpio2: gpio@73f88000 {
304 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
305 reg = <0x73f88000 0x4000>;
306 interrupts = <52 53>;
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 gpio3: gpio@73f8c000 {
314 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
315 reg = <0x73f8c000 0x4000>;
316 interrupts = <54 55>;
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 gpio4: gpio@73f90000 {
324 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
325 reg = <0x73f90000 0x4000>;
326 interrupts = <56 57>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 kpp: kpp@73f94000 {
334 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
335 reg = <0x73f94000 0x4000>;
336 interrupts = <60>;
337 clocks = <&clks IMX5_CLK_DUMMY>;
338 status = "disabled";
339 };
340
341 wdog1: wdog@73f98000 {
342 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
343 reg = <0x73f98000 0x4000>;
344 interrupts = <58>;
345 clocks = <&clks IMX5_CLK_DUMMY>;
346 };
347
348 wdog2: wdog@73f9c000 {
349 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
350 reg = <0x73f9c000 0x4000>;
351 interrupts = <59>;
352 clocks = <&clks IMX5_CLK_DUMMY>;
353 status = "disabled";
354 };
355
356 gpt: timer@73fa0000 {
357 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
358 reg = <0x73fa0000 0x4000>;
359 interrupts = <39>;
360 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
361 <&clks IMX5_CLK_GPT_HF_GATE>;
362 clock-names = "ipg", "per";
363 };
364
365 iomuxc: iomuxc@73fa8000 {
366 compatible = "fsl,imx51-iomuxc";
367 reg = <0x73fa8000 0x4000>;
368 };
369
370 pwm1: pwm@73fb4000 {
371 #pwm-cells = <2>;
372 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
373 reg = <0x73fb4000 0x4000>;
374 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
375 <&clks IMX5_CLK_PWM1_HF_GATE>;
376 clock-names = "ipg", "per";
377 interrupts = <61>;
378 };
379
380 pwm2: pwm@73fb8000 {
381 #pwm-cells = <2>;
382 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
383 reg = <0x73fb8000 0x4000>;
384 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
385 <&clks IMX5_CLK_PWM2_HF_GATE>;
386 clock-names = "ipg", "per";
387 interrupts = <94>;
388 };
389
390 uart1: serial@73fbc000 {
391 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
392 reg = <0x73fbc000 0x4000>;
393 interrupts = <31>;
394 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
395 <&clks IMX5_CLK_UART1_PER_GATE>;
396 clock-names = "ipg", "per";
397 status = "disabled";
398 };
399
400 uart2: serial@73fc0000 {
401 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
402 reg = <0x73fc0000 0x4000>;
403 interrupts = <32>;
404 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
405 <&clks IMX5_CLK_UART2_PER_GATE>;
406 clock-names = "ipg", "per";
407 status = "disabled";
408 };
409
410 src: src@73fd0000 {
411 compatible = "fsl,imx51-src";
412 reg = <0x73fd0000 0x4000>;
413 #reset-cells = <1>;
414 };
415
416 clks: ccm@73fd4000{
417 compatible = "fsl,imx51-ccm";
418 reg = <0x73fd4000 0x4000>;
419 interrupts = <0 71 0x04 0 72 0x04>;
420 #clock-cells = <1>;
421 };
422 };
423
424 aips@80000000 { /* AIPS2 */
425 compatible = "fsl,aips-bus", "simple-bus";
426 #address-cells = <1>;
427 #size-cells = <1>;
428 reg = <0x80000000 0x10000000>;
429 ranges;
430
431 iim: iim@83f98000 {
432 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
433 reg = <0x83f98000 0x4000>;
434 interrupts = <69>;
435 clocks = <&clks IMX5_CLK_IIM_GATE>;
436 };
437
438 owire: owire@83fa4000 {
439 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
440 reg = <0x83fa4000 0x4000>;
441 interrupts = <88>;
442 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
443 status = "disabled";
444 };
445
446 ecspi2: ecspi@83fac000 {
447 #address-cells = <1>;
448 #size-cells = <0>;
449 compatible = "fsl,imx51-ecspi";
450 reg = <0x83fac000 0x4000>;
451 interrupts = <37>;
452 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
453 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
454 clock-names = "ipg", "per";
455 status = "disabled";
456 };
457
458 sdma: sdma@83fb0000 {
459 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
460 reg = <0x83fb0000 0x4000>;
461 interrupts = <6>;
462 clocks = <&clks IMX5_CLK_SDMA_GATE>,
463 <&clks IMX5_CLK_SDMA_GATE>;
464 clock-names = "ipg", "ahb";
465 #dma-cells = <3>;
466 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
467 };
468
469 cspi: cspi@83fc0000 {
470 #address-cells = <1>;
471 #size-cells = <0>;
472 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
473 reg = <0x83fc0000 0x4000>;
474 interrupts = <38>;
475 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
476 <&clks IMX5_CLK_CSPI_IPG_GATE>;
477 clock-names = "ipg", "per";
478 status = "disabled";
479 };
480
481 i2c2: i2c@83fc4000 {
482 #address-cells = <1>;
483 #size-cells = <0>;
484 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
485 reg = <0x83fc4000 0x4000>;
486 interrupts = <63>;
487 clocks = <&clks IMX5_CLK_I2C2_GATE>;
488 status = "disabled";
489 };
490
491 i2c1: i2c@83fc8000 {
492 #address-cells = <1>;
493 #size-cells = <0>;
494 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
495 reg = <0x83fc8000 0x4000>;
496 interrupts = <62>;
497 clocks = <&clks IMX5_CLK_I2C1_GATE>;
498 status = "disabled";
499 };
500
501 ssi1: ssi@83fcc000 {
502 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
503 reg = <0x83fcc000 0x4000>;
504 interrupts = <29>;
505 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
506 dmas = <&sdma 28 0 0>,
507 <&sdma 29 0 0>;
508 dma-names = "rx", "tx";
509 fsl,fifo-depth = <15>;
510 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
511 status = "disabled";
512 };
513
514 audmux: audmux@83fd0000 {
515 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
516 reg = <0x83fd0000 0x4000>;
517 clocks = <&clks IMX5_CLK_DUMMY>;
518 clock-names = "audmux";
519 status = "disabled";
520 };
521
522 weim: weim@83fda000 {
523 #address-cells = <2>;
524 #size-cells = <1>;
525 compatible = "fsl,imx51-weim";
526 reg = <0x83fda000 0x1000>;
527 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
528 ranges = <
529 0 0 0xb0000000 0x08000000
530 1 0 0xb8000000 0x08000000
531 2 0 0xc0000000 0x08000000
532 3 0 0xc8000000 0x04000000
533 4 0 0xcc000000 0x02000000
534 5 0 0xce000000 0x02000000
535 >;
536 status = "disabled";
537 };
538
539 nfc: nand@83fdb000 {
540 compatible = "fsl,imx51-nand";
541 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
542 interrupts = <8>;
543 clocks = <&clks IMX5_CLK_NFC_GATE>;
544 status = "disabled";
545 };
546
547 pata: pata@83fe0000 {
548 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
549 reg = <0x83fe0000 0x4000>;
550 interrupts = <70>;
551 clocks = <&clks IMX5_CLK_PATA_GATE>;
552 status = "disabled";
553 };
554
555 ssi3: ssi@83fe8000 {
556 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
557 reg = <0x83fe8000 0x4000>;
558 interrupts = <96>;
559 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
560 dmas = <&sdma 46 0 0>,
561 <&sdma 47 0 0>;
562 dma-names = "rx", "tx";
563 fsl,fifo-depth = <15>;
564 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
565 status = "disabled";
566 };
567
568 fec: ethernet@83fec000 {
569 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
570 reg = <0x83fec000 0x4000>;
571 interrupts = <87>;
572 clocks = <&clks IMX5_CLK_FEC_GATE>,
573 <&clks IMX5_CLK_FEC_GATE>,
574 <&clks IMX5_CLK_FEC_GATE>;
575 clock-names = "ipg", "ahb", "ptp";
576 status = "disabled";
577 };
578 };
579 };
580};