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1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx51.dtsi"
15
16/ {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
20 memory {
21 reg = <0x90000000 0x20000000>;
22 };
23
24 display0: display@di0 {
25 compatible = "fsl,imx-parallel-display";
26 interface-pix-fmt = "rgb24";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_ipu_disp1>;
29 display-timings {
30 native-mode = <&timing0>;
31 timing0: dvi {
32 clock-frequency = <65000000>;
33 hactive = <1024>;
34 vactive = <768>;
35 hback-porch = <220>;
36 hfront-porch = <40>;
37 vback-porch = <21>;
38 vfront-porch = <7>;
39 hsync-len = <60>;
40 vsync-len = <10>;
41 };
42 };
43
44 port {
45 display0_in: endpoint {
46 remote-endpoint = <&ipu_di0_disp0>;
47 };
48 };
49 };
50
51 display1: display@di1 {
52 compatible = "fsl,imx-parallel-display";
53 interface-pix-fmt = "rgb565";
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_ipu_disp2>;
56 status = "disabled";
57 display-timings {
58 native-mode = <&timing1>;
59 timing1: claawvga {
60 clock-frequency = <27000000>;
61 hactive = <800>;
62 vactive = <480>;
63 hback-porch = <40>;
64 hfront-porch = <60>;
65 vback-porch = <10>;
66 vfront-porch = <10>;
67 hsync-len = <20>;
68 vsync-len = <10>;
69 hsync-active = <0>;
70 vsync-active = <0>;
71 de-active = <1>;
72 pixelclk-active = <0>;
73 };
74 };
75
76 port {
77 display1_in: endpoint {
78 remote-endpoint = <&ipu_di1_disp1>;
79 };
80 };
81 };
82
83 gpio-keys {
84 compatible = "gpio-keys";
85
86 power {
87 label = "Power Button";
88 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
89 linux,code = <116>; /* KEY_POWER */
90 gpio-key,wakeup;
91 };
92 };
93
94 leds {
95 compatible = "gpio-leds";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_gpio_leds>;
98
99 led-diagnostic {
100 label = "diagnostic";
101 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
102 };
103 };
104
105 sound {
106 compatible = "fsl,imx51-babbage-sgtl5000",
107 "fsl,imx-audio-sgtl5000";
108 model = "imx51-babbage-sgtl5000";
109 ssi-controller = <&ssi2>;
110 audio-codec = <&sgtl5000>;
111 audio-routing =
112 "MIC_IN", "Mic Jack",
113 "Mic Jack", "Mic Bias",
114 "Headphone Jack", "HP_OUT";
115 mux-int-port = <2>;
116 mux-ext-port = <3>;
117 };
118
119 clocks {
120 ckih1 {
121 clock-frequency = <22579200>;
122 };
123
124 clk_26M: codec_clock {
125 compatible = "fixed-clock";
126 reg=<0>;
127 #clock-cells = <0>;
128 clock-frequency = <26000000>;
129 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
130 };
131 };
132};
133
134&esdhc1 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_esdhc1>;
137 fsl,cd-controller;
138 fsl,wp-controller;
139 status = "okay";
140};
141
142&esdhc2 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_esdhc2>;
145 cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
146 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
147 status = "okay";
148};
149
150&uart3 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart3>;
153 fsl,uart-has-rtscts;
154 status = "okay";
155};
156
157&ecspi1 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_ecspi1>;
160 fsl,spi-num-chipselects = <2>;
161 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
162 <&gpio4 25 GPIO_ACTIVE_LOW>;
163 status = "okay";
164
165 pmic: mc13892@0 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,mc13892";
169 spi-max-frequency = <6000000>;
170 spi-cs-high;
171 reg = <0>;
172 interrupt-parent = <&gpio1>;
173 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
174
175 regulators {
176 sw1_reg: sw1 {
177 regulator-min-microvolt = <600000>;
178 regulator-max-microvolt = <1375000>;
179 regulator-boot-on;
180 regulator-always-on;
181 };
182
183 sw2_reg: sw2 {
184 regulator-min-microvolt = <900000>;
185 regulator-max-microvolt = <1850000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 sw3_reg: sw3 {
191 regulator-min-microvolt = <1100000>;
192 regulator-max-microvolt = <1850000>;
193 regulator-boot-on;
194 regulator-always-on;
195 };
196
197 sw4_reg: sw4 {
198 regulator-min-microvolt = <1100000>;
199 regulator-max-microvolt = <1850000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 vpll_reg: vpll {
205 regulator-min-microvolt = <1050000>;
206 regulator-max-microvolt = <1800000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
210
211 vdig_reg: vdig {
212 regulator-min-microvolt = <1650000>;
213 regulator-max-microvolt = <1650000>;
214 regulator-boot-on;
215 };
216
217 vsd_reg: vsd {
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3150000>;
220 };
221
222 vusb2_reg: vusb2 {
223 regulator-min-microvolt = <2400000>;
224 regulator-max-microvolt = <2775000>;
225 regulator-boot-on;
226 regulator-always-on;
227 };
228
229 vvideo_reg: vvideo {
230 regulator-min-microvolt = <2775000>;
231 regulator-max-microvolt = <2775000>;
232 };
233
234 vaudio_reg: vaudio {
235 regulator-min-microvolt = <2300000>;
236 regulator-max-microvolt = <3000000>;
237 };
238
239 vcam_reg: vcam {
240 regulator-min-microvolt = <2500000>;
241 regulator-max-microvolt = <3000000>;
242 };
243
244 vgen1_reg: vgen1 {
245 regulator-min-microvolt = <1200000>;
246 regulator-max-microvolt = <1200000>;
247 };
248
249 vgen2_reg: vgen2 {
250 regulator-min-microvolt = <1200000>;
251 regulator-max-microvolt = <3150000>;
252 regulator-always-on;
253 };
254
255 vgen3_reg: vgen3 {
256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <2900000>;
258 regulator-always-on;
259 };
260 };
261 };
262
263 flash: at45db321d@1 {
264 #address-cells = <1>;
265 #size-cells = <1>;
266 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
267 spi-max-frequency = <25000000>;
268 reg = <1>;
269
270 partition@0 {
271 label = "U-Boot";
272 reg = <0x0 0x40000>;
273 read-only;
274 };
275
276 partition@40000 {
277 label = "Kernel";
278 reg = <0x40000 0x3c0000>;
279 };
280 };
281};
282
283&ipu_di0_disp0 {
284 remote-endpoint = <&display0_in>;
285};
286
287&ipu_di1_disp1 {
288 remote-endpoint = <&display1_in>;
289};
290
291&ssi2 {
292 fsl,mode = "i2s-slave";
293 status = "okay";
294};
295
296&iomuxc {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_hog>;
299
300 imx51-babbage {
301 pinctrl_hog: hoggrp {
302 fsl,pins = <
303 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
304 MX51_PAD_GPIO1_1__SD1_WP 0x20d5
305 MX51_PAD_GPIO1_5__GPIO1_5 0x100
306 MX51_PAD_GPIO1_6__GPIO1_6 0x100
307 MX51_PAD_EIM_A27__GPIO2_21 0x5
308 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
309 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
310 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
311 >;
312 };
313
314 pinctrl_audmux: audmuxgrp {
315 fsl,pins = <
316 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
317 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
318 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
319 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
320 >;
321 };
322
323 pinctrl_ecspi1: ecspi1grp {
324 fsl,pins = <
325 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
326 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
327 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
328 >;
329 };
330
331 pinctrl_esdhc1: esdhc1grp {
332 fsl,pins = <
333 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
334 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
335 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
336 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
337 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
338 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
339 >;
340 };
341
342 pinctrl_esdhc2: esdhc2grp {
343 fsl,pins = <
344 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
345 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
346 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
347 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
348 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
349 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
350 >;
351 };
352
353 pinctrl_fec: fecgrp {
354 fsl,pins = <
355 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
356 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
357 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
358 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
359 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
360 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
361 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
362 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
363 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
364 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
365 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
366 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
367 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
368 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
369 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
370 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
371 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
372 MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
373 >;
374 };
375
376 pinctrl_gpio_leds: gpioledsgrp {
377 fsl,pins = <
378 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
379 >;
380 };
381
382 pinctrl_i2c2: i2c2grp {
383 fsl,pins = <
384 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
385 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
386 >;
387 };
388
389 pinctrl_ipu_disp1: ipudisp1grp {
390 fsl,pins = <
391 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
392 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
393 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
394 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
395 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
396 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
397 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
398 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
399 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
400 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
401 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
402 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
403 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
404 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
405 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
406 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
407 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
408 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
409 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
410 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
411 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
412 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
413 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
414 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
415 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
416 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
417 >;
418 };
419
420 pinctrl_ipu_disp2: ipudisp2grp {
421 fsl,pins = <
422 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
423 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
424 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
425 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
426 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
427 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
428 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
429 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
430 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
431 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
432 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
433 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
434 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
435 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
436 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
437 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
438 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
439 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
440 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
441 MX51_PAD_DI_GP4__DI2_PIN15 0x5
442 >;
443 };
444
445 pinctrl_kpp: kppgrp {
446 fsl,pins = <
447 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
448 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
449 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
450 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
451 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
452 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
453 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
454 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
455 >;
456 };
457
458 pinctrl_uart1: uart1grp {
459 fsl,pins = <
460 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
461 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
462 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
463 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
464 >;
465 };
466
467 pinctrl_uart2: uart2grp {
468 fsl,pins = <
469 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
470 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
471 >;
472 };
473
474 pinctrl_uart3: uart3grp {
475 fsl,pins = <
476 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
477 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
478 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
479 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
480 >;
481 };
482 };
483};
484
485&uart1 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_uart1>;
488 fsl,uart-has-rtscts;
489 status = "okay";
490};
491
492&uart2 {
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_uart2>;
495 status = "okay";
496};
497
498&i2c2 {
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_i2c2>;
501 status = "okay";
502
503 sgtl5000: codec@0a {
504 compatible = "fsl,sgtl5000";
505 reg = <0x0a>;
506 clocks = <&clk_26M>;
507 VDDA-supply = <&vdig_reg>;
508 VDDIO-supply = <&vvideo_reg>;
509 };
510};
511
512&audmux {
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_audmux>;
515 status = "okay";
516};
517
518&fec {
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_fec>;
521 phy-mode = "mii";
522 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
523 phy-reset-duration = <1>;
524 status = "okay";
525};
526
527&kpp {
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_kpp>;
530 linux,keymap = <
531 MATRIX_KEY(0, 0, KEY_UP)
532 MATRIX_KEY(0, 1, KEY_DOWN)
533 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
534 MATRIX_KEY(0, 3, KEY_HOME)
535 MATRIX_KEY(1, 0, KEY_RIGHT)
536 MATRIX_KEY(1, 1, KEY_LEFT)
537 MATRIX_KEY(1, 2, KEY_ENTER)
538 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
539 MATRIX_KEY(2, 0, KEY_F6)
540 MATRIX_KEY(2, 1, KEY_F8)
541 MATRIX_KEY(2, 2, KEY_F9)
542 MATRIX_KEY(2, 3, KEY_F10)
543 MATRIX_KEY(3, 0, KEY_F1)
544 MATRIX_KEY(3, 1, KEY_F2)
545 MATRIX_KEY(3, 2, KEY_F3)
546 MATRIX_KEY(3, 3, KEY_POWER)
547 >;
548 status = "okay";
549};