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1/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton64.dtsi"
20
21#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22
23/ {
24 model = "Marvell Armada 370 and XP SoC";
25 compatible = "marvell,armada-370-xp";
26
27 aliases {
28 eth0 = ð0;
29 eth1 = ð1;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35 cpu@0 {
36 compatible = "marvell,sheeva-v7";
37 device_type = "cpu";
38 reg = <0>;
39 };
40 };
41
42 soc {
43 #address-cells = <2>;
44 #size-cells = <1>;
45 controller = <&mbusc>;
46 interrupt-parent = <&mpic>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
49
50 devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
59
60 devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
69
70 devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
79
80 devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
89
90 devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
99
100 internal-regs {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
105
106 rtc@10300 {
107 compatible = "marvell,orion-rtc";
108 reg = <0x10300 0x20>;
109 interrupts = <50>;
110 };
111
112 spi0: spi@10600 {
113 compatible = "marvell,orion-spi";
114 reg = <0x10600 0x28>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 cell-index = <0>;
118 interrupts = <30>;
119 clocks = <&coreclk 0>;
120 status = "disabled";
121 };
122
123 spi1: spi@10680 {
124 compatible = "marvell,orion-spi";
125 reg = <0x10680 0x28>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128 cell-index = <1>;
129 interrupts = <92>;
130 clocks = <&coreclk 0>;
131 status = "disabled";
132 };
133
134 i2c0: i2c@11000 {
135 compatible = "marvell,mv64xxx-i2c";
136 #address-cells = <1>;
137 #size-cells = <0>;
138 interrupts = <31>;
139 timeout-ms = <1000>;
140 clocks = <&coreclk 0>;
141 status = "disabled";
142 };
143
144 i2c1: i2c@11100 {
145 compatible = "marvell,mv64xxx-i2c";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 interrupts = <32>;
149 timeout-ms = <1000>;
150 clocks = <&coreclk 0>;
151 status = "disabled";
152 };
153
154 serial@12000 {
155 compatible = "snps,dw-apb-uart";
156 reg = <0x12000 0x100>;
157 reg-shift = <2>;
158 interrupts = <41>;
159 reg-io-width = <1>;
160 status = "disabled";
161 };
162 serial@12100 {
163 compatible = "snps,dw-apb-uart";
164 reg = <0x12100 0x100>;
165 reg-shift = <2>;
166 interrupts = <42>;
167 reg-io-width = <1>;
168 status = "disabled";
169 };
170
171 coredivclk: corediv-clock@18740 {
172 compatible = "marvell,armada-370-corediv-clock";
173 reg = <0x18740 0xc>;
174 #clock-cells = <1>;
175 clocks = <&mainpll>;
176 clock-output-names = "nand";
177 };
178
179 mbusc: mbus-controller@20000 {
180 compatible = "marvell,mbus-controller";
181 reg = <0x20000 0x100>, <0x20180 0x20>;
182 };
183
184 mpic: interrupt-controller@20000 {
185 compatible = "marvell,mpic";
186 #interrupt-cells = <1>;
187 #size-cells = <1>;
188 interrupt-controller;
189 msi-controller;
190 };
191
192 coherency-fabric@20200 {
193 compatible = "marvell,coherency-fabric";
194 reg = <0x20200 0xb0>, <0x21010 0x1c>;
195 };
196
197 timer@20300 {
198 reg = <0x20300 0x30>, <0x21040 0x30>;
199 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
200 };
201
202 watchdog@20300 {
203 reg = <0x20300 0x34>, <0x20704 0x4>;
204 };
205
206 usb@50000 {
207 compatible = "marvell,orion-ehci";
208 reg = <0x50000 0x500>;
209 interrupts = <45>;
210 status = "disabled";
211 };
212
213 usb@51000 {
214 compatible = "marvell,orion-ehci";
215 reg = <0x51000 0x500>;
216 interrupts = <46>;
217 status = "disabled";
218 };
219
220 eth0: ethernet@70000 {
221 compatible = "marvell,armada-370-neta";
222 reg = <0x70000 0x4000>;
223 interrupts = <8>;
224 clocks = <&gateclk 4>;
225 status = "disabled";
226 };
227
228 mdio {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "marvell,orion-mdio";
232 reg = <0x72004 0x4>;
233 clocks = <&gateclk 4>;
234 };
235
236 eth1: ethernet@74000 {
237 compatible = "marvell,armada-370-neta";
238 reg = <0x74000 0x4000>;
239 interrupts = <10>;
240 clocks = <&gateclk 3>;
241 status = "disabled";
242 };
243
244 sata@a0000 {
245 compatible = "marvell,armada-370-sata";
246 reg = <0xa0000 0x5000>;
247 interrupts = <55>;
248 clocks = <&gateclk 15>, <&gateclk 30>;
249 clock-names = "0", "1";
250 status = "disabled";
251 };
252
253 nand@d0000 {
254 compatible = "marvell,armada370-nand";
255 reg = <0xd0000 0x54>;
256 #address-cells = <1>;
257 #size-cells = <1>;
258 interrupts = <113>;
259 clocks = <&coredivclk 0>;
260 status = "disabled";
261 };
262
263 mvsdio@d4000 {
264 compatible = "marvell,orion-sdio";
265 reg = <0xd4000 0x200>;
266 interrupts = <54>;
267 clocks = <&gateclk 17>;
268 bus-width = <4>;
269 cap-sdio-irq;
270 cap-sd-highspeed;
271 cap-mmc-highspeed;
272 status = "disabled";
273 };
274 };
275 };
276
277 clocks {
278 /* 2 GHz fixed main PLL */
279 mainpll: mainpll {
280 compatible = "fixed-clock";
281 #clock-cells = <0>;
282 clock-frequency = <2000000000>;
283 };
284 };
285 };