Linux Audio

Check our new training course

Loading...
Note: File does not exist in v3.15.
  1.. SPDX-License-Identifier: GPL-2.0
  2
  3Kernel driver max16601
  4======================
  5
  6Supported chips:
  7
  8  * Maxim MAX16508
  9
 10    Prefix: 'max16508'
 11
 12    Addresses scanned: -
 13
 14    Datasheet: Not published
 15
 16  * Maxim MAX16600
 17
 18    Prefix: 'max16600'
 19
 20    Addresses scanned: -
 21
 22    Datasheet: Not published
 23
 24  * Maxim MAX16601
 25
 26    Prefix: 'max16601'
 27
 28    Addresses scanned: -
 29
 30    Datasheet: Not published
 31
 32  * Maxim MAX16602
 33
 34    Prefix: 'max16602'
 35
 36    Addresses scanned: -
 37
 38    Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX16602.pdf
 39
 40Author: Guenter Roeck <linux@roeck-us.net>
 41
 42
 43Description
 44-----------
 45
 46This driver supports the MAX16508 VR13 Dual-Output Voltage Regulator
 47as well as the MAX16600, MAX16601, and MAX16602 VR13.HC Dual-Output
 48Voltage Regulator chipsets.
 49
 50The driver is a client driver to the core PMBus driver.
 51Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers.
 52
 53
 54Usage Notes
 55-----------
 56
 57This driver does not auto-detect devices. You will have to instantiate the
 58devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for
 59details.
 60
 61
 62Platform data support
 63---------------------
 64
 65The driver supports standard PMBus driver platform data.
 66
 67
 68Sysfs entries
 69-------------
 70
 71The following attributes are supported.
 72
 73=============================== ===============================================
 74in1_label			"vin1"
 75in1_input			VCORE input voltage.
 76in1_alarm			Input voltage alarm.
 77
 78in2_label			"vout1"
 79in2_input			VCORE output voltage.
 80in2_alarm			Output voltage alarm.
 81
 82curr1_label			"iin1"
 83curr1_input			VCORE input current, derived from duty cycle
 84				and output current.
 85curr1_max			Maximum input current.
 86curr1_max_alarm			Current high alarm.
 87
 88curr[P+2]_label			"iin1.P"
 89curr[P+2]_input			VCORE phase P input current.
 90
 91curr[N+2]_label			"iin2"
 92curr[N+2]_input			VCORE input current, derived from sensor
 93				element.
 94				'N' is the number of enabled/populated phases.
 95
 96curr[N+3]_label			"iin3"
 97curr[N+3]_input			VSA input current.
 98
 99curr[N+4]_label			"iout1"
100curr[N+4]_input			VCORE output current.
101curr[N+4]_crit			Critical output current.
102curr[N+4]_crit_alarm		Output current critical alarm.
103curr[N+4]_max			Maximum output current.
104curr[N+4]_max_alarm		Output current high alarm.
105
106curr[N+P+5]_label		"iout1.P"
107curr[N+P+5]_input		VCORE phase P output current.
108
109curr[2*N+5]_label		"iout3"
110curr[2*N+5]_input		VSA output current.
111curr[2*N+5]_highest		Historical maximum VSA output current.
112curr[2*N+5]_reset_history	Write any value to reset curr21_highest.
113curr[2*N+5]_crit		Critical output current.
114curr[2*N+5]_crit_alarm		Output current critical alarm.
115curr[2*N+5]_max			Maximum output current.
116curr[2*N+5]_max_alarm		Output current high alarm.
117
118power1_label			"pin1"
119power1_input			Input power, derived from duty cycle and output
120				current.
121power1_alarm			Input power alarm.
122
123power2_label			"pin2"
124power2_input			Input power, derived from input current sensor.
125
126power3_label			"pout"
127power3_input			Output power.
128
129temp1_input			VCORE temperature.
130temp1_crit			Critical high temperature.
131temp1_crit_alarm		Chip temperature critical high alarm.
132temp1_max			Maximum temperature.
133temp1_max_alarm			Chip temperature high alarm.
134
135temp2_input			TSENSE_0 temperature
136temp3_input			TSENSE_1 temperature
137temp4_input			TSENSE_2 temperature
138temp5_input			TSENSE_3 temperature
139
140temp6_input			VSA temperature.
141temp6_crit			Critical high temperature.
142temp6_crit_alarm		Chip temperature critical high alarm.
143temp6_max			Maximum temperature.
144temp6_max_alarm			Chip temperature high alarm.
145=============================== ===============================================