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v6.13.7
  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * ci.h - common structures, functions, and macros of the ChipIdea driver
  4 *
  5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  6 *
  7 * Author: David Lopo
 
 
 
 
  8 */
  9
 10#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
 11#define __DRIVERS_USB_CHIPIDEA_CI_H
 12
 13#include <linux/list.h>
 14#include <linux/irqreturn.h>
 15#include <linux/usb.h>
 16#include <linux/usb/gadget.h>
 17#include <linux/usb/otg-fsm.h>
 18#include <linux/usb/otg.h>
 19#include <linux/usb/role.h>
 20#include <linux/ulpi/interface.h>
 21
 22/******************************************************************************
 23 * DEFINE
 24 *****************************************************************************/
 25#define TD_PAGE_COUNT      5
 26#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
 27#define ENDPT_MAX          32
 28#define CI_MAX_REQ_SIZE	(4 * CI_HDRC_PAGE_SIZE)
 29#define CI_MAX_BUF_SIZE	(TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
 30
 31/******************************************************************************
 32 * REGISTERS
 33 *****************************************************************************/
 34/* Identification Registers */
 35#define ID_ID				0x0
 36#define ID_HWGENERAL			0x4
 37#define ID_HWHOST			0x8
 38#define ID_HWDEVICE			0xc
 39#define ID_HWTXBUF			0x10
 40#define ID_HWRXBUF			0x14
 41#define ID_SBUSCFG			0x90
 42
 43/* register indices */
 44enum ci_hw_regs {
 45	CAP_CAPLENGTH,
 46	CAP_HCCPARAMS,
 47	CAP_DCCPARAMS,
 48	CAP_TESTMODE,
 49	CAP_LAST = CAP_TESTMODE,
 50	OP_USBCMD,
 51	OP_USBSTS,
 52	OP_USBINTR,
 53	OP_FRINDEX,
 54	OP_DEVICEADDR,
 55	OP_ENDPTLISTADDR,
 56	OP_TTCTRL,
 57	OP_BURSTSIZE,
 58	OP_ULPI_VIEWPORT,
 59	OP_PORTSC,
 60	OP_DEVLC,
 61	OP_OTGSC,
 62	OP_USBMODE,
 63	OP_ENDPTSETUPSTAT,
 64	OP_ENDPTPRIME,
 65	OP_ENDPTFLUSH,
 66	OP_ENDPTSTAT,
 67	OP_ENDPTCOMPLETE,
 68	OP_ENDPTCTRL,
 69	/* endptctrl1..15 follow */
 70	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
 71};
 72
 73/******************************************************************************
 74 * STRUCTURES
 75 *****************************************************************************/
 76/**
 77 * struct ci_hw_ep - endpoint representation
 78 * @ep: endpoint structure for gadget drivers
 79 * @dir: endpoint direction (TX/RX)
 80 * @num: endpoint number
 81 * @type: endpoint type
 82 * @name: string description of the endpoint
 83 * @qh: queue head for this endpoint
 84 * @wedge: is the endpoint wedged
 85 * @ci: pointer to the controller
 86 * @lock: pointer to controller's spinlock
 87 * @td_pool: pointer to controller's TD pool
 88 */
 89struct ci_hw_ep {
 90	struct usb_ep				ep;
 91	u8					dir;
 92	u8					num;
 93	u8					type;
 94	char					name[16];
 95	struct {
 96		struct list_head	queue;
 97		struct ci_hw_qh		*ptr;
 98		dma_addr_t		dma;
 99	}					qh;
100	int					wedge;
101
102	/* global resources */
103	struct ci_hdrc				*ci;
104	spinlock_t				*lock;
105	struct dma_pool				*td_pool;
106	struct td_node				*pending_td;
107};
108
109enum ci_role {
110	CI_ROLE_HOST = 0,
111	CI_ROLE_GADGET,
112	CI_ROLE_END,
113};
114
115enum ci_revision {
116	CI_REVISION_1X = 10,	/* Revision 1.x */
117	CI_REVISION_20 = 20, /* Revision 2.0 */
118	CI_REVISION_21, /* Revision 2.1 */
119	CI_REVISION_22, /* Revision 2.2 */
120	CI_REVISION_23, /* Revision 2.3 */
121	CI_REVISION_24, /* Revision 2.4 */
122	CI_REVISION_25, /* Revision 2.5 */
123	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
124	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
125};
126
127/**
128 * struct ci_role_driver - host/gadget role driver
129 * @start: start this role
130 * @stop: stop this role
131 * @suspend: system suspend handler for this role
132 * @resume: system resume handler for this role
133 * @irq: irq handler for this role
134 * @name: role name string (host/gadget)
135 */
136struct ci_role_driver {
137	int		(*start)(struct ci_hdrc *);
138	void		(*stop)(struct ci_hdrc *);
139	void		(*suspend)(struct ci_hdrc *ci);
140	void		(*resume)(struct ci_hdrc *ci, bool power_lost);
141	irqreturn_t	(*irq)(struct ci_hdrc *);
142	const char	*name;
143};
144
145/**
146 * struct hw_bank - hardware register mapping representation
147 * @lpm: set if the device is LPM capable
148 * @phys: physical address of the controller's registers
149 * @abs: absolute address of the beginning of register window
150 * @cap: capability registers
151 * @op: operational registers
152 * @size: size of the register window
153 * @regmap: register lookup table
154 */
155struct hw_bank {
156	unsigned	lpm;
157	resource_size_t	phys;
158	void __iomem	*abs;
159	void __iomem	*cap;
160	void __iomem	*op;
161	size_t		size;
162	void __iomem	*regmap[OP_LAST + 1];
163};
164
165/**
166 * struct ci_hdrc - chipidea device representation
167 * @dev: pointer to parent device
168 * @lock: access synchronization
169 * @hw_bank: hardware register mapping
170 * @irq: IRQ number
171 * @roles: array of supported roles for this controller
172 * @role: current role
173 * @is_otg: if the device is otg-capable
174 * @fsm: otg finite state machine
175 * @otg_fsm_hrtimer: hrtimer for otg fsm timers
176 * @hr_timeouts: time out list for active otg fsm timers
177 * @enabled_otg_timer_bits: bits of enabled otg timers
178 * @next_otg_timer: next nearest enabled timer to be expired
179 * @work: work for role changing
180 * @power_lost_work: work for power lost handling
181 * @wq: workqueue thread
182 * @qh_pool: allocation pool for queue heads
183 * @td_pool: allocation pool for transfer descriptors
184 * @gadget: device side representation for peripheral controller
185 * @driver: gadget driver
186 * @resume_state: save the state of gadget suspend from
187 * @hw_ep_max: total number of endpoints supported by hardware
188 * @ci_hw_ep: array of endpoints
189 * @ep0_dir: ep0 direction
190 * @ep0out: pointer to ep0 OUT endpoint
191 * @ep0in: pointer to ep0 IN endpoint
192 * @status: ep0 status request
193 * @setaddr: if we should set the address on status completion
194 * @address: usb address received from the host
195 * @remote_wakeup: host-enabled remote wakeup
196 * @suspended: suspended by host
197 * @test_mode: the selected test mode
198 * @platdata: platform specific information supplied by parent device
199 * @vbus_active: is VBUS active
200 * @ulpi: pointer to ULPI device, if any
201 * @ulpi_ops: ULPI read/write ops for this device
202 * @phy: pointer to PHY, if any
203 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
204 * @hcd: pointer to usb_hcd for ehci host driver
 
205 * @id_event: indicates there is an id event, and handled at ci_otg_work
206 * @b_sess_valid_event: indicates there is a vbus event, and handled
207 * at ci_otg_work
208 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
209 * @supports_runtime_pm: if runtime pm is supported
210 * @in_lpm: if the core in low power mode
211 * @wakeup_int: if wakeup interrupt occur
212 * @rev: The revision number for controller
213 * @mutex: protect code from concorrent running when doing role switch
214 */
215struct ci_hdrc {
216	struct device			*dev;
217	spinlock_t			lock;
218	struct hw_bank			hw_bank;
219	int				irq;
220	struct ci_role_driver		*roles[CI_ROLE_END];
221	enum ci_role			role;
222	bool				is_otg;
223	struct usb_otg			otg;
224	struct otg_fsm			fsm;
225	struct hrtimer			otg_fsm_hrtimer;
226	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
227	unsigned			enabled_otg_timer_bits;
228	enum otg_fsm_timer		next_otg_timer;
229	struct usb_role_switch		*role_switch;
230	struct work_struct		work;
231	struct work_struct		power_lost_work;
232	struct workqueue_struct		*wq;
233
234	struct dma_pool			*qh_pool;
235	struct dma_pool			*td_pool;
236
237	struct usb_gadget		gadget;
238	struct usb_gadget_driver	*driver;
239	enum usb_device_state		resume_state;
240	unsigned			hw_ep_max;
241	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
242	u32				ep0_dir;
243	struct ci_hw_ep			*ep0out, *ep0in;
244
245	struct usb_request		*status;
246	bool				setaddr;
247	u8				address;
248	u8				remote_wakeup;
249	u8				suspended;
250	u8				test_mode;
251
252	struct ci_hdrc_platform_data	*platdata;
253	int				vbus_active;
254	struct ulpi			*ulpi;
255	struct ulpi_ops 		ulpi_ops;
256	struct phy			*phy;
257	/* old usb_phy interface */
258	struct usb_phy			*usb_phy;
259	struct usb_hcd			*hcd;
 
260	bool				id_event;
261	bool				b_sess_valid_event;
262	bool				imx28_write_fix;
263	bool				has_portsc_pec_bug;
264	bool				has_short_pkt_limit;
265	bool				supports_runtime_pm;
266	bool				in_lpm;
267	bool				wakeup_int;
268	enum ci_revision		rev;
269	struct mutex                    mutex;
270};
271
272static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
273{
274	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
275	return ci->roles[ci->role];
276}
277
278static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
279{
280	int ret;
281
282	if (role >= CI_ROLE_END)
283		return -EINVAL;
284
285	if (!ci->roles[role])
286		return -ENXIO;
287
288	ret = ci->roles[role]->start(ci);
289	if (ret)
290		return ret;
291
292	ci->role = role;
293
294	if (ci->usb_phy) {
295		if (role == CI_ROLE_HOST)
296			usb_phy_set_event(ci->usb_phy, USB_EVENT_ID);
297		else
298			/* in device mode but vbus is invalid*/
299			usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);
300	}
301
302	return ret;
303}
304
305static inline void ci_role_stop(struct ci_hdrc *ci)
306{
307	enum ci_role role = ci->role;
308
309	if (role == CI_ROLE_END)
310		return;
311
312	ci->role = CI_ROLE_END;
313
314	ci->roles[role]->stop(ci);
315
316	if (ci->usb_phy)
317		usb_phy_set_event(ci->usb_phy, USB_EVENT_NONE);
318}
319
320static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
321{
322	if (ci->role == CI_ROLE_HOST)
323		return USB_ROLE_HOST;
324	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
325		return USB_ROLE_DEVICE;
326	else
327		return USB_ROLE_NONE;
328}
329
330static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
331{
332	if (role == USB_ROLE_HOST)
333		return CI_ROLE_HOST;
334	else if (role == USB_ROLE_DEVICE)
335		return CI_ROLE_GADGET;
336	else
337		return CI_ROLE_END;
338}
339
340/**
341 * hw_read_id_reg: reads from a identification register
342 * @ci: the controller
343 * @offset: offset from the beginning of identification registers region
344 * @mask: bitfield mask
345 *
346 * This function returns register contents
347 */
348static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
349{
350	return ioread32(ci->hw_bank.abs + offset) & mask;
351}
352
353/**
354 * hw_write_id_reg: writes to a identification register
355 * @ci: the controller
356 * @offset: offset from the beginning of identification registers region
357 * @mask: bitfield mask
358 * @data: new value
359 */
360static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
361			    u32 mask, u32 data)
362{
363	if (~mask)
364		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
365			| (data & mask);
366
367	iowrite32(data, ci->hw_bank.abs + offset);
368}
369
370/**
371 * hw_read: reads from a hw register
372 * @ci: the controller
373 * @reg:  register index
374 * @mask: bitfield mask
375 *
376 * This function returns register contents
377 */
378static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
379{
380	return ioread32(ci->hw_bank.regmap[reg]) & mask;
381}
382
383#ifdef CONFIG_SOC_IMX28
384static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
385{
386	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
387}
388#else
389static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
390{
391}
392#endif
393
394static inline void __hw_write(struct ci_hdrc *ci, u32 val,
395		void __iomem *addr)
396{
397	if (ci->imx28_write_fix)
398		imx28_ci_writel(val, addr);
399	else
400		iowrite32(val, addr);
401}
402
403/**
404 * hw_write: writes to a hw register
405 * @ci: the controller
406 * @reg:  register index
407 * @mask: bitfield mask
408 * @data: new value
409 */
410static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
411			    u32 mask, u32 data)
412{
413	if (~mask)
414		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
415			| (data & mask);
416
417	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
418}
419
420/**
421 * hw_test_and_clear: tests & clears a hw register
422 * @ci: the controller
423 * @reg:  register index
424 * @mask: bitfield mask
425 *
426 * This function returns register contents
427 */
428static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
429				    u32 mask)
430{
431	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
432
433	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
434	return val;
435}
436
437/**
438 * hw_test_and_write: tests & writes a hw register
439 * @ci: the controller
440 * @reg:  register index
441 * @mask: bitfield mask
442 * @data: new value
443 *
444 * This function returns register contents
445 */
446static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
447				    u32 mask, u32 data)
448{
449	u32 val = hw_read(ci, reg, ~0);
450
451	hw_write(ci, reg, mask, data);
452	return (val & mask) >> __ffs(mask);
453}
454
455/**
456 * ci_otg_is_fsm_mode: runtime check if otg controller
457 * is in otg fsm mode.
458 *
459 * @ci: chipidea device
460 */
461static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
462{
463#ifdef CONFIG_USB_OTG_FSM
464	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
465
466	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
467		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
468		otg_caps->hnp_support || otg_caps->adp_support);
469#else
470	return false;
471#endif
472}
473
474int ci_ulpi_init(struct ci_hdrc *ci);
475void ci_ulpi_exit(struct ci_hdrc *ci);
476int ci_ulpi_resume(struct ci_hdrc *ci);
477
478u32 hw_read_intr_enable(struct ci_hdrc *ci);
479
480u32 hw_read_intr_status(struct ci_hdrc *ci);
481
482int hw_device_reset(struct ci_hdrc *ci);
483
484int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
485
486u8 hw_port_test_get(struct ci_hdrc *ci);
487
488void hw_phymode_configure(struct ci_hdrc *ci);
489
490void ci_platform_configure(struct ci_hdrc *ci);
491
492void dbg_create_files(struct ci_hdrc *ci);
493
494void dbg_remove_files(struct ci_hdrc *ci);
495#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
v3.15
 
  1/*
  2 * ci.h - common structures, functions, and macros of the ChipIdea driver
  3 *
  4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5 *
  6 * Author: David Lopo
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 */
 12
 13#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
 14#define __DRIVERS_USB_CHIPIDEA_CI_H
 15
 16#include <linux/list.h>
 17#include <linux/irqreturn.h>
 18#include <linux/usb.h>
 19#include <linux/usb/gadget.h>
 
 
 
 
 20
 21/******************************************************************************
 22 * DEFINE
 23 *****************************************************************************/
 24#define TD_PAGE_COUNT      5
 25#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
 26#define ENDPT_MAX          32
 
 
 27
 28/******************************************************************************
 29 * REGISTERS
 30 *****************************************************************************/
 
 
 
 
 
 
 
 
 
 31/* register indices */
 32enum ci_hw_regs {
 33	CAP_CAPLENGTH,
 34	CAP_HCCPARAMS,
 35	CAP_DCCPARAMS,
 36	CAP_TESTMODE,
 37	CAP_LAST = CAP_TESTMODE,
 38	OP_USBCMD,
 39	OP_USBSTS,
 40	OP_USBINTR,
 
 41	OP_DEVICEADDR,
 42	OP_ENDPTLISTADDR,
 
 
 
 43	OP_PORTSC,
 44	OP_DEVLC,
 45	OP_OTGSC,
 46	OP_USBMODE,
 47	OP_ENDPTSETUPSTAT,
 48	OP_ENDPTPRIME,
 49	OP_ENDPTFLUSH,
 50	OP_ENDPTSTAT,
 51	OP_ENDPTCOMPLETE,
 52	OP_ENDPTCTRL,
 53	/* endptctrl1..15 follow */
 54	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
 55};
 56
 57/******************************************************************************
 58 * STRUCTURES
 59 *****************************************************************************/
 60/**
 61 * struct ci_hw_ep - endpoint representation
 62 * @ep: endpoint structure for gadget drivers
 63 * @dir: endpoint direction (TX/RX)
 64 * @num: endpoint number
 65 * @type: endpoint type
 66 * @name: string description of the endpoint
 67 * @qh: queue head for this endpoint
 68 * @wedge: is the endpoint wedged
 69 * @ci: pointer to the controller
 70 * @lock: pointer to controller's spinlock
 71 * @td_pool: pointer to controller's TD pool
 72 */
 73struct ci_hw_ep {
 74	struct usb_ep				ep;
 75	u8					dir;
 76	u8					num;
 77	u8					type;
 78	char					name[16];
 79	struct {
 80		struct list_head	queue;
 81		struct ci_hw_qh		*ptr;
 82		dma_addr_t		dma;
 83	}					qh;
 84	int					wedge;
 85
 86	/* global resources */
 87	struct ci_hdrc				*ci;
 88	spinlock_t				*lock;
 89	struct dma_pool				*td_pool;
 90	struct td_node				*pending_td;
 91};
 92
 93enum ci_role {
 94	CI_ROLE_HOST = 0,
 95	CI_ROLE_GADGET,
 96	CI_ROLE_END,
 97};
 98
 
 
 
 
 
 
 
 
 
 
 
 
 99/**
100 * struct ci_role_driver - host/gadget role driver
101 * start: start this role
102 * stop: stop this role
103 * irq: irq handler for this role
104 * name: role name string (host/gadget)
 
 
105 */
106struct ci_role_driver {
107	int		(*start)(struct ci_hdrc *);
108	void		(*stop)(struct ci_hdrc *);
 
 
109	irqreturn_t	(*irq)(struct ci_hdrc *);
110	const char	*name;
111};
112
113/**
114 * struct hw_bank - hardware register mapping representation
115 * @lpm: set if the device is LPM capable
116 * @phys: physical address of the controller's registers
117 * @abs: absolute address of the beginning of register window
118 * @cap: capability registers
119 * @op: operational registers
120 * @size: size of the register window
121 * @regmap: register lookup table
122 */
123struct hw_bank {
124	unsigned	lpm;
125	resource_size_t	phys;
126	void __iomem	*abs;
127	void __iomem	*cap;
128	void __iomem	*op;
129	size_t		size;
130	void __iomem	*regmap[OP_LAST + 1];
131};
132
133/**
134 * struct ci_hdrc - chipidea device representation
135 * @dev: pointer to parent device
136 * @lock: access synchronization
137 * @hw_bank: hardware register mapping
138 * @irq: IRQ number
139 * @roles: array of supported roles for this controller
140 * @role: current role
141 * @is_otg: if the device is otg-capable
 
 
 
 
 
142 * @work: work for role changing
 
143 * @wq: workqueue thread
144 * @qh_pool: allocation pool for queue heads
145 * @td_pool: allocation pool for transfer descriptors
146 * @gadget: device side representation for peripheral controller
147 * @driver: gadget driver
 
148 * @hw_ep_max: total number of endpoints supported by hardware
149 * @ci_hw_ep: array of endpoints
150 * @ep0_dir: ep0 direction
151 * @ep0out: pointer to ep0 OUT endpoint
152 * @ep0in: pointer to ep0 IN endpoint
153 * @status: ep0 status request
154 * @setaddr: if we should set the address on status completion
155 * @address: usb address received from the host
156 * @remote_wakeup: host-enabled remote wakeup
157 * @suspended: suspended by host
158 * @test_mode: the selected test mode
159 * @platdata: platform specific information supplied by parent device
160 * @vbus_active: is VBUS active
161 * @transceiver: pointer to USB PHY, if any
 
 
 
162 * @hcd: pointer to usb_hcd for ehci host driver
163 * @debugfs: root dentry for this controller in debugfs
164 * @id_event: indicates there is an id event, and handled at ci_otg_work
165 * @b_sess_valid_event: indicates there is a vbus event, and handled
166 * at ci_otg_work
167 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 
 
 
 
 
168 */
169struct ci_hdrc {
170	struct device			*dev;
171	spinlock_t			lock;
172	struct hw_bank			hw_bank;
173	int				irq;
174	struct ci_role_driver		*roles[CI_ROLE_END];
175	enum ci_role			role;
176	bool				is_otg;
 
 
 
 
 
 
 
177	struct work_struct		work;
 
178	struct workqueue_struct		*wq;
179
180	struct dma_pool			*qh_pool;
181	struct dma_pool			*td_pool;
182
183	struct usb_gadget		gadget;
184	struct usb_gadget_driver	*driver;
 
185	unsigned			hw_ep_max;
186	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
187	u32				ep0_dir;
188	struct ci_hw_ep			*ep0out, *ep0in;
189
190	struct usb_request		*status;
191	bool				setaddr;
192	u8				address;
193	u8				remote_wakeup;
194	u8				suspended;
195	u8				test_mode;
196
197	struct ci_hdrc_platform_data	*platdata;
198	int				vbus_active;
199	struct usb_phy			*transceiver;
 
 
 
 
200	struct usb_hcd			*hcd;
201	struct dentry			*debugfs;
202	bool				id_event;
203	bool				b_sess_valid_event;
204	bool				imx28_write_fix;
 
 
 
 
 
 
 
205};
206
207static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
208{
209	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
210	return ci->roles[ci->role];
211}
212
213static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
214{
215	int ret;
216
217	if (role >= CI_ROLE_END)
218		return -EINVAL;
219
220	if (!ci->roles[role])
221		return -ENXIO;
222
223	ret = ci->roles[role]->start(ci);
224	if (!ret)
225		ci->role = role;
 
 
 
 
 
 
 
 
 
 
 
226	return ret;
227}
228
229static inline void ci_role_stop(struct ci_hdrc *ci)
230{
231	enum ci_role role = ci->role;
232
233	if (role == CI_ROLE_END)
234		return;
235
236	ci->role = CI_ROLE_END;
237
238	ci->roles[role]->stop(ci);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
239}
240
241/**
242 * hw_read: reads from a hw register
 
243 * @reg:  register index
244 * @mask: bitfield mask
245 *
246 * This function returns register contents
247 */
248static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
249{
250	return ioread32(ci->hw_bank.regmap[reg]) & mask;
251}
252
253#ifdef CONFIG_SOC_IMX28
254static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
255{
256	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
257}
258#else
259static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
260{
261}
262#endif
263
264static inline void __hw_write(struct ci_hdrc *ci, u32 val,
265		void __iomem *addr)
266{
267	if (ci->imx28_write_fix)
268		imx28_ci_writel(val, addr);
269	else
270		iowrite32(val, addr);
271}
272
273/**
274 * hw_write: writes to a hw register
 
275 * @reg:  register index
276 * @mask: bitfield mask
277 * @data: new value
278 */
279static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
280			    u32 mask, u32 data)
281{
282	if (~mask)
283		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
284			| (data & mask);
285
286	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
287}
288
289/**
290 * hw_test_and_clear: tests & clears a hw register
 
291 * @reg:  register index
292 * @mask: bitfield mask
293 *
294 * This function returns register contents
295 */
296static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
297				    u32 mask)
298{
299	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
300
301	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
302	return val;
303}
304
305/**
306 * hw_test_and_write: tests & writes a hw register
 
307 * @reg:  register index
308 * @mask: bitfield mask
309 * @data: new value
310 *
311 * This function returns register contents
312 */
313static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
314				    u32 mask, u32 data)
315{
316	u32 val = hw_read(ci, reg, ~0);
317
318	hw_write(ci, reg, mask, data);
319	return (val & mask) >> __ffs(mask);
320}
321
322int hw_device_reset(struct ci_hdrc *ci, u32 mode);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
323
324int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
325
326u8 hw_port_test_get(struct ci_hdrc *ci);
327
328int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
329				u32 value, unsigned int timeout_ms);
 
 
 
330
 
331#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */