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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Texas Instruments CPDMA Driver
4 *
5 * Copyright (C) 2010 Texas Instruments
6 *
7 */
8#ifndef __DAVINCI_CPDMA_H__
9#define __DAVINCI_CPDMA_H__
10
11#define CPDMA_MAX_CHANNELS BITS_PER_LONG
12
13#define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
14
15#define CPDMA_RX_VLAN_ENCAP BIT(19)
16
17#define CPDMA_EOI_RX_THRESH 0x0
18#define CPDMA_EOI_RX 0x1
19#define CPDMA_EOI_TX 0x2
20#define CPDMA_EOI_MISC 0x3
21
22struct cpdma_params {
23 struct device *dev;
24 void __iomem *dmaregs;
25 void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
26 void __iomem *rxthresh, *rxfree;
27 int num_chan;
28 bool has_soft_reset;
29 int min_packet_size;
30 dma_addr_t desc_mem_phys;
31 dma_addr_t desc_hw_addr;
32 int desc_mem_size;
33 int desc_align;
34 u32 bus_freq_mhz;
35 u32 descs_pool_size;
36
37 /*
38 * Some instances of embedded cpdma controllers have extra control and
39 * status registers. The following flag enables access to these
40 * "extended" registers.
41 */
42 bool has_ext_regs;
43};
44
45struct cpdma_chan_stats {
46 u32 head_enqueue;
47 u32 tail_enqueue;
48 u32 pad_enqueue;
49 u32 misqueued;
50 u32 desc_alloc_fail;
51 u32 pad_alloc_fail;
52 u32 runt_receive_buff;
53 u32 runt_transmit_buff;
54 u32 empty_dequeue;
55 u32 busy_dequeue;
56 u32 good_dequeue;
57 u32 requeue;
58 u32 teardown_dequeue;
59};
60
61struct cpdma_ctlr;
62struct cpdma_chan;
63
64typedef void (*cpdma_handler_fn)(void *token, int len, int status);
65
66struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
67int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
68int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
69int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
70
71struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
72 cpdma_handler_fn handler, int rx_type);
73int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
74int cpdma_chan_destroy(struct cpdma_chan *chan);
75int cpdma_chan_start(struct cpdma_chan *chan);
76int cpdma_chan_stop(struct cpdma_chan *chan);
77
78int cpdma_chan_get_stats(struct cpdma_chan *chan,
79 struct cpdma_chan_stats *stats);
80int cpdma_chan_submit_mapped(struct cpdma_chan *chan, void *token,
81 dma_addr_t data, int len, int directed);
82int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
83 int len, int directed);
84int cpdma_chan_idle_submit_mapped(struct cpdma_chan *chan, void *token,
85 dma_addr_t data, int len, int directed);
86int cpdma_chan_idle_submit(struct cpdma_chan *chan, void *token, void *data,
87 int len, int directed);
88int cpdma_chan_process(struct cpdma_chan *chan, int quota);
89
90int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
91void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
92int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
93u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
94u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
95bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
96int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
97int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
98u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
99u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
100
101enum cpdma_control {
102 CPDMA_TX_RLIM, /* read-write */
103 CPDMA_CMD_IDLE, /* write-only */
104 CPDMA_COPY_ERROR_FRAMES, /* read-write */
105 CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
106 CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
107 CPDMA_TX_PRIO_FIXED, /* read-write */
108 CPDMA_STAT_IDLE, /* read-only */
109 CPDMA_STAT_TX_ERR_CHAN, /* read-only */
110 CPDMA_STAT_TX_ERR_CODE, /* read-only */
111 CPDMA_STAT_RX_ERR_CHAN, /* read-only */
112 CPDMA_STAT_RX_ERR_CODE, /* read-only */
113 CPDMA_RX_BUFFER_OFFSET, /* read-write */
114};
115
116int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
117int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
118int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr);
119int cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc);
120int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr);
121
122#endif
1/*
2 * Texas Instruments CPDMA Driver
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef __DAVINCI_CPDMA_H__
16#define __DAVINCI_CPDMA_H__
17
18#define CPDMA_MAX_CHANNELS BITS_PER_LONG
19
20#define tx_chan_num(chan) (chan)
21#define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS)
22#define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS)
23#define is_tx_chan(chan) (!is_rx_chan(chan))
24#define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1))
25#define chan_linear(chan) __chan_linear((chan)->chan_num)
26
27#define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
28
29#define CPDMA_EOI_RX_THRESH 0x0
30#define CPDMA_EOI_RX 0x1
31#define CPDMA_EOI_TX 0x2
32#define CPDMA_EOI_MISC 0x3
33
34struct cpdma_params {
35 struct device *dev;
36 void __iomem *dmaregs;
37 void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
38 void __iomem *rxthresh, *rxfree;
39 int num_chan;
40 bool has_soft_reset;
41 int min_packet_size;
42 u32 desc_mem_phys;
43 u32 desc_hw_addr;
44 int desc_mem_size;
45 int desc_align;
46
47 /*
48 * Some instances of embedded cpdma controllers have extra control and
49 * status registers. The following flag enables access to these
50 * "extended" registers.
51 */
52 bool has_ext_regs;
53};
54
55struct cpdma_chan_stats {
56 u32 head_enqueue;
57 u32 tail_enqueue;
58 u32 pad_enqueue;
59 u32 misqueued;
60 u32 desc_alloc_fail;
61 u32 pad_alloc_fail;
62 u32 runt_receive_buff;
63 u32 runt_transmit_buff;
64 u32 empty_dequeue;
65 u32 busy_dequeue;
66 u32 good_dequeue;
67 u32 requeue;
68 u32 teardown_dequeue;
69};
70
71struct cpdma_ctlr;
72struct cpdma_chan;
73
74typedef void (*cpdma_handler_fn)(void *token, int len, int status);
75
76struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
77int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
78int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
79int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
80int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr);
81
82struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
83 cpdma_handler_fn handler);
84int cpdma_chan_destroy(struct cpdma_chan *chan);
85int cpdma_chan_start(struct cpdma_chan *chan);
86int cpdma_chan_stop(struct cpdma_chan *chan);
87int cpdma_chan_dump(struct cpdma_chan *chan);
88
89int cpdma_chan_get_stats(struct cpdma_chan *chan,
90 struct cpdma_chan_stats *stats);
91int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
92 int len, int directed);
93int cpdma_chan_process(struct cpdma_chan *chan, int quota);
94
95int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
96void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
97int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
98bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
99
100enum cpdma_control {
101 CPDMA_CMD_IDLE, /* write-only */
102 CPDMA_COPY_ERROR_FRAMES, /* read-write */
103 CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
104 CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
105 CPDMA_TX_PRIO_FIXED, /* read-write */
106 CPDMA_STAT_IDLE, /* read-only */
107 CPDMA_STAT_TX_ERR_CHAN, /* read-only */
108 CPDMA_STAT_TX_ERR_CODE, /* read-only */
109 CPDMA_STAT_RX_ERR_CHAN, /* read-only */
110 CPDMA_STAT_RX_ERR_CODE, /* read-only */
111 CPDMA_RX_BUFFER_OFFSET, /* read-write */
112};
113
114int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
115int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
116
117#endif