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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#ifndef _IXGBE_H_
5#define _IXGBE_H_
6
7#include <linux/bitops.h>
8#include <linux/types.h>
9#include <linux/pci.h>
10#include <linux/netdevice.h>
11#include <linux/cpumask.h>
12#include <linux/if_vlan.h>
13#include <linux/jiffies.h>
14#include <linux/phy.h>
15
16#include <linux/timecounter.h>
17#include <linux/net_tstamp.h>
18#include <linux/ptp_clock_kernel.h>
19
20#include "ixgbe_type.h"
21#include "ixgbe_common.h"
22#include "ixgbe_dcb.h"
23#if IS_ENABLED(CONFIG_FCOE)
24#define IXGBE_FCOE
25#include "ixgbe_fcoe.h"
26#endif /* IS_ENABLED(CONFIG_FCOE) */
27#ifdef CONFIG_IXGBE_DCA
28#include <linux/dca.h>
29#endif
30#include "ixgbe_ipsec.h"
31
32#include <net/xdp.h>
33
34/* common prefix used by pr_<> macros */
35#undef pr_fmt
36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38/* TX/RX descriptor defines */
39#define IXGBE_DEFAULT_TXD 512
40#define IXGBE_DEFAULT_TX_WORK 256
41#define IXGBE_MAX_TXD_82598 4096
42#define IXGBE_MAX_TXD_82599 8192
43#define IXGBE_MAX_TXD_X540 8192
44#define IXGBE_MAX_TXD_X550 32768
45#define IXGBE_MIN_TXD 64
46
47#if (PAGE_SIZE < 8192)
48#define IXGBE_DEFAULT_RXD 512
49#else
50#define IXGBE_DEFAULT_RXD 128
51#endif
52#define IXGBE_MAX_RXD_82598 4096
53#define IXGBE_MAX_RXD_82599 8192
54#define IXGBE_MAX_RXD_X540 8192
55#define IXGBE_MAX_RXD_X550 32768
56#define IXGBE_MIN_RXD 64
57
58/* flow control */
59#define IXGBE_MIN_FCRTL 0x40
60#define IXGBE_MAX_FCRTL 0x7FF80
61#define IXGBE_MIN_FCRTH 0x600
62#define IXGBE_MAX_FCRTH 0x7FFF0
63#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
64#define IXGBE_MIN_FCPAUSE 0
65#define IXGBE_MAX_FCPAUSE 0xFFFF
66
67/* Supported Rx Buffer Sizes */
68#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
69#define IXGBE_RXBUFFER_1536 1536
70#define IXGBE_RXBUFFER_2K 2048
71#define IXGBE_RXBUFFER_3K 3072
72#define IXGBE_RXBUFFER_4K 4096
73#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
74
75#define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
76
77/* Attempt to maximize the headroom available for incoming frames. We
78 * use a 2K buffer for receives and need 1536/1534 to store the data for
79 * the frame. This leaves us with 512 bytes of room. From that we need
80 * to deduct the space needed for the shared info and the padding needed
81 * to IP align the frame.
82 *
83 * Note: For cache line sizes 256 or larger this value is going to end
84 * up negative. In these cases we should fall back to the 3K
85 * buffers.
86 */
87#if (PAGE_SIZE < 8192)
88#define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN)
89#define IXGBE_2K_TOO_SMALL_WITH_PADDING \
90((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K))
91
92static inline int ixgbe_compute_pad(int rx_buf_len)
93{
94 int page_size, pad_size;
95
96 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
97 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
98
99 return pad_size;
100}
101
102static inline int ixgbe_skb_pad(void)
103{
104 int rx_buf_len;
105
106 /* If a 2K buffer cannot handle a standard Ethernet frame then
107 * optimize padding for a 3K buffer instead of a 1.5K buffer.
108 *
109 * For a 3K buffer we need to add enough padding to allow for
110 * tailroom due to NET_IP_ALIGN possibly shifting us out of
111 * cache-line alignment.
112 */
113 if (IXGBE_2K_TOO_SMALL_WITH_PADDING)
114 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN);
115 else
116 rx_buf_len = IXGBE_RXBUFFER_1536;
117
118 /* if needed make room for NET_IP_ALIGN */
119 rx_buf_len -= NET_IP_ALIGN;
120
121 return ixgbe_compute_pad(rx_buf_len);
122}
123
124#define IXGBE_SKB_PAD ixgbe_skb_pad()
125#else
126#define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
127#endif
128
129/*
130 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
131 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
132 * this adds up to 448 bytes of extra data.
133 *
134 * Since netdev_alloc_skb now allocates a page fragment we can use a value
135 * of 256 and the resultant skb will have a truesize of 960 or less.
136 */
137#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
138
139/* How many Rx Buffers do we bundle into one write to the hardware ? */
140#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
141
142#define IXGBE_RX_DMA_ATTR \
143 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
144
145enum ixgbe_tx_flags {
146 /* cmd_type flags */
147 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
148 IXGBE_TX_FLAGS_TSO = 0x02,
149 IXGBE_TX_FLAGS_TSTAMP = 0x04,
150
151 /* olinfo flags */
152 IXGBE_TX_FLAGS_CC = 0x08,
153 IXGBE_TX_FLAGS_IPV4 = 0x10,
154 IXGBE_TX_FLAGS_CSUM = 0x20,
155 IXGBE_TX_FLAGS_IPSEC = 0x40,
156
157 /* software defined flags */
158 IXGBE_TX_FLAGS_SW_VLAN = 0x80,
159 IXGBE_TX_FLAGS_FCOE = 0x100,
160};
161
162/* VLAN info */
163#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
164#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
165#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
166#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
167
168#define IXGBE_MAX_VF_MC_ENTRIES 30
169#define IXGBE_MAX_VF_FUNCTIONS 64
170#define IXGBE_MAX_VFTA_ENTRIES 128
171#define MAX_EMULATION_MAC_ADDRS 16
172#define IXGBE_MAX_PF_MACVLANS 15
173#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
174#define IXGBE_82599_VF_DEVICE_ID 0x10ED
175#define IXGBE_X540_VF_DEVICE_ID 0x1515
176
177#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
178 { \
179 u32 current_counter = IXGBE_READ_REG(hw, reg); \
180 if (current_counter < last_counter) \
181 counter += 0x100000000LL; \
182 last_counter = current_counter; \
183 counter &= 0xFFFFFFFF00000000LL; \
184 counter |= current_counter; \
185 }
186
187#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
188 { \
189 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
190 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
191 u64 current_counter = (current_counter_msb << 32) | \
192 current_counter_lsb; \
193 if (current_counter < last_counter) \
194 counter += 0x1000000000LL; \
195 last_counter = current_counter; \
196 counter &= 0xFFFFFFF000000000LL; \
197 counter |= current_counter; \
198 }
199
200struct vf_stats {
201 u64 gprc;
202 u64 gorc;
203 u64 gptc;
204 u64 gotc;
205 u64 mprc;
206};
207
208struct vf_data_storage {
209 struct pci_dev *vfdev;
210 unsigned char vf_mac_addresses[ETH_ALEN];
211 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
212 u16 num_vf_mc_hashes;
213 bool clear_to_send;
214 struct vf_stats vfstats;
215 struct vf_stats last_vfstats;
216 struct vf_stats saved_rst_vfstats;
217 bool pf_set_mac;
218 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
219 u16 pf_qos;
220 u16 tx_rate;
221 int link_enable;
222 int link_state;
223 u8 spoofchk_enabled;
224 bool rss_query_enabled;
225 u8 trusted;
226 int xcast_mode;
227 unsigned int vf_api;
228 u8 primary_abort_count;
229};
230
231enum ixgbevf_xcast_modes {
232 IXGBEVF_XCAST_MODE_NONE = 0,
233 IXGBEVF_XCAST_MODE_MULTI,
234 IXGBEVF_XCAST_MODE_ALLMULTI,
235 IXGBEVF_XCAST_MODE_PROMISC,
236};
237
238struct vf_macvlans {
239 struct list_head l;
240 int vf;
241 bool free;
242 bool is_macvlan;
243 u8 vf_macvlan[ETH_ALEN];
244};
245
246#define IXGBE_MAX_TXD_PWR 14
247#define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
248
249/* Tx Descriptors needed, worst case */
250#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
251#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
252
253/* wrapper around a pointer to a socket buffer,
254 * so a DMA handle can be stored along with the buffer */
255struct ixgbe_tx_buffer {
256 union ixgbe_adv_tx_desc *next_to_watch;
257 unsigned long time_stamp;
258 union {
259 struct sk_buff *skb;
260 struct xdp_frame *xdpf;
261 };
262 unsigned int bytecount;
263 unsigned short gso_segs;
264 __be16 protocol;
265 DEFINE_DMA_UNMAP_ADDR(dma);
266 DEFINE_DMA_UNMAP_LEN(len);
267 u32 tx_flags;
268};
269
270struct ixgbe_rx_buffer {
271 union {
272 struct {
273 struct sk_buff *skb;
274 dma_addr_t dma;
275 struct page *page;
276 __u32 page_offset;
277 __u16 pagecnt_bias;
278 };
279 struct {
280 bool discard;
281 struct xdp_buff *xdp;
282 };
283 };
284};
285
286struct ixgbe_queue_stats {
287 u64 packets;
288 u64 bytes;
289};
290
291struct ixgbe_tx_queue_stats {
292 u64 restart_queue;
293 u64 tx_busy;
294 u64 tx_done_old;
295};
296
297struct ixgbe_rx_queue_stats {
298 u64 rsc_count;
299 u64 rsc_flush;
300 u64 non_eop_descs;
301 u64 alloc_rx_page;
302 u64 alloc_rx_page_failed;
303 u64 alloc_rx_buff_failed;
304 u64 csum_err;
305};
306
307#define IXGBE_TS_HDR_LEN 8
308
309enum ixgbe_ring_state_t {
310 __IXGBE_RX_3K_BUFFER,
311 __IXGBE_RX_BUILD_SKB_ENABLED,
312 __IXGBE_RX_RSC_ENABLED,
313 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
314 __IXGBE_RX_FCOE,
315 __IXGBE_TX_FDIR_INIT_DONE,
316 __IXGBE_TX_XPS_INIT_DONE,
317 __IXGBE_TX_DETECT_HANG,
318 __IXGBE_HANG_CHECK_ARMED,
319 __IXGBE_TX_XDP_RING,
320 __IXGBE_TX_DISABLED,
321};
322
323#define ring_uses_build_skb(ring) \
324 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state)
325
326struct ixgbe_fwd_adapter {
327 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
328 struct net_device *netdev;
329 unsigned int tx_base_queue;
330 unsigned int rx_base_queue;
331 int pool;
332};
333
334#define check_for_tx_hang(ring) \
335 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
336#define set_check_for_tx_hang(ring) \
337 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
338#define clear_check_for_tx_hang(ring) \
339 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
340#define ring_is_rsc_enabled(ring) \
341 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
342#define set_ring_rsc_enabled(ring) \
343 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
344#define clear_ring_rsc_enabled(ring) \
345 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
346#define ring_is_xdp(ring) \
347 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
348#define set_ring_xdp(ring) \
349 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
350#define clear_ring_xdp(ring) \
351 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
352struct ixgbe_ring {
353 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
354 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
355 struct net_device *netdev; /* netdev ring belongs to */
356 struct bpf_prog *xdp_prog;
357 struct device *dev; /* device for DMA mapping */
358 void *desc; /* descriptor ring memory */
359 union {
360 struct ixgbe_tx_buffer *tx_buffer_info;
361 struct ixgbe_rx_buffer *rx_buffer_info;
362 };
363 unsigned long state;
364 u8 __iomem *tail;
365 dma_addr_t dma; /* phys. address of descriptor ring */
366 unsigned int size; /* length in bytes */
367
368 u16 count; /* amount of descriptors */
369
370 u8 queue_index; /* needed for multiqueue queue management */
371 u8 reg_idx; /* holds the special value that gets
372 * the hardware register offset
373 * associated with this ring, which is
374 * different for DCB and RSS modes
375 */
376 u16 next_to_use;
377 u16 next_to_clean;
378
379 unsigned long last_rx_timestamp;
380
381 union {
382 u16 next_to_alloc;
383 struct {
384 u8 atr_sample_rate;
385 u8 atr_count;
386 };
387 };
388
389 u8 dcb_tc;
390 struct ixgbe_queue_stats stats;
391 struct u64_stats_sync syncp;
392 union {
393 struct ixgbe_tx_queue_stats tx_stats;
394 struct ixgbe_rx_queue_stats rx_stats;
395 };
396 u16 rx_offset;
397 struct xdp_rxq_info xdp_rxq;
398 spinlock_t tx_lock; /* used in XDP mode */
399 struct xsk_buff_pool *xsk_pool;
400 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */
401 u16 rx_buf_len;
402} ____cacheline_internodealigned_in_smp;
403
404enum ixgbe_ring_f_enum {
405 RING_F_NONE = 0,
406 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
407 RING_F_RSS,
408 RING_F_FDIR,
409#ifdef IXGBE_FCOE
410 RING_F_FCOE,
411#endif /* IXGBE_FCOE */
412
413 RING_F_ARRAY_SIZE /* must be last in enum set */
414};
415
416#define IXGBE_MAX_RSS_INDICES 16
417#define IXGBE_MAX_RSS_INDICES_X550 63
418#define IXGBE_MAX_VMDQ_INDICES 64
419#define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
420#define IXGBE_MAX_FCOE_INDICES 8
421#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
422#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
423#define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1)
424#define IXGBE_MAX_L2A_QUEUES 4
425#define IXGBE_BAD_L2A_QUEUE 3
426#define IXGBE_MAX_MACVLANS 63
427
428DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key);
429
430struct ixgbe_ring_feature {
431 u16 limit; /* upper limit on feature indices */
432 u16 indices; /* current value of indices */
433 u16 mask; /* Mask used for feature to ring mapping */
434 u16 offset; /* offset to start of feature */
435} ____cacheline_internodealigned_in_smp;
436
437#define IXGBE_82599_VMDQ_8Q_MASK 0x78
438#define IXGBE_82599_VMDQ_4Q_MASK 0x7C
439#define IXGBE_82599_VMDQ_2Q_MASK 0x7E
440
441/*
442 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
443 * this is twice the size of a half page we need to double the page order
444 * for FCoE enabled Rx queues.
445 */
446static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
447{
448 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
449 return IXGBE_RXBUFFER_3K;
450#if (PAGE_SIZE < 8192)
451 if (ring_uses_build_skb(ring))
452 return IXGBE_MAX_2K_FRAME_BUILD_SKB;
453#endif
454 return IXGBE_RXBUFFER_2K;
455}
456
457static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
458{
459#if (PAGE_SIZE < 8192)
460 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
461 return 1;
462#endif
463 return 0;
464}
465#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
466
467#define IXGBE_ITR_ADAPTIVE_MIN_INC 2
468#define IXGBE_ITR_ADAPTIVE_MIN_USECS 10
469#define IXGBE_ITR_ADAPTIVE_MAX_USECS 126
470#define IXGBE_ITR_ADAPTIVE_LATENCY 0x80
471#define IXGBE_ITR_ADAPTIVE_BULK 0x00
472
473struct ixgbe_ring_container {
474 struct ixgbe_ring *ring; /* pointer to linked list of rings */
475 unsigned long next_update; /* jiffies value of last update */
476 unsigned int total_bytes; /* total bytes processed this int */
477 unsigned int total_packets; /* total packets processed this int */
478 u16 work_limit; /* total work allowed per interrupt */
479 u8 count; /* total number of rings in vector */
480 u8 itr; /* current ITR setting for ring */
481};
482
483/* iterator for handling rings in ring container */
484#define ixgbe_for_each_ring(pos, head) \
485 for (pos = (head).ring; pos != NULL; pos = pos->next)
486
487#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
488 ? 8 : 1)
489#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
490
491/* MAX_Q_VECTORS of these are allocated,
492 * but we only use one per queue-specific vector.
493 */
494struct ixgbe_q_vector {
495 struct ixgbe_adapter *adapter;
496#ifdef CONFIG_IXGBE_DCA
497 int cpu; /* CPU for DCA */
498#endif
499 u16 v_idx; /* index of q_vector within array, also used for
500 * finding the bit in EICR and friends that
501 * represents the vector for this ring */
502 u16 itr; /* Interrupt throttle rate written to EITR */
503 struct ixgbe_ring_container rx, tx;
504
505 struct napi_struct napi;
506 cpumask_t affinity_mask;
507 int numa_node;
508 struct rcu_head rcu; /* to avoid race with update stats on free */
509 char name[IFNAMSIZ + 9];
510
511 /* for dynamic allocation of rings associated with this q_vector */
512 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp;
513};
514
515#ifdef CONFIG_IXGBE_HWMON
516
517#define IXGBE_HWMON_TYPE_LOC 0
518#define IXGBE_HWMON_TYPE_TEMP 1
519#define IXGBE_HWMON_TYPE_CAUTION 2
520#define IXGBE_HWMON_TYPE_MAX 3
521
522struct hwmon_attr {
523 struct device_attribute dev_attr;
524 struct ixgbe_hw *hw;
525 struct ixgbe_thermal_diode_data *sensor;
526 char name[12];
527};
528
529struct hwmon_buff {
530 struct attribute_group group;
531 const struct attribute_group *groups[2];
532 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
533 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
534 unsigned int n_hwmon;
535};
536#endif /* CONFIG_IXGBE_HWMON */
537
538/*
539 * microsecond values for various ITR rates shifted by 2 to fit itr register
540 * with the first 3 bits reserved 0
541 */
542#define IXGBE_MIN_RSC_ITR 24
543#define IXGBE_100K_ITR 40
544#define IXGBE_20K_ITR 200
545#define IXGBE_12K_ITR 336
546
547/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
548static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
549 const u32 stat_err_bits)
550{
551 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
552}
553
554static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
555{
556 u16 ntc = ring->next_to_clean;
557 u16 ntu = ring->next_to_use;
558
559 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
560}
561
562#define IXGBE_RX_DESC(R, i) \
563 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
564#define IXGBE_TX_DESC(R, i) \
565 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
566#define IXGBE_TX_CTXTDESC(R, i) \
567 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
568
569#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
570#ifdef IXGBE_FCOE
571/* Use 3K as the baby jumbo frame size for FCoE */
572#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
573#endif /* IXGBE_FCOE */
574
575#define OTHER_VECTOR 1
576#define NON_Q_VECTORS (OTHER_VECTOR)
577
578#define MAX_MSIX_VECTORS_82599 64
579#define MAX_Q_VECTORS_82599 64
580#define MAX_MSIX_VECTORS_82598 18
581#define MAX_Q_VECTORS_82598 16
582
583struct ixgbe_mac_addr {
584 u8 addr[ETH_ALEN];
585 u16 pool;
586 u16 state; /* bitmask */
587};
588
589#define IXGBE_MAC_STATE_DEFAULT 0x1
590#define IXGBE_MAC_STATE_MODIFIED 0x2
591#define IXGBE_MAC_STATE_IN_USE 0x4
592
593#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
594#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
595
596#define MIN_MSIX_Q_VECTORS 1
597#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
598
599/* default to trying for four seconds */
600#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
601#define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
602
603#define IXGBE_PRIMARY_ABORT_LIMIT 5
604
605/* board specific private data structure */
606struct ixgbe_adapter {
607 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
608 /* OS defined structs */
609 struct net_device *netdev;
610 struct bpf_prog *xdp_prog;
611 struct pci_dev *pdev;
612 struct mii_bus *mii_bus;
613
614 unsigned long state;
615
616 /* Some features need tri-state capability,
617 * thus the additional *_CAPABLE flags.
618 */
619 u32 flags;
620#define IXGBE_FLAG_MSI_ENABLED BIT(1)
621#define IXGBE_FLAG_MSIX_ENABLED BIT(3)
622#define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
623#define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
624#define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
625#define IXGBE_FLAG_DCA_ENABLED BIT(8)
626#define IXGBE_FLAG_DCA_CAPABLE BIT(9)
627#define IXGBE_FLAG_IMIR_ENABLED BIT(10)
628#define IXGBE_FLAG_MQ_CAPABLE BIT(11)
629#define IXGBE_FLAG_DCB_ENABLED BIT(12)
630#define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
631#define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
632#define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
633#define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
634#define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
635#define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
636#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
637#define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
638#define IXGBE_FLAG_FCOE_ENABLED BIT(21)
639#define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
640#define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
641#define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
642#define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
643#define IXGBE_FLAG_DCB_CAPABLE BIT(27)
644
645 u32 flags2;
646#define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
647#define IXGBE_FLAG2_RSC_ENABLED BIT(1)
648#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
649#define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
650#define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
651#define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
652#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
653#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
654#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
655#define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
656#define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
657#define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
658#define IXGBE_FLAG2_EEE_CAPABLE BIT(14)
659#define IXGBE_FLAG2_EEE_ENABLED BIT(15)
660#define IXGBE_FLAG2_RX_LEGACY BIT(16)
661#define IXGBE_FLAG2_IPSEC_ENABLED BIT(17)
662#define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18)
663#define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19)
664
665 /* Tx fast path data */
666 int num_tx_queues;
667 u16 tx_itr_setting;
668 u16 tx_work_limit;
669 u64 tx_ipsec;
670
671 /* Rx fast path data */
672 int num_rx_queues;
673 u16 rx_itr_setting;
674 u64 rx_ipsec;
675
676 /* Port number used to identify VXLAN traffic */
677 __be16 vxlan_port;
678 __be16 geneve_port;
679
680 /* XDP */
681 int num_xdp_queues;
682 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS];
683 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */
684
685 /* TX */
686 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
687
688 u64 restart_queue;
689 u64 lsc_int;
690 u32 tx_timeout_count;
691
692 /* RX */
693 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
694 int num_rx_pools; /* == num_rx_queues in 82598 */
695 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
696 u64 hw_csum_rx_error;
697 u64 hw_rx_no_dma_resources;
698 u64 rsc_total_count;
699 u64 rsc_total_flush;
700 u64 non_eop_descs;
701 u32 alloc_rx_page;
702 u32 alloc_rx_page_failed;
703 u32 alloc_rx_buff_failed;
704
705 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
706
707 /* DCB parameters */
708 struct ieee_pfc *ixgbe_ieee_pfc;
709 struct ieee_ets *ixgbe_ieee_ets;
710 struct ixgbe_dcb_config dcb_cfg;
711 struct ixgbe_dcb_config temp_dcb_cfg;
712 u8 hw_tcs;
713 u8 dcb_set_bitmap;
714 u8 dcbx_cap;
715 enum ixgbe_fc_mode last_lfc_mode;
716
717 int num_q_vectors; /* current number of q_vectors for device */
718 int max_q_vectors; /* true count of q_vectors for device */
719 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
720 struct msix_entry *msix_entries;
721
722 u32 test_icr;
723 struct ixgbe_ring test_tx_ring;
724 struct ixgbe_ring test_rx_ring;
725
726 /* structs defined in ixgbe_hw.h */
727 struct ixgbe_hw hw;
728 u16 msg_enable;
729 struct ixgbe_hw_stats stats;
730
731 u64 tx_busy;
732 unsigned int tx_ring_count;
733 unsigned int xdp_ring_count;
734 unsigned int rx_ring_count;
735
736 u32 link_speed;
737 bool link_up;
738 unsigned long sfp_poll_time;
739 unsigned long link_check_timeout;
740
741 struct timer_list service_timer;
742 struct work_struct service_task;
743
744 struct hlist_head fdir_filter_list;
745 unsigned long fdir_overflow; /* number of times ATR was backed off */
746 union ixgbe_atr_input fdir_mask;
747 int fdir_filter_count;
748 u32 fdir_pballoc;
749 u32 atr_sample_rate;
750 spinlock_t fdir_perfect_lock;
751
752#ifdef IXGBE_FCOE
753 struct ixgbe_fcoe fcoe;
754#endif /* IXGBE_FCOE */
755 u8 __iomem *io_addr; /* Mainly for iounmap use */
756 u32 wol;
757
758 u16 bridge_mode;
759
760 char eeprom_id[NVM_VER_SIZE];
761 u16 eeprom_cap;
762
763 u32 interrupt_event;
764 u32 led_reg;
765
766 struct ptp_clock *ptp_clock;
767 struct ptp_clock_info ptp_caps;
768 struct work_struct ptp_tx_work;
769 struct sk_buff *ptp_tx_skb;
770 struct hwtstamp_config tstamp_config;
771 unsigned long ptp_tx_start;
772 unsigned long last_overflow_check;
773 unsigned long last_rx_ptp_check;
774 unsigned long last_rx_timestamp;
775 spinlock_t tmreg_lock;
776 struct cyclecounter hw_cc;
777 struct timecounter hw_tc;
778 u32 base_incval;
779 u32 tx_hwtstamp_timeouts;
780 u32 tx_hwtstamp_skipped;
781 u32 rx_hwtstamp_cleared;
782 void (*ptp_setup_sdp)(struct ixgbe_adapter *);
783
784 /* SR-IOV */
785 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
786 unsigned int num_vfs;
787 struct vf_data_storage *vfinfo;
788 int vf_rate_link_speed;
789 struct vf_macvlans vf_mvs;
790 struct vf_macvlans *mv_list;
791
792 u32 timer_event_accumulator;
793 u32 vferr_refcount;
794 struct ixgbe_mac_addr *mac_table;
795 struct kobject *info_kobj;
796#ifdef CONFIG_IXGBE_HWMON
797 struct hwmon_buff *ixgbe_hwmon_buff;
798#endif /* CONFIG_IXGBE_HWMON */
799#ifdef CONFIG_DEBUG_FS
800 struct dentry *ixgbe_dbg_adapter;
801#endif /*CONFIG_DEBUG_FS*/
802
803 u8 default_up;
804 /* Bitmask indicating in use pools */
805 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1);
806
807#define IXGBE_MAX_LINK_HANDLE 10
808 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
809 unsigned long tables;
810
811/* maximum number of RETA entries among all devices supported by ixgbe
812 * driver: currently it's x550 device in non-SRIOV mode
813 */
814#define IXGBE_MAX_RETA_ENTRIES 512
815 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
816
817#define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
818 u32 *rss_key;
819
820#ifdef CONFIG_IXGBE_IPSEC
821 struct ixgbe_ipsec *ipsec;
822#endif /* CONFIG_IXGBE_IPSEC */
823 spinlock_t vfs_lock;
824};
825
826static inline int ixgbe_determine_xdp_q_idx(int cpu)
827{
828 if (static_key_enabled(&ixgbe_xdp_locking_key))
829 return cpu % IXGBE_MAX_XDP_QS;
830 else
831 return cpu;
832}
833
834static inline
835struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter)
836{
837 int index = ixgbe_determine_xdp_q_idx(smp_processor_id());
838
839 return adapter->xdp_ring[index];
840}
841
842static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
843{
844 switch (adapter->hw.mac.type) {
845 case ixgbe_mac_82598EB:
846 case ixgbe_mac_82599EB:
847 case ixgbe_mac_X540:
848 return IXGBE_MAX_RSS_INDICES;
849 case ixgbe_mac_X550:
850 case ixgbe_mac_X550EM_x:
851 case ixgbe_mac_x550em_a:
852 return IXGBE_MAX_RSS_INDICES_X550;
853 default:
854 return 0;
855 }
856}
857
858struct ixgbe_fdir_filter {
859 struct hlist_node fdir_node;
860 union ixgbe_atr_input filter;
861 u16 sw_idx;
862 u64 action;
863};
864
865enum ixgbe_state_t {
866 __IXGBE_TESTING,
867 __IXGBE_RESETTING,
868 __IXGBE_DOWN,
869 __IXGBE_DISABLED,
870 __IXGBE_REMOVING,
871 __IXGBE_SERVICE_SCHED,
872 __IXGBE_SERVICE_INITED,
873 __IXGBE_IN_SFP_INIT,
874 __IXGBE_PTP_RUNNING,
875 __IXGBE_PTP_TX_IN_PROGRESS,
876 __IXGBE_RESET_REQUESTED,
877};
878
879struct ixgbe_cb {
880 union { /* Union defining head/tail partner */
881 struct sk_buff *head;
882 struct sk_buff *tail;
883 };
884 dma_addr_t dma;
885 u16 append_cnt;
886 bool page_released;
887};
888#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
889
890enum ixgbe_boards {
891 board_82598,
892 board_82599,
893 board_X540,
894 board_X550,
895 board_X550EM_x,
896 board_x550em_x_fw,
897 board_x550em_a,
898 board_x550em_a_fw,
899};
900
901extern const struct ixgbe_info ixgbe_82598_info;
902extern const struct ixgbe_info ixgbe_82599_info;
903extern const struct ixgbe_info ixgbe_X540_info;
904extern const struct ixgbe_info ixgbe_X550_info;
905extern const struct ixgbe_info ixgbe_X550EM_x_info;
906extern const struct ixgbe_info ixgbe_x550em_x_fw_info;
907extern const struct ixgbe_info ixgbe_x550em_a_info;
908extern const struct ixgbe_info ixgbe_x550em_a_fw_info;
909#ifdef CONFIG_IXGBE_DCB
910extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops;
911#endif
912
913extern char ixgbe_driver_name[];
914#ifdef IXGBE_FCOE
915extern char ixgbe_default_device_descr[];
916#endif /* IXGBE_FCOE */
917
918int ixgbe_open(struct net_device *netdev);
919int ixgbe_close(struct net_device *netdev);
920void ixgbe_up(struct ixgbe_adapter *adapter);
921void ixgbe_down(struct ixgbe_adapter *adapter);
922void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
923void ixgbe_reset(struct ixgbe_adapter *adapter);
924void ixgbe_set_ethtool_ops(struct net_device *netdev);
925int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
926int ixgbe_setup_tx_resources(struct ixgbe_ring *);
927void ixgbe_free_rx_resources(struct ixgbe_ring *);
928void ixgbe_free_tx_resources(struct ixgbe_ring *);
929void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
930void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
931void ixgbe_disable_rx(struct ixgbe_adapter *adapter);
932void ixgbe_disable_tx(struct ixgbe_adapter *adapter);
933void ixgbe_update_stats(struct ixgbe_adapter *adapter);
934int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
935bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
936 u16 subdevice_id);
937#ifdef CONFIG_PCI_IOV
938void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
939#endif
940int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
941 const u8 *addr, u16 queue);
942int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
943 const u8 *addr, u16 queue);
944void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
945void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
946netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
947 struct ixgbe_ring *);
948void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
949void ixgbe_write_eitr(struct ixgbe_q_vector *);
950int ixgbe_poll(struct napi_struct *napi, int budget);
951int ethtool_ioctl(struct ifreq *ifr);
952int ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
953int ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
954int ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
955int ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
956 union ixgbe_atr_hash_dword input,
957 union ixgbe_atr_hash_dword common,
958 u8 queue);
959int ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
960 union ixgbe_atr_input *input_mask);
961int ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
962 union ixgbe_atr_input *input,
963 u16 soft_id, u8 queue);
964int ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
965 union ixgbe_atr_input *input,
966 u16 soft_id);
967void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
968 union ixgbe_atr_input *mask);
969int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
970 struct ixgbe_fdir_filter *input,
971 u16 sw_idx);
972void ixgbe_set_rx_mode(struct net_device *netdev);
973#ifdef CONFIG_IXGBE_DCB
974void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
975#endif
976int ixgbe_setup_tc(struct net_device *dev, u8 tc);
977void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
978void ixgbe_do_reset(struct net_device *netdev);
979#ifdef CONFIG_IXGBE_HWMON
980void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
981int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
982#endif /* CONFIG_IXGBE_HWMON */
983#ifdef IXGBE_FCOE
984void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
985int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
986 u8 *hdr_len);
987int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
988 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
989int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
990 struct scatterlist *sgl, unsigned int sgc);
991int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
992 struct scatterlist *sgl, unsigned int sgc);
993int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
994int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
995void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
996int ixgbe_fcoe_enable(struct net_device *netdev);
997int ixgbe_fcoe_disable(struct net_device *netdev);
998int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
999int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
1000 struct netdev_fcoe_hbainfo *info);
1001u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
1002#endif /* IXGBE_FCOE */
1003#ifdef CONFIG_DEBUG_FS
1004void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
1005void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
1006void ixgbe_dbg_init(void);
1007void ixgbe_dbg_exit(void);
1008#else
1009static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
1010static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
1011static inline void ixgbe_dbg_init(void) {}
1012static inline void ixgbe_dbg_exit(void) {}
1013#endif /* CONFIG_DEBUG_FS */
1014static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
1015{
1016 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
1017}
1018
1019void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
1020void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
1021void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
1022void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
1023void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
1024void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter);
1025void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
1026void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
1027static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
1028 union ixgbe_adv_rx_desc *rx_desc,
1029 struct sk_buff *skb)
1030{
1031 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
1032 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
1033 return;
1034 }
1035
1036 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1037 return;
1038
1039 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
1040
1041 /* Update the last_rx_timestamp timer in order to enable watchdog check
1042 * for error case of latched timestamp on a dropped packet.
1043 */
1044 rx_ring->last_rx_timestamp = jiffies;
1045}
1046
1047int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1048int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
1049void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
1050void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
1051void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
1052#ifdef CONFIG_PCI_IOV
1053void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
1054#endif
1055
1056netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
1057 struct ixgbe_adapter *adapter,
1058 struct ixgbe_ring *tx_ring);
1059u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
1060void ixgbe_store_key(struct ixgbe_adapter *adapter);
1061void ixgbe_store_reta(struct ixgbe_adapter *adapter);
1062int ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1063 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
1064#ifdef CONFIG_IXGBE_IPSEC
1065void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
1066void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter);
1067void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter);
1068void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1069 union ixgbe_adv_rx_desc *rx_desc,
1070 struct sk_buff *skb);
1071int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
1072 struct ixgbe_ipsec_tx_data *itd);
1073void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf);
1074int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1075int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1076#else
1077static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { }
1078static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { }
1079static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { }
1080static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1081 union ixgbe_adv_rx_desc *rx_desc,
1082 struct sk_buff *skb) { }
1083static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring,
1084 struct ixgbe_tx_buffer *first,
1085 struct ixgbe_ipsec_tx_data *itd) { return 0; }
1086static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter,
1087 u32 vf) { }
1088static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter,
1089 u32 *mbuf, u32 vf) { return -EACCES; }
1090static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter,
1091 u32 *mbuf, u32 vf) { return -EACCES; }
1092#endif /* CONFIG_IXGBE_IPSEC */
1093
1094static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter)
1095{
1096 return !!adapter->xdp_prog;
1097}
1098
1099#endif /* _IXGBE_H_ */
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_H_
30#define _IXGBE_H_
31
32#include <linux/bitops.h>
33#include <linux/types.h>
34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/cpumask.h>
37#include <linux/aer.h>
38#include <linux/if_vlan.h>
39#include <linux/jiffies.h>
40
41#include <linux/clocksource.h>
42#include <linux/net_tstamp.h>
43#include <linux/ptp_clock_kernel.h>
44
45#include "ixgbe_type.h"
46#include "ixgbe_common.h"
47#include "ixgbe_dcb.h"
48#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
49#define IXGBE_FCOE
50#include "ixgbe_fcoe.h"
51#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52#ifdef CONFIG_IXGBE_DCA
53#include <linux/dca.h>
54#endif
55
56#include <net/busy_poll.h>
57
58#ifdef CONFIG_NET_RX_BUSY_POLL
59#define BP_EXTENDED_STATS
60#endif
61/* common prefix used by pr_<> macros */
62#undef pr_fmt
63#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
64
65/* TX/RX descriptor defines */
66#define IXGBE_DEFAULT_TXD 512
67#define IXGBE_DEFAULT_TX_WORK 256
68#define IXGBE_MAX_TXD 4096
69#define IXGBE_MIN_TXD 64
70
71#if (PAGE_SIZE < 8192)
72#define IXGBE_DEFAULT_RXD 512
73#else
74#define IXGBE_DEFAULT_RXD 128
75#endif
76#define IXGBE_MAX_RXD 4096
77#define IXGBE_MIN_RXD 64
78
79/* flow control */
80#define IXGBE_MIN_FCRTL 0x40
81#define IXGBE_MAX_FCRTL 0x7FF80
82#define IXGBE_MIN_FCRTH 0x600
83#define IXGBE_MAX_FCRTH 0x7FFF0
84#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
85#define IXGBE_MIN_FCPAUSE 0
86#define IXGBE_MAX_FCPAUSE 0xFFFF
87
88/* Supported Rx Buffer Sizes */
89#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
90#define IXGBE_RXBUFFER_2K 2048
91#define IXGBE_RXBUFFER_3K 3072
92#define IXGBE_RXBUFFER_4K 4096
93#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
94
95/*
96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
98 * this adds up to 448 bytes of extra data.
99 *
100 * Since netdev_alloc_skb now allocates a page fragment we can use a value
101 * of 256 and the resultant skb will have a truesize of 960 or less.
102 */
103#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
104
105/* How many Rx Buffers do we bundle into one write to the hardware ? */
106#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
107
108enum ixgbe_tx_flags {
109 /* cmd_type flags */
110 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
111 IXGBE_TX_FLAGS_TSO = 0x02,
112 IXGBE_TX_FLAGS_TSTAMP = 0x04,
113
114 /* olinfo flags */
115 IXGBE_TX_FLAGS_CC = 0x08,
116 IXGBE_TX_FLAGS_IPV4 = 0x10,
117 IXGBE_TX_FLAGS_CSUM = 0x20,
118
119 /* software defined flags */
120 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
121 IXGBE_TX_FLAGS_FCOE = 0x80,
122};
123
124/* VLAN info */
125#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
126#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
127#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
128#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
129
130#define IXGBE_MAX_VF_MC_ENTRIES 30
131#define IXGBE_MAX_VF_FUNCTIONS 64
132#define IXGBE_MAX_VFTA_ENTRIES 128
133#define MAX_EMULATION_MAC_ADDRS 16
134#define IXGBE_MAX_PF_MACVLANS 15
135#define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
136#define IXGBE_82599_VF_DEVICE_ID 0x10ED
137#define IXGBE_X540_VF_DEVICE_ID 0x1515
138
139struct vf_data_storage {
140 unsigned char vf_mac_addresses[ETH_ALEN];
141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
142 u16 num_vf_mc_hashes;
143 u16 default_vf_vlan_id;
144 u16 vlans_enabled;
145 bool clear_to_send;
146 bool pf_set_mac;
147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
148 u16 pf_qos;
149 u16 tx_rate;
150 u16 vlan_count;
151 u8 spoofchk_enabled;
152 unsigned int vf_api;
153};
154
155struct vf_macvlans {
156 struct list_head l;
157 int vf;
158 int rar_entry;
159 bool free;
160 bool is_macvlan;
161 u8 vf_macvlan[ETH_ALEN];
162};
163
164#define IXGBE_MAX_TXD_PWR 14
165#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
166
167/* Tx Descriptors needed, worst case */
168#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
169#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
170
171/* wrapper around a pointer to a socket buffer,
172 * so a DMA handle can be stored along with the buffer */
173struct ixgbe_tx_buffer {
174 union ixgbe_adv_tx_desc *next_to_watch;
175 unsigned long time_stamp;
176 struct sk_buff *skb;
177 unsigned int bytecount;
178 unsigned short gso_segs;
179 __be16 protocol;
180 DEFINE_DMA_UNMAP_ADDR(dma);
181 DEFINE_DMA_UNMAP_LEN(len);
182 u32 tx_flags;
183};
184
185struct ixgbe_rx_buffer {
186 struct sk_buff *skb;
187 dma_addr_t dma;
188 struct page *page;
189 unsigned int page_offset;
190};
191
192struct ixgbe_queue_stats {
193 u64 packets;
194 u64 bytes;
195#ifdef BP_EXTENDED_STATS
196 u64 yields;
197 u64 misses;
198 u64 cleaned;
199#endif /* BP_EXTENDED_STATS */
200};
201
202struct ixgbe_tx_queue_stats {
203 u64 restart_queue;
204 u64 tx_busy;
205 u64 tx_done_old;
206};
207
208struct ixgbe_rx_queue_stats {
209 u64 rsc_count;
210 u64 rsc_flush;
211 u64 non_eop_descs;
212 u64 alloc_rx_page_failed;
213 u64 alloc_rx_buff_failed;
214 u64 csum_err;
215};
216
217enum ixgbe_ring_state_t {
218 __IXGBE_TX_FDIR_INIT_DONE,
219 __IXGBE_TX_XPS_INIT_DONE,
220 __IXGBE_TX_DETECT_HANG,
221 __IXGBE_HANG_CHECK_ARMED,
222 __IXGBE_RX_RSC_ENABLED,
223 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
224 __IXGBE_RX_FCOE,
225};
226
227struct ixgbe_fwd_adapter {
228 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
229 struct net_device *netdev;
230 struct ixgbe_adapter *real_adapter;
231 unsigned int tx_base_queue;
232 unsigned int rx_base_queue;
233 int pool;
234};
235
236#define check_for_tx_hang(ring) \
237 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
238#define set_check_for_tx_hang(ring) \
239 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
240#define clear_check_for_tx_hang(ring) \
241 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
242#define ring_is_rsc_enabled(ring) \
243 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
244#define set_ring_rsc_enabled(ring) \
245 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
246#define clear_ring_rsc_enabled(ring) \
247 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
248struct ixgbe_ring {
249 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
250 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
251 struct net_device *netdev; /* netdev ring belongs to */
252 struct device *dev; /* device for DMA mapping */
253 struct ixgbe_fwd_adapter *l2_accel_priv;
254 void *desc; /* descriptor ring memory */
255 union {
256 struct ixgbe_tx_buffer *tx_buffer_info;
257 struct ixgbe_rx_buffer *rx_buffer_info;
258 };
259 unsigned long state;
260 u8 __iomem *tail;
261 dma_addr_t dma; /* phys. address of descriptor ring */
262 unsigned int size; /* length in bytes */
263
264 u16 count; /* amount of descriptors */
265
266 u8 queue_index; /* needed for multiqueue queue management */
267 u8 reg_idx; /* holds the special value that gets
268 * the hardware register offset
269 * associated with this ring, which is
270 * different for DCB and RSS modes
271 */
272 u16 next_to_use;
273 u16 next_to_clean;
274
275 union {
276 u16 next_to_alloc;
277 struct {
278 u8 atr_sample_rate;
279 u8 atr_count;
280 };
281 };
282
283 u8 dcb_tc;
284 struct ixgbe_queue_stats stats;
285 struct u64_stats_sync syncp;
286 union {
287 struct ixgbe_tx_queue_stats tx_stats;
288 struct ixgbe_rx_queue_stats rx_stats;
289 };
290} ____cacheline_internodealigned_in_smp;
291
292enum ixgbe_ring_f_enum {
293 RING_F_NONE = 0,
294 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
295 RING_F_RSS,
296 RING_F_FDIR,
297#ifdef IXGBE_FCOE
298 RING_F_FCOE,
299#endif /* IXGBE_FCOE */
300
301 RING_F_ARRAY_SIZE /* must be last in enum set */
302};
303
304#define IXGBE_MAX_RSS_INDICES 16
305#define IXGBE_MAX_VMDQ_INDICES 64
306#define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
307#define IXGBE_MAX_FCOE_INDICES 8
308#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
309#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
310#define IXGBE_MAX_L2A_QUEUES 4
311#define IXGBE_MAX_L2A_QUEUES 4
312#define IXGBE_BAD_L2A_QUEUE 3
313#define IXGBE_MAX_MACVLANS 31
314#define IXGBE_MAX_DCBMACVLANS 8
315
316struct ixgbe_ring_feature {
317 u16 limit; /* upper limit on feature indices */
318 u16 indices; /* current value of indices */
319 u16 mask; /* Mask used for feature to ring mapping */
320 u16 offset; /* offset to start of feature */
321} ____cacheline_internodealigned_in_smp;
322
323#define IXGBE_82599_VMDQ_8Q_MASK 0x78
324#define IXGBE_82599_VMDQ_4Q_MASK 0x7C
325#define IXGBE_82599_VMDQ_2Q_MASK 0x7E
326
327/*
328 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
329 * this is twice the size of a half page we need to double the page order
330 * for FCoE enabled Rx queues.
331 */
332static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
333{
334#ifdef IXGBE_FCOE
335 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
336 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
337 IXGBE_RXBUFFER_3K;
338#endif
339 return IXGBE_RXBUFFER_2K;
340}
341
342static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
343{
344#ifdef IXGBE_FCOE
345 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
346 return (PAGE_SIZE < 8192) ? 1 : 0;
347#endif
348 return 0;
349}
350#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
351
352struct ixgbe_ring_container {
353 struct ixgbe_ring *ring; /* pointer to linked list of rings */
354 unsigned int total_bytes; /* total bytes processed this int */
355 unsigned int total_packets; /* total packets processed this int */
356 u16 work_limit; /* total work allowed per interrupt */
357 u8 count; /* total number of rings in vector */
358 u8 itr; /* current ITR setting for ring */
359};
360
361/* iterator for handling rings in ring container */
362#define ixgbe_for_each_ring(pos, head) \
363 for (pos = (head).ring; pos != NULL; pos = pos->next)
364
365#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
366 ? 8 : 1)
367#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
368
369/* MAX_Q_VECTORS of these are allocated,
370 * but we only use one per queue-specific vector.
371 */
372struct ixgbe_q_vector {
373 struct ixgbe_adapter *adapter;
374#ifdef CONFIG_IXGBE_DCA
375 int cpu; /* CPU for DCA */
376#endif
377 u16 v_idx; /* index of q_vector within array, also used for
378 * finding the bit in EICR and friends that
379 * represents the vector for this ring */
380 u16 itr; /* Interrupt throttle rate written to EITR */
381 struct ixgbe_ring_container rx, tx;
382
383 struct napi_struct napi;
384 cpumask_t affinity_mask;
385 int numa_node;
386 struct rcu_head rcu; /* to avoid race with update stats on free */
387 char name[IFNAMSIZ + 9];
388
389#ifdef CONFIG_NET_RX_BUSY_POLL
390 unsigned int state;
391#define IXGBE_QV_STATE_IDLE 0
392#define IXGBE_QV_STATE_NAPI 1 /* NAPI owns this QV */
393#define IXGBE_QV_STATE_POLL 2 /* poll owns this QV */
394#define IXGBE_QV_STATE_DISABLED 4 /* QV is disabled */
395#define IXGBE_QV_OWNED (IXGBE_QV_STATE_NAPI | IXGBE_QV_STATE_POLL)
396#define IXGBE_QV_LOCKED (IXGBE_QV_OWNED | IXGBE_QV_STATE_DISABLED)
397#define IXGBE_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
398#define IXGBE_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
399#define IXGBE_QV_YIELD (IXGBE_QV_STATE_NAPI_YIELD | IXGBE_QV_STATE_POLL_YIELD)
400#define IXGBE_QV_USER_PEND (IXGBE_QV_STATE_POLL | IXGBE_QV_STATE_POLL_YIELD)
401 spinlock_t lock;
402#endif /* CONFIG_NET_RX_BUSY_POLL */
403
404 /* for dynamic allocation of rings associated with this q_vector */
405 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
406};
407#ifdef CONFIG_NET_RX_BUSY_POLL
408static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
409{
410
411 spin_lock_init(&q_vector->lock);
412 q_vector->state = IXGBE_QV_STATE_IDLE;
413}
414
415/* called from the device poll routine to get ownership of a q_vector */
416static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
417{
418 int rc = true;
419 spin_lock_bh(&q_vector->lock);
420 if (q_vector->state & IXGBE_QV_LOCKED) {
421 WARN_ON(q_vector->state & IXGBE_QV_STATE_NAPI);
422 q_vector->state |= IXGBE_QV_STATE_NAPI_YIELD;
423 rc = false;
424#ifdef BP_EXTENDED_STATS
425 q_vector->tx.ring->stats.yields++;
426#endif
427 } else {
428 /* we don't care if someone yielded */
429 q_vector->state = IXGBE_QV_STATE_NAPI;
430 }
431 spin_unlock_bh(&q_vector->lock);
432 return rc;
433}
434
435/* returns true is someone tried to get the qv while napi had it */
436static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
437{
438 int rc = false;
439 spin_lock_bh(&q_vector->lock);
440 WARN_ON(q_vector->state & (IXGBE_QV_STATE_POLL |
441 IXGBE_QV_STATE_NAPI_YIELD));
442
443 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD)
444 rc = true;
445 /* will reset state to idle, unless QV is disabled */
446 q_vector->state &= IXGBE_QV_STATE_DISABLED;
447 spin_unlock_bh(&q_vector->lock);
448 return rc;
449}
450
451/* called from ixgbe_low_latency_poll() */
452static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
453{
454 int rc = true;
455 spin_lock_bh(&q_vector->lock);
456 if ((q_vector->state & IXGBE_QV_LOCKED)) {
457 q_vector->state |= IXGBE_QV_STATE_POLL_YIELD;
458 rc = false;
459#ifdef BP_EXTENDED_STATS
460 q_vector->rx.ring->stats.yields++;
461#endif
462 } else {
463 /* preserve yield marks */
464 q_vector->state |= IXGBE_QV_STATE_POLL;
465 }
466 spin_unlock_bh(&q_vector->lock);
467 return rc;
468}
469
470/* returns true if someone tried to get the qv while it was locked */
471static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
472{
473 int rc = false;
474 spin_lock_bh(&q_vector->lock);
475 WARN_ON(q_vector->state & (IXGBE_QV_STATE_NAPI));
476
477 if (q_vector->state & IXGBE_QV_STATE_POLL_YIELD)
478 rc = true;
479 /* will reset state to idle, unless QV is disabled */
480 q_vector->state &= IXGBE_QV_STATE_DISABLED;
481 spin_unlock_bh(&q_vector->lock);
482 return rc;
483}
484
485/* true if a socket is polling, even if it did not get the lock */
486static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
487{
488 WARN_ON(!(q_vector->state & IXGBE_QV_OWNED));
489 return q_vector->state & IXGBE_QV_USER_PEND;
490}
491
492/* false if QV is currently owned */
493static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
494{
495 int rc = true;
496 spin_lock_bh(&q_vector->lock);
497 if (q_vector->state & IXGBE_QV_OWNED)
498 rc = false;
499 q_vector->state |= IXGBE_QV_STATE_DISABLED;
500 spin_unlock_bh(&q_vector->lock);
501
502 return rc;
503}
504
505#else /* CONFIG_NET_RX_BUSY_POLL */
506static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
507{
508}
509
510static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
511{
512 return true;
513}
514
515static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
516{
517 return false;
518}
519
520static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
521{
522 return false;
523}
524
525static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
526{
527 return false;
528}
529
530static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
531{
532 return false;
533}
534
535static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
536{
537 return true;
538}
539
540#endif /* CONFIG_NET_RX_BUSY_POLL */
541
542#ifdef CONFIG_IXGBE_HWMON
543
544#define IXGBE_HWMON_TYPE_LOC 0
545#define IXGBE_HWMON_TYPE_TEMP 1
546#define IXGBE_HWMON_TYPE_CAUTION 2
547#define IXGBE_HWMON_TYPE_MAX 3
548
549struct hwmon_attr {
550 struct device_attribute dev_attr;
551 struct ixgbe_hw *hw;
552 struct ixgbe_thermal_diode_data *sensor;
553 char name[12];
554};
555
556struct hwmon_buff {
557 struct attribute_group group;
558 const struct attribute_group *groups[2];
559 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
560 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
561 unsigned int n_hwmon;
562};
563#endif /* CONFIG_IXGBE_HWMON */
564
565/*
566 * microsecond values for various ITR rates shifted by 2 to fit itr register
567 * with the first 3 bits reserved 0
568 */
569#define IXGBE_MIN_RSC_ITR 24
570#define IXGBE_100K_ITR 40
571#define IXGBE_20K_ITR 200
572#define IXGBE_10K_ITR 400
573#define IXGBE_8K_ITR 500
574
575/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
576static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
577 const u32 stat_err_bits)
578{
579 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
580}
581
582static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
583{
584 u16 ntc = ring->next_to_clean;
585 u16 ntu = ring->next_to_use;
586
587 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
588}
589
590static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value)
591{
592 writel(value, ring->tail);
593}
594
595#define IXGBE_RX_DESC(R, i) \
596 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
597#define IXGBE_TX_DESC(R, i) \
598 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
599#define IXGBE_TX_CTXTDESC(R, i) \
600 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
601
602#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
603#ifdef IXGBE_FCOE
604/* Use 3K as the baby jumbo frame size for FCoE */
605#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
606#endif /* IXGBE_FCOE */
607
608#define OTHER_VECTOR 1
609#define NON_Q_VECTORS (OTHER_VECTOR)
610
611#define MAX_MSIX_VECTORS_82599 64
612#define MAX_Q_VECTORS_82599 64
613#define MAX_MSIX_VECTORS_82598 18
614#define MAX_Q_VECTORS_82598 16
615
616#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
617#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
618
619#define MIN_MSIX_Q_VECTORS 1
620#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
621
622/* default to trying for four seconds */
623#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
624
625/* board specific private data structure */
626struct ixgbe_adapter {
627 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
628 /* OS defined structs */
629 struct net_device *netdev;
630 struct pci_dev *pdev;
631
632 unsigned long state;
633
634 /* Some features need tri-state capability,
635 * thus the additional *_CAPABLE flags.
636 */
637 u32 flags;
638#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
639#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
640#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
641#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
642#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
643#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
644#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
645#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
646#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
647#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
648#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
649#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
650#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
651#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
652#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
653#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
654#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
655#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
656#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
657#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
658#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
659#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
660#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
661#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
662
663 u32 flags2;
664#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
665#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
666#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
667#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
668#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
669#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
670#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
671#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
672#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
673#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
674#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
675#define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11)
676
677 /* Tx fast path data */
678 int num_tx_queues;
679 u16 tx_itr_setting;
680 u16 tx_work_limit;
681
682 /* Rx fast path data */
683 int num_rx_queues;
684 u16 rx_itr_setting;
685
686 /* TX */
687 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
688
689 u64 restart_queue;
690 u64 lsc_int;
691 u32 tx_timeout_count;
692
693 /* RX */
694 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
695 int num_rx_pools; /* == num_rx_queues in 82598 */
696 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
697 u64 hw_csum_rx_error;
698 u64 hw_rx_no_dma_resources;
699 u64 rsc_total_count;
700 u64 rsc_total_flush;
701 u64 non_eop_descs;
702 u32 alloc_rx_page_failed;
703 u32 alloc_rx_buff_failed;
704
705 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
706
707 /* DCB parameters */
708 struct ieee_pfc *ixgbe_ieee_pfc;
709 struct ieee_ets *ixgbe_ieee_ets;
710 struct ixgbe_dcb_config dcb_cfg;
711 struct ixgbe_dcb_config temp_dcb_cfg;
712 u8 dcb_set_bitmap;
713 u8 dcbx_cap;
714 enum ixgbe_fc_mode last_lfc_mode;
715
716 int num_q_vectors; /* current number of q_vectors for device */
717 int max_q_vectors; /* true count of q_vectors for device */
718 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
719 struct msix_entry *msix_entries;
720
721 u32 test_icr;
722 struct ixgbe_ring test_tx_ring;
723 struct ixgbe_ring test_rx_ring;
724
725 /* structs defined in ixgbe_hw.h */
726 struct ixgbe_hw hw;
727 u16 msg_enable;
728 struct ixgbe_hw_stats stats;
729
730 u64 tx_busy;
731 unsigned int tx_ring_count;
732 unsigned int rx_ring_count;
733
734 u32 link_speed;
735 bool link_up;
736 unsigned long link_check_timeout;
737
738 struct timer_list service_timer;
739 struct work_struct service_task;
740
741 struct hlist_head fdir_filter_list;
742 unsigned long fdir_overflow; /* number of times ATR was backed off */
743 union ixgbe_atr_input fdir_mask;
744 int fdir_filter_count;
745 u32 fdir_pballoc;
746 u32 atr_sample_rate;
747 spinlock_t fdir_perfect_lock;
748
749#ifdef IXGBE_FCOE
750 struct ixgbe_fcoe fcoe;
751#endif /* IXGBE_FCOE */
752 u8 __iomem *io_addr; /* Mainly for iounmap use */
753 u32 wol;
754
755 u16 bd_number;
756
757 u16 eeprom_verh;
758 u16 eeprom_verl;
759 u16 eeprom_cap;
760
761 u32 interrupt_event;
762 u32 led_reg;
763
764 struct ptp_clock *ptp_clock;
765 struct ptp_clock_info ptp_caps;
766 struct work_struct ptp_tx_work;
767 struct sk_buff *ptp_tx_skb;
768 struct hwtstamp_config tstamp_config;
769 unsigned long ptp_tx_start;
770 unsigned long last_overflow_check;
771 unsigned long last_rx_ptp_check;
772 unsigned long last_rx_timestamp;
773 spinlock_t tmreg_lock;
774 struct cyclecounter cc;
775 struct timecounter tc;
776 u32 base_incval;
777
778 /* SR-IOV */
779 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
780 unsigned int num_vfs;
781 struct vf_data_storage *vfinfo;
782 int vf_rate_link_speed;
783 struct vf_macvlans vf_mvs;
784 struct vf_macvlans *mv_list;
785
786 u32 timer_event_accumulator;
787 u32 vferr_refcount;
788 struct kobject *info_kobj;
789#ifdef CONFIG_IXGBE_HWMON
790 struct hwmon_buff *ixgbe_hwmon_buff;
791#endif /* CONFIG_IXGBE_HWMON */
792#ifdef CONFIG_DEBUG_FS
793 struct dentry *ixgbe_dbg_adapter;
794#endif /*CONFIG_DEBUG_FS*/
795
796 u8 default_up;
797 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
798};
799
800struct ixgbe_fdir_filter {
801 struct hlist_node fdir_node;
802 union ixgbe_atr_input filter;
803 u16 sw_idx;
804 u16 action;
805};
806
807enum ixgbe_state_t {
808 __IXGBE_TESTING,
809 __IXGBE_RESETTING,
810 __IXGBE_DOWN,
811 __IXGBE_DISABLED,
812 __IXGBE_REMOVING,
813 __IXGBE_SERVICE_SCHED,
814 __IXGBE_SERVICE_INITED,
815 __IXGBE_IN_SFP_INIT,
816 __IXGBE_PTP_RUNNING,
817 __IXGBE_PTP_TX_IN_PROGRESS,
818};
819
820struct ixgbe_cb {
821 union { /* Union defining head/tail partner */
822 struct sk_buff *head;
823 struct sk_buff *tail;
824 };
825 dma_addr_t dma;
826 u16 append_cnt;
827 bool page_released;
828};
829#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
830
831enum ixgbe_boards {
832 board_82598,
833 board_82599,
834 board_X540,
835};
836
837extern struct ixgbe_info ixgbe_82598_info;
838extern struct ixgbe_info ixgbe_82599_info;
839extern struct ixgbe_info ixgbe_X540_info;
840#ifdef CONFIG_IXGBE_DCB
841extern const struct dcbnl_rtnl_ops dcbnl_ops;
842#endif
843
844extern char ixgbe_driver_name[];
845extern const char ixgbe_driver_version[];
846#ifdef IXGBE_FCOE
847extern char ixgbe_default_device_descr[];
848#endif /* IXGBE_FCOE */
849
850void ixgbe_up(struct ixgbe_adapter *adapter);
851void ixgbe_down(struct ixgbe_adapter *adapter);
852void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
853void ixgbe_reset(struct ixgbe_adapter *adapter);
854void ixgbe_set_ethtool_ops(struct net_device *netdev);
855int ixgbe_setup_rx_resources(struct ixgbe_ring *);
856int ixgbe_setup_tx_resources(struct ixgbe_ring *);
857void ixgbe_free_rx_resources(struct ixgbe_ring *);
858void ixgbe_free_tx_resources(struct ixgbe_ring *);
859void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
860void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
861void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
862void ixgbe_update_stats(struct ixgbe_adapter *adapter);
863int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
864int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
865 u16 subdevice_id);
866void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
867netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
868 struct ixgbe_ring *);
869void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
870 struct ixgbe_tx_buffer *);
871void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
872void ixgbe_write_eitr(struct ixgbe_q_vector *);
873int ixgbe_poll(struct napi_struct *napi, int budget);
874int ethtool_ioctl(struct ifreq *ifr);
875s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
876s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
877s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
878s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
879 union ixgbe_atr_hash_dword input,
880 union ixgbe_atr_hash_dword common,
881 u8 queue);
882s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
883 union ixgbe_atr_input *input_mask);
884s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
885 union ixgbe_atr_input *input,
886 u16 soft_id, u8 queue);
887s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
888 union ixgbe_atr_input *input,
889 u16 soft_id);
890void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
891 union ixgbe_atr_input *mask);
892void ixgbe_set_rx_mode(struct net_device *netdev);
893#ifdef CONFIG_IXGBE_DCB
894void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
895#endif
896int ixgbe_setup_tc(struct net_device *dev, u8 tc);
897void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
898void ixgbe_do_reset(struct net_device *netdev);
899#ifdef CONFIG_IXGBE_HWMON
900void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
901int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
902#endif /* CONFIG_IXGBE_HWMON */
903#ifdef IXGBE_FCOE
904void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
905int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
906 u8 *hdr_len);
907int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
908 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
909int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
910 struct scatterlist *sgl, unsigned int sgc);
911int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
912 struct scatterlist *sgl, unsigned int sgc);
913int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
914int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
915void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
916int ixgbe_fcoe_enable(struct net_device *netdev);
917int ixgbe_fcoe_disable(struct net_device *netdev);
918#ifdef CONFIG_IXGBE_DCB
919u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
920u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
921#endif /* CONFIG_IXGBE_DCB */
922int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
923int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
924 struct netdev_fcoe_hbainfo *info);
925u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
926#endif /* IXGBE_FCOE */
927#ifdef CONFIG_DEBUG_FS
928void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
929void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
930void ixgbe_dbg_init(void);
931void ixgbe_dbg_exit(void);
932#else
933static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
934static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
935static inline void ixgbe_dbg_init(void) {}
936static inline void ixgbe_dbg_exit(void) {}
937#endif /* CONFIG_DEBUG_FS */
938static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
939{
940 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
941}
942
943void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
944void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
945void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
946void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
947void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb);
948int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
949int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
950void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
951void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
952void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
953#ifdef CONFIG_PCI_IOV
954void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
955#endif
956
957netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
958 struct ixgbe_adapter *adapter,
959 struct ixgbe_ring *tx_ring);
960#endif /* _IXGBE_H_ */