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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
6 *
7 * This code was implemented by Mocean Laboratories AB when porting linux
8 * to the automotive development board Russellville. The copyright holder
9 * as seen in the header is Intel corporation.
10 * Mocean Laboratories forked off the GNU/Linux platform work into a
11 * separate company called Pelagicore AB, which committed the code to the
12 * kernel.
13 */
14
15/* Supports:
16 * Xilinx IIC
17 */
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/i2c.h>
25#include <linux/interrupt.h>
26#include <linux/completion.h>
27#include <linux/platform_data/i2c-xiic.h>
28#include <linux/io.h>
29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/clk.h>
32#include <linux/pm_runtime.h>
33
34#define DRIVER_NAME "xiic-i2c"
35#define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
36#define SMBUS_BLOCK_READ_MIN_LEN 3
37
38enum xilinx_i2c_state {
39 STATE_DONE,
40 STATE_ERROR,
41 STATE_START
42};
43
44enum xiic_endian {
45 LITTLE,
46 BIG
47};
48
49enum i2c_scl_freq {
50 REG_VALUES_100KHZ = 0,
51 REG_VALUES_400KHZ = 1,
52 REG_VALUES_1MHZ = 2
53};
54
55/**
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
57 * @dev: Pointer to device structure
58 * @base: Memory base of the HW registers
59 * @completion: Completion for callers
60 * @adap: Kernel adapter representation
61 * @tx_msg: Messages from above to be sent
62 * @lock: Mutual exclusion
63 * @tx_pos: Current pos in TX message
64 * @nmsgs: Number of messages in tx_msg
65 * @rx_msg: Current RX message
66 * @rx_pos: Position within current RX message
67 * @endianness: big/little-endian byte order
68 * @clk: Pointer to AXI4-lite input clock
69 * @state: See STATE_
70 * @singlemaster: Indicates bus is single master
71 * @dynamic: Mode of controller
72 * @prev_msg_tx: Previous message is Tx
73 * @quirks: To hold platform specific bug info
74 * @smbus_block_read: Flag to handle block read
75 * @input_clk: Input clock to I2C controller
76 * @i2c_clk: I2C SCL frequency
77 */
78struct xiic_i2c {
79 struct device *dev;
80 void __iomem *base;
81 struct completion completion;
82 struct i2c_adapter adap;
83 struct i2c_msg *tx_msg;
84 struct mutex lock;
85 unsigned int tx_pos;
86 unsigned int nmsgs;
87 struct i2c_msg *rx_msg;
88 int rx_pos;
89 enum xiic_endian endianness;
90 struct clk *clk;
91 enum xilinx_i2c_state state;
92 bool singlemaster;
93 bool dynamic;
94 bool prev_msg_tx;
95 u32 quirks;
96 bool smbus_block_read;
97 unsigned long input_clk;
98 unsigned int i2c_clk;
99};
100
101struct xiic_version_data {
102 u32 quirks;
103};
104
105/**
106 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
107 * @tsusta: setup time for a repeated START condition
108 * @tsusto: setup time for a STOP condition
109 * @thdsta: hold time for a repeated START condition
110 * @tsudat: setup time for data
111 * @tbuf: bus free time between STOP and START
112 */
113struct timing_regs {
114 unsigned int tsusta;
115 unsigned int tsusto;
116 unsigned int thdsta;
117 unsigned int tsudat;
118 unsigned int tbuf;
119};
120
121/* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
122static const struct timing_regs timing_reg_values[] = {
123 { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */
124 { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */
125 { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */
126};
127
128#define XIIC_MSB_OFFSET 0
129#define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
130
131/*
132 * Register offsets in bytes from RegisterBase. Three is added to the
133 * base offset to access LSB (IBM style) of the word
134 */
135#define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */
136#define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */
137#define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */
138#define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */
139#define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */
140#define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
141#define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
142#define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */
143#define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
144#define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */
145
146/*
147 * Timing register offsets from RegisterBase. These are used only for
148 * setting i2c clock frequency for the line.
149 */
150#define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */
151#define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */
152#define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */
153#define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */
154#define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */
155#define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */
156#define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */
157#define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */
158
159/* Control Register masks */
160#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
161#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
162#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
163#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
164#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
165#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
166#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
167
168/* Status Register masks */
169#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
170#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
171#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
172#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
173#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
174#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
175#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
176#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
177
178/* Interrupt Status Register masks Interrupt occurs when... */
179#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
180#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
181#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
182#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
183#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
184#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
185#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
186#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
187
188/* The following constants specify the depth of the FIFOs */
189#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
190#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
191
192/* The following constants specify groups of interrupts that are typically
193 * enabled or disables at the same time
194 */
195#define XIIC_TX_INTERRUPTS \
196(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
197
198#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
199
200/*
201 * Tx Fifo upper bit masks.
202 */
203#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
204#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
205
206/* Dynamic mode constants */
207#define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */
208
209/*
210 * The following constants define the register offsets for the Interrupt
211 * registers. There are some holes in the memory map for reserved addresses
212 * to allow other registers to be added and still match the memory map of the
213 * interrupt controller registers
214 */
215#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
216#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
217#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
218#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
219
220#define XIIC_RESET_MASK 0xAUL
221
222#define XIIC_PM_TIMEOUT 1000 /* ms */
223/* timeout waiting for the controller to respond */
224#define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
225/* timeout waiting for the controller finish transfers */
226#define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000))
227
228/*
229 * The following constant is used for the device global interrupt enable
230 * register, to enable all interrupts for the device, this is the only bit
231 * in the register
232 */
233#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
234
235#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
236#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
237
238static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
239static void __xiic_start_xfer(struct xiic_i2c *i2c);
240
241/*
242 * For the register read and write functions, a little-endian and big-endian
243 * version are necessary. Endianness is detected during the probe function.
244 * Only the least significant byte [doublet] of the register are ever
245 * accessed. This requires an offset of 3 [2] from the base address for
246 * big-endian systems.
247 */
248
249static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
250{
251 if (i2c->endianness == LITTLE)
252 iowrite8(value, i2c->base + reg);
253 else
254 iowrite8(value, i2c->base + reg + 3);
255}
256
257static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
258{
259 u8 ret;
260
261 if (i2c->endianness == LITTLE)
262 ret = ioread8(i2c->base + reg);
263 else
264 ret = ioread8(i2c->base + reg + 3);
265 return ret;
266}
267
268static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
269{
270 if (i2c->endianness == LITTLE)
271 iowrite16(value, i2c->base + reg);
272 else
273 iowrite16be(value, i2c->base + reg + 2);
274}
275
276static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
277{
278 if (i2c->endianness == LITTLE)
279 iowrite32(value, i2c->base + reg);
280 else
281 iowrite32be(value, i2c->base + reg);
282}
283
284static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
285{
286 u32 ret;
287
288 if (i2c->endianness == LITTLE)
289 ret = ioread32(i2c->base + reg);
290 else
291 ret = ioread32be(i2c->base + reg);
292 return ret;
293}
294
295static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
296{
297 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
298
299 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
300}
301
302static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
303{
304 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
305
306 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
307}
308
309static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
310{
311 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
312
313 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
314}
315
316static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
317{
318 xiic_irq_clr(i2c, mask);
319 xiic_irq_en(i2c, mask);
320}
321
322static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
323{
324 u8 sr;
325 unsigned long timeout;
326
327 timeout = jiffies + XIIC_I2C_TIMEOUT;
328 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
329 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
330 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
331 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
332 if (time_after(jiffies, timeout)) {
333 dev_err(i2c->dev, "Failed to clear rx fifo\n");
334 return -ETIMEDOUT;
335 }
336 }
337
338 return 0;
339}
340
341static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
342{
343 u8 isr;
344 unsigned long timeout;
345
346 timeout = jiffies + XIIC_I2C_TIMEOUT;
347 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
348 !(isr & XIIC_INTR_TX_EMPTY_MASK);
349 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
350 if (time_after(jiffies, timeout)) {
351 dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
352 return -ETIMEDOUT;
353 }
354 }
355
356 return 0;
357}
358
359/**
360 * xiic_setclk - Sets the configured clock rate
361 * @i2c: Pointer to the xiic device structure
362 *
363 * The timing register values are calculated according to the input clock
364 * frequency and configured scl frequency. For details, please refer the
365 * AXI I2C PG and NXP I2C Spec.
366 * Supported frequencies are 100KHz, 400KHz and 1MHz.
367 *
368 * Return: 0 on success (Supported frequency selected or not configurable in SW)
369 * -EINVAL on failure (scl frequency not supported or THIGH is 0)
370 */
371static int xiic_setclk(struct xiic_i2c *i2c)
372{
373 unsigned int clk_in_mhz;
374 unsigned int index = 0;
375 u32 reg_val;
376
377 dev_dbg(i2c->adap.dev.parent,
378 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
379 __func__, i2c->input_clk, i2c->i2c_clk);
380
381 /* If not specified in DT, do not configure in SW. Rely only on Vivado design */
382 if (!i2c->i2c_clk || !i2c->input_clk)
383 return 0;
384
385 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
386
387 switch (i2c->i2c_clk) {
388 case I2C_MAX_FAST_MODE_PLUS_FREQ:
389 index = REG_VALUES_1MHZ;
390 break;
391 case I2C_MAX_FAST_MODE_FREQ:
392 index = REG_VALUES_400KHZ;
393 break;
394 case I2C_MAX_STANDARD_MODE_FREQ:
395 index = REG_VALUES_100KHZ;
396 break;
397 default:
398 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
399 return -EINVAL;
400 }
401
402 /*
403 * Value to be stored in a register is the number of clock cycles required
404 * for the time duration. So the time is divided by the input clock time
405 * period to get the number of clock cycles required. Refer Xilinx AXI I2C
406 * PG document and I2C specification for further details.
407 */
408
409 /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */
410 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
411 if (reg_val == 0)
412 return -EINVAL;
413
414 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
415
416 /* TLOW - Value same as THIGH */
417 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
418
419 /* TSUSTA */
420 reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;
421 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
422
423 /* TSUSTO */
424 reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;
425 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
426
427 /* THDSTA */
428 reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;
429 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
430
431 /* TSUDAT */
432 reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;
433 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
434
435 /* TBUF */
436 reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;
437 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
438
439 /* THDDAT */
440 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
441
442 return 0;
443}
444
445static int xiic_reinit(struct xiic_i2c *i2c)
446{
447 int ret;
448
449 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
450
451 ret = xiic_setclk(i2c);
452 if (ret)
453 return ret;
454
455 /* Set receive Fifo depth to maximum (zero based). */
456 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
457
458 /* Reset Tx Fifo. */
459 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
460
461 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
462 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
463
464 /* make sure RX fifo is empty */
465 ret = xiic_clear_rx_fifo(i2c);
466 if (ret)
467 return ret;
468
469 /* Enable interrupts */
470 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
471
472 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
473
474 return 0;
475}
476
477static void xiic_deinit(struct xiic_i2c *i2c)
478{
479 u8 cr;
480
481 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
482
483 /* Disable IIC Device. */
484 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
485 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
486}
487
488static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
489{
490 u8 rxmsg_len, rfd_set = 0;
491
492 /*
493 * Clear the I2C_M_RECV_LEN flag to avoid setting
494 * message length again
495 */
496 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
497
498 /* Set smbus_block_read flag to identify in isr */
499 i2c->smbus_block_read = true;
500
501 /* Read byte from rx fifo and set message length */
502 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
503
504 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
505
506 /* Check if received length is valid */
507 if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) {
508 /* Set Receive fifo depth */
509 if (rxmsg_len > IIC_RX_FIFO_DEPTH) {
510 /*
511 * When Rx msg len greater than or equal to Rx fifo capacity
512 * Receive fifo depth should set to Rx fifo capacity minus 1
513 */
514 rfd_set = IIC_RX_FIFO_DEPTH - 1;
515 i2c->rx_msg->len = rxmsg_len + 1;
516 } else if ((rxmsg_len == 1) ||
517 (rxmsg_len == 0)) {
518 /*
519 * Minimum of 3 bytes required to exit cleanly. 1 byte
520 * already received, Second byte is being received. Have
521 * to set NACK in read_rx before receiving the last byte
522 */
523 rfd_set = 0;
524 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
525 } else {
526 /*
527 * When Rx msg len less than Rx fifo capacity
528 * Receive fifo depth should set to Rx msg len minus 2
529 */
530 rfd_set = rxmsg_len - 2;
531 i2c->rx_msg->len = rxmsg_len + 1;
532 }
533 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
534
535 return;
536 }
537
538 /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */
539 i2c->tx_msg->len = 3;
540 i2c->smbus_block_read = false;
541 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
542}
543
544static void xiic_read_rx(struct xiic_i2c *i2c)
545{
546 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0;
547 u32 bytes_rem = 0;
548 int i;
549
550 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
551
552 dev_dbg(i2c->adap.dev.parent,
553 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n",
554 __func__, bytes_in_fifo, xiic_rx_space(i2c),
555 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
556 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
557
558 if (bytes_in_fifo > xiic_rx_space(i2c))
559 bytes_in_fifo = xiic_rx_space(i2c);
560
561 bytes_to_read = bytes_in_fifo;
562
563 if (!i2c->dynamic) {
564 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
565
566 /* Set msg length if smbus_block_read */
567 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
568 xiic_smbus_block_read_setup(i2c);
569 return;
570 }
571
572 if (bytes_rem > IIC_RX_FIFO_DEPTH) {
573 bytes_to_read = bytes_in_fifo;
574 } else if (bytes_rem > 1) {
575 bytes_to_read = bytes_rem - 1;
576 } else if (bytes_rem == 1) {
577 bytes_to_read = 1;
578 /* Set NACK in CR to indicate slave transmitter */
579 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
580 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
581 XIIC_CR_NO_ACK_MASK);
582 } else if (bytes_rem == 0) {
583 bytes_to_read = bytes_in_fifo;
584
585 /* Generate stop on the bus if it is last message */
586 if (i2c->nmsgs == 1) {
587 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
588 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
589 ~XIIC_CR_MSMS_MASK);
590 }
591
592 /* Make TXACK=0, clean up for next transaction */
593 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
594 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
595 ~XIIC_CR_NO_ACK_MASK);
596 }
597 }
598
599 /* Read the fifo */
600 for (i = 0; i < bytes_to_read; i++) {
601 i2c->rx_msg->buf[i2c->rx_pos++] =
602 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
603 }
604
605 if (i2c->dynamic) {
606 u8 bytes;
607
608 /* Receive remaining bytes if less than fifo depth */
609 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH);
610 bytes--;
611 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
612 }
613}
614
615static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
616{
617 /* return the actual space left in the FIFO */
618 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
619}
620
621static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
622{
623 u8 fifo_space = xiic_tx_fifo_space(i2c);
624 int len = xiic_tx_space(i2c);
625
626 len = (len > fifo_space) ? fifo_space : len;
627
628 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
629 __func__, len, fifo_space);
630
631 while (len--) {
632 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
633
634 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
635 /* last message in transfer -> STOP */
636 if (i2c->dynamic) {
637 data |= XIIC_TX_DYN_STOP_MASK;
638 } else {
639 u8 cr;
640 int status;
641
642 /* Wait till FIFO is empty so STOP is sent last */
643 status = xiic_wait_tx_empty(i2c);
644 if (status)
645 return;
646
647 /* Write to CR to stop */
648 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
649 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
650 ~XIIC_CR_MSMS_MASK);
651 }
652 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
653 }
654 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
655 }
656}
657
658static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
659{
660 i2c->tx_msg = NULL;
661 i2c->rx_msg = NULL;
662 i2c->nmsgs = 0;
663 i2c->state = code;
664 complete(&i2c->completion);
665}
666
667static irqreturn_t xiic_process(int irq, void *dev_id)
668{
669 struct xiic_i2c *i2c = dev_id;
670 u32 pend, isr, ier;
671 u32 clr = 0;
672 int xfer_more = 0;
673 int wakeup_req = 0;
674 enum xilinx_i2c_state wakeup_code = STATE_DONE;
675 int ret;
676
677 /* Get the interrupt Status from the IPIF. There is no clearing of
678 * interrupts in the IPIF. Interrupts must be cleared at the source.
679 * To find which interrupts are pending; AND interrupts pending with
680 * interrupts masked.
681 */
682 mutex_lock(&i2c->lock);
683 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
684 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
685 pend = isr & ier;
686
687 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
688 __func__, ier, isr, pend);
689 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
690 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
691 i2c->tx_msg, i2c->nmsgs);
692 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n",
693 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
694 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
695
696 /* Service requesting interrupt */
697 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
698 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
699 !(pend & XIIC_INTR_RX_FULL_MASK))) {
700 /* bus arbritration lost, or...
701 * Transmit error _OR_ RX completed
702 * if this happens when RX_FULL is not set
703 * this is probably a TX error
704 */
705
706 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
707
708 /* dynamic mode seem to suffer from problems if we just flushes
709 * fifos and the next message is a TX with len 0 (only addr)
710 * reset the IP instead of just flush fifos
711 */
712 ret = xiic_reinit(i2c);
713 if (ret < 0)
714 dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
715
716 if (i2c->rx_msg) {
717 wakeup_req = 1;
718 wakeup_code = STATE_ERROR;
719 }
720 if (i2c->tx_msg) {
721 wakeup_req = 1;
722 wakeup_code = STATE_ERROR;
723 }
724 /* don't try to handle other events */
725 goto out;
726 }
727 if (pend & XIIC_INTR_RX_FULL_MASK) {
728 /* Receive register/FIFO is full */
729
730 clr |= XIIC_INTR_RX_FULL_MASK;
731 if (!i2c->rx_msg) {
732 dev_dbg(i2c->adap.dev.parent,
733 "%s unexpected RX IRQ\n", __func__);
734 xiic_clear_rx_fifo(i2c);
735 goto out;
736 }
737
738 xiic_read_rx(i2c);
739 if (xiic_rx_space(i2c) == 0) {
740 /* this is the last part of the message */
741 i2c->rx_msg = NULL;
742
743 /* also clear TX error if there (RX complete) */
744 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
745
746 dev_dbg(i2c->adap.dev.parent,
747 "%s end of message, nmsgs: %d\n",
748 __func__, i2c->nmsgs);
749
750 /* send next message if this wasn't the last,
751 * otherwise the transfer will be finialise when
752 * receiving the bus not busy interrupt
753 */
754 if (i2c->nmsgs > 1) {
755 i2c->nmsgs--;
756 i2c->tx_msg++;
757 dev_dbg(i2c->adap.dev.parent,
758 "%s will start next...\n", __func__);
759 xfer_more = 1;
760 }
761 }
762 }
763 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
764 /* Transmit register/FIFO is empty or ½ empty */
765
766 clr |= (pend &
767 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
768
769 if (!i2c->tx_msg) {
770 dev_dbg(i2c->adap.dev.parent,
771 "%s unexpected TX IRQ\n", __func__);
772 goto out;
773 }
774
775 if (xiic_tx_space(i2c)) {
776 xiic_fill_tx_fifo(i2c);
777 } else {
778 /* current message fully written */
779 dev_dbg(i2c->adap.dev.parent,
780 "%s end of message sent, nmsgs: %d\n",
781 __func__, i2c->nmsgs);
782 /* Don't move onto the next message until the TX FIFO empties,
783 * to ensure that a NAK is not missed.
784 */
785 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) {
786 i2c->nmsgs--;
787 i2c->tx_msg++;
788 xfer_more = 1;
789 } else {
790 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
791
792 dev_dbg(i2c->adap.dev.parent,
793 "%s Got TX IRQ but no more to do...\n",
794 __func__);
795 }
796 }
797 }
798
799 if (pend & XIIC_INTR_BNB_MASK) {
800 /* IIC bus has transitioned to not busy */
801 clr |= XIIC_INTR_BNB_MASK;
802
803 /* The bus is not busy, disable BusNotBusy interrupt */
804 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
805
806 if (i2c->tx_msg && i2c->smbus_block_read) {
807 i2c->smbus_block_read = false;
808 /* Set requested message len=1 to indicate STATE_DONE */
809 i2c->tx_msg->len = 1;
810 }
811
812 if (!i2c->tx_msg)
813 goto out;
814
815 wakeup_req = 1;
816
817 if (i2c->nmsgs == 1 && !i2c->rx_msg &&
818 xiic_tx_space(i2c) == 0)
819 wakeup_code = STATE_DONE;
820 else
821 wakeup_code = STATE_ERROR;
822 }
823
824out:
825 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
826
827 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
828 if (xfer_more)
829 __xiic_start_xfer(i2c);
830 if (wakeup_req)
831 xiic_wakeup(i2c, wakeup_code);
832
833 WARN_ON(xfer_more && wakeup_req);
834
835 mutex_unlock(&i2c->lock);
836 return IRQ_HANDLED;
837}
838
839static int xiic_bus_busy(struct xiic_i2c *i2c)
840{
841 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
842
843 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
844}
845
846static int xiic_wait_not_busy(struct xiic_i2c *i2c)
847{
848 int tries = 3;
849 int err;
850
851 /* for instance if previous transfer was terminated due to TX error
852 * it might be that the bus is on it's way to become available
853 * give it at most 3 ms to wake
854 */
855 err = xiic_bus_busy(i2c);
856 while (err && tries--) {
857 msleep(1);
858 err = xiic_bus_busy(i2c);
859 }
860
861 return err;
862}
863
864static void xiic_start_recv(struct xiic_i2c *i2c)
865{
866 u16 rx_watermark;
867 u8 cr = 0, rfd_set = 0;
868 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
869
870 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
871 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
872 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
873
874 /* Disable Tx interrupts */
875 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK);
876
877 if (i2c->dynamic) {
878 u8 bytes;
879 u16 val;
880
881 /* Clear and enable Rx full interrupt. */
882 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
883 XIIC_INTR_TX_ERROR_MASK);
884
885 /*
886 * We want to get all but last byte, because the TX_ERROR IRQ
887 * is used to indicate error ACK on the address, and
888 * negative ack on the last received byte, so to not mix
889 * them receive all but last.
890 * In the case where there is only one byte to receive
891 * we can check if ERROR and RX full is set at the same time
892 */
893 rx_watermark = msg->len;
894 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH);
895
896 if (rx_watermark > 0)
897 bytes--;
898 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
899
900 /* write the address */
901 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
902 i2c_8bit_addr_from_msg(msg) |
903 XIIC_TX_DYN_START_MASK);
904
905 /* If last message, include dynamic stop bit with length */
906 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
907 val |= msg->len;
908
909 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
910
911 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
912 } else {
913 /*
914 * If previous message is Tx, make sure that Tx FIFO is empty
915 * before starting a new transfer as the repeated start in
916 * standard mode can corrupt the transaction if there are
917 * still bytes to be transmitted in FIFO
918 */
919 if (i2c->prev_msg_tx) {
920 int status;
921
922 status = xiic_wait_tx_empty(i2c);
923 if (status)
924 return;
925 }
926
927 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
928
929 /* Set Receive fifo depth */
930 rx_watermark = msg->len;
931 if (rx_watermark > IIC_RX_FIFO_DEPTH) {
932 rfd_set = IIC_RX_FIFO_DEPTH - 1;
933 } else if (rx_watermark == 1) {
934 rfd_set = rx_watermark - 1;
935
936 /* Set No_ACK, except for smbus_block_read */
937 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
938 /* Handle single byte transfer separately */
939 cr |= XIIC_CR_NO_ACK_MASK;
940 }
941 } else if (rx_watermark == 0) {
942 rfd_set = rx_watermark;
943 } else {
944 rfd_set = rx_watermark - 2;
945 }
946 /* Check if RSTA should be set */
947 if (cr & XIIC_CR_MSMS_MASK) {
948 /* Already a master, RSTA should be set */
949 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
950 XIIC_CR_REPEATED_START_MASK) &
951 ~(XIIC_CR_DIR_IS_TX_MASK));
952 }
953
954 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
955
956 /* Clear and enable Rx full and transmit complete interrupts */
957 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
958 XIIC_INTR_TX_ERROR_MASK);
959
960 /* Write the address */
961 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
962 i2c_8bit_addr_from_msg(msg));
963
964 /* Write to Control Register,to start transaction in Rx mode */
965 if ((cr & XIIC_CR_MSMS_MASK) == 0) {
966 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
967 XIIC_CR_MSMS_MASK)
968 & ~(XIIC_CR_DIR_IS_TX_MASK));
969 }
970 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
971 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
972 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
973 }
974
975 if (i2c->nmsgs == 1)
976 /* very last, enable bus not busy as well */
977 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
978
979 /* the message is tx:ed */
980 i2c->tx_pos = msg->len;
981
982 /* Enable interrupts */
983 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
984
985 i2c->prev_msg_tx = false;
986}
987
988static void xiic_start_send(struct xiic_i2c *i2c)
989{
990 u8 cr = 0;
991 u16 data;
992 struct i2c_msg *msg = i2c->tx_msg;
993
994 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
995 __func__, msg, msg->len);
996 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
997 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
998 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
999
1000 if (i2c->dynamic) {
1001 /* write the address */
1002 data = i2c_8bit_addr_from_msg(msg) |
1003 XIIC_TX_DYN_START_MASK;
1004
1005 if (i2c->nmsgs == 1 && msg->len == 0)
1006 /* no data and last message -> add STOP */
1007 data |= XIIC_TX_DYN_STOP_MASK;
1008
1009 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1010
1011 /* Clear any pending Tx empty, Tx Error and then enable them */
1012 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1013 XIIC_INTR_TX_ERROR_MASK |
1014 XIIC_INTR_BNB_MASK |
1015 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
1016 XIIC_INTR_TX_HALF_MASK : 0));
1017
1018 xiic_fill_tx_fifo(i2c);
1019 } else {
1020 /*
1021 * If previous message is Tx, make sure that Tx FIFO is empty
1022 * before starting a new transfer as the repeated start in
1023 * standard mode can corrupt the transaction if there are
1024 * still bytes to be transmitted in FIFO
1025 */
1026 if (i2c->prev_msg_tx) {
1027 int status;
1028
1029 status = xiic_wait_tx_empty(i2c);
1030 if (status)
1031 return;
1032 }
1033 /* Check if RSTA should be set */
1034 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1035 if (cr & XIIC_CR_MSMS_MASK) {
1036 /* Already a master, RSTA should be set */
1037 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1038 XIIC_CR_REPEATED_START_MASK |
1039 XIIC_CR_DIR_IS_TX_MASK) &
1040 ~(XIIC_CR_NO_ACK_MASK));
1041 }
1042
1043 /* Write address to FIFO */
1044 data = i2c_8bit_addr_from_msg(msg);
1045 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1046
1047 /* Fill fifo */
1048 xiic_fill_tx_fifo(i2c);
1049
1050 if ((cr & XIIC_CR_MSMS_MASK) == 0) {
1051 /* Start Tx by writing to CR */
1052 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1053 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
1054 XIIC_CR_MSMS_MASK |
1055 XIIC_CR_DIR_IS_TX_MASK);
1056 }
1057
1058 /* Clear any pending Tx empty, Tx Error and then enable them */
1059 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1060 XIIC_INTR_TX_ERROR_MASK |
1061 XIIC_INTR_BNB_MASK);
1062 }
1063 i2c->prev_msg_tx = true;
1064}
1065
1066static void __xiic_start_xfer(struct xiic_i2c *i2c)
1067{
1068 int fifo_space = xiic_tx_fifo_space(i2c);
1069
1070 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1071 __func__, i2c->tx_msg, fifo_space);
1072
1073 if (!i2c->tx_msg)
1074 return;
1075
1076 i2c->rx_pos = 0;
1077 i2c->tx_pos = 0;
1078 i2c->state = STATE_START;
1079 if (i2c->tx_msg->flags & I2C_M_RD) {
1080 /* we dont date putting several reads in the FIFO */
1081 xiic_start_recv(i2c);
1082 } else {
1083 xiic_start_send(i2c);
1084 }
1085}
1086
1087static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
1088{
1089 bool broken_read, max_read_len, smbus_blk_read;
1090 int ret, count;
1091
1092 mutex_lock(&i2c->lock);
1093
1094 if (i2c->tx_msg || i2c->rx_msg) {
1095 dev_err(i2c->adap.dev.parent,
1096 "cannot start a transfer while busy\n");
1097 ret = -EBUSY;
1098 goto out;
1099 }
1100
1101 /* In single master mode bus can only be busy, when in use by this
1102 * driver. If the register indicates bus being busy for some reason we
1103 * should ignore it, since bus will never be released and i2c will be
1104 * stuck forever.
1105 */
1106 if (!i2c->singlemaster) {
1107 ret = xiic_wait_not_busy(i2c);
1108 if (ret) {
1109 /* If the bus is stuck in a busy state, such as due to spurious low
1110 * pulses on the bus causing a false start condition to be detected,
1111 * then try to recover by re-initializing the controller and check
1112 * again if the bus is still busy.
1113 */
1114 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n");
1115 ret = xiic_reinit(i2c);
1116 if (ret)
1117 goto out;
1118 ret = xiic_wait_not_busy(i2c);
1119 if (ret)
1120 goto out;
1121 }
1122 }
1123
1124 i2c->tx_msg = msgs;
1125 i2c->rx_msg = NULL;
1126 i2c->nmsgs = num;
1127 init_completion(&i2c->completion);
1128
1129 /* Decide standard mode or Dynamic mode */
1130 i2c->dynamic = true;
1131
1132 /* Initialize prev message type */
1133 i2c->prev_msg_tx = false;
1134
1135 /*
1136 * Scan through nmsgs, use dynamic mode when none of the below three
1137 * conditions occur. We need standard mode even if one condition holds
1138 * true in the entire array of messages in a single transfer.
1139 * If read transaction as dynamic mode is broken for delayed reads
1140 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions.
1141 * If read length is > 255 bytes.
1142 * If smbus_block_read transaction.
1143 */
1144 for (count = 0; count < i2c->nmsgs; count++) {
1145 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
1146 (i2c->tx_msg[count].flags & I2C_M_RD);
1147 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
1148 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
1149 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
1150
1151 if (broken_read || max_read_len || smbus_blk_read) {
1152 i2c->dynamic = false;
1153 break;
1154 }
1155 }
1156
1157 ret = xiic_reinit(i2c);
1158 if (!ret)
1159 __xiic_start_xfer(i2c);
1160
1161out:
1162 mutex_unlock(&i2c->lock);
1163
1164 return ret;
1165}
1166
1167static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1168{
1169 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1170 int err;
1171
1172 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
1173 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
1174
1175 err = pm_runtime_resume_and_get(i2c->dev);
1176 if (err < 0)
1177 return err;
1178
1179 err = xiic_start_xfer(i2c, msgs, num);
1180 if (err < 0)
1181 goto out;
1182
1183 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
1184 mutex_lock(&i2c->lock);
1185 if (err == 0) { /* Timeout */
1186 i2c->tx_msg = NULL;
1187 i2c->rx_msg = NULL;
1188 i2c->nmsgs = 0;
1189 err = -ETIMEDOUT;
1190 } else {
1191 err = (i2c->state == STATE_DONE) ? num : -EIO;
1192 }
1193 mutex_unlock(&i2c->lock);
1194
1195out:
1196 pm_runtime_mark_last_busy(i2c->dev);
1197 pm_runtime_put_autosuspend(i2c->dev);
1198 return err;
1199}
1200
1201static u32 xiic_func(struct i2c_adapter *adap)
1202{
1203 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
1204}
1205
1206static const struct i2c_algorithm xiic_algorithm = {
1207 .master_xfer = xiic_xfer,
1208 .functionality = xiic_func,
1209};
1210
1211static const struct i2c_adapter xiic_adapter = {
1212 .owner = THIS_MODULE,
1213 .class = I2C_CLASS_DEPRECATED,
1214 .algo = &xiic_algorithm,
1215};
1216
1217#if defined(CONFIG_OF)
1218static const struct xiic_version_data xiic_2_00 = {
1219 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT,
1220};
1221
1222static const struct of_device_id xiic_of_match[] = {
1223 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
1224 { .compatible = "xlnx,axi-iic-2.1", },
1225 {},
1226};
1227MODULE_DEVICE_TABLE(of, xiic_of_match);
1228#endif
1229
1230static int xiic_i2c_probe(struct platform_device *pdev)
1231{
1232 struct xiic_i2c *i2c;
1233 struct xiic_i2c_platform_data *pdata;
1234 const struct of_device_id *match;
1235 struct resource *res;
1236 int ret, irq;
1237 u8 i;
1238 u32 sr;
1239
1240 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1241 if (!i2c)
1242 return -ENOMEM;
1243
1244 match = of_match_node(xiic_of_match, pdev->dev.of_node);
1245 if (match && match->data) {
1246 const struct xiic_version_data *data = match->data;
1247
1248 i2c->quirks = data->quirks;
1249 }
1250
1251 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1252 if (IS_ERR(i2c->base))
1253 return PTR_ERR(i2c->base);
1254
1255 irq = platform_get_irq(pdev, 0);
1256 if (irq < 0)
1257 return irq;
1258
1259 pdata = dev_get_platdata(&pdev->dev);
1260
1261 /* hook up driver to tree */
1262 platform_set_drvdata(pdev, i2c);
1263 i2c->adap = xiic_adapter;
1264 i2c_set_adapdata(&i2c->adap, i2c);
1265 i2c->adap.dev.parent = &pdev->dev;
1266 i2c->adap.dev.of_node = pdev->dev.of_node;
1267 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
1268 DRIVER_NAME " %s", pdev->name);
1269
1270 mutex_init(&i2c->lock);
1271
1272 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1273 if (IS_ERR(i2c->clk))
1274 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
1275 "failed to enable input clock.\n");
1276
1277 i2c->dev = &pdev->dev;
1278 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
1279 pm_runtime_use_autosuspend(i2c->dev);
1280 pm_runtime_set_active(i2c->dev);
1281 pm_runtime_enable(i2c->dev);
1282
1283 /* SCL frequency configuration */
1284 i2c->input_clk = clk_get_rate(i2c->clk);
1285 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1286 &i2c->i2c_clk);
1287 /* If clock-frequency not specified in DT, do not configure in SW */
1288 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
1289 i2c->i2c_clk = 0;
1290
1291 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1292 xiic_process, IRQF_ONESHOT,
1293 pdev->name, i2c);
1294
1295 if (ret < 0) {
1296 dev_err(&pdev->dev, "Cannot claim IRQ\n");
1297 goto err_pm_disable;
1298 }
1299
1300 i2c->singlemaster =
1301 of_property_read_bool(pdev->dev.of_node, "single-master");
1302
1303 /*
1304 * Detect endianness
1305 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
1306 * set, assume that the endianness was wrong and swap.
1307 */
1308 i2c->endianness = LITTLE;
1309 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
1310 /* Reset is cleared in xiic_reinit */
1311 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
1312 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
1313 i2c->endianness = BIG;
1314
1315 ret = xiic_reinit(i2c);
1316 if (ret < 0) {
1317 dev_err(&pdev->dev, "Cannot xiic_reinit\n");
1318 goto err_pm_disable;
1319 }
1320
1321 /* add i2c adapter to i2c tree */
1322 ret = i2c_add_adapter(&i2c->adap);
1323 if (ret) {
1324 xiic_deinit(i2c);
1325 goto err_pm_disable;
1326 }
1327
1328 if (pdata) {
1329 /* add in known devices to the bus */
1330 for (i = 0; i < pdata->num_devices; i++)
1331 i2c_new_client_device(&i2c->adap, pdata->devices + i);
1332 }
1333
1334 dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n",
1335 (unsigned long)res->start, irq, i2c->i2c_clk);
1336
1337 return 0;
1338
1339err_pm_disable:
1340 pm_runtime_disable(&pdev->dev);
1341 pm_runtime_set_suspended(&pdev->dev);
1342
1343 return ret;
1344}
1345
1346static void xiic_i2c_remove(struct platform_device *pdev)
1347{
1348 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
1349 int ret;
1350
1351 /* remove adapter & data */
1352 i2c_del_adapter(&i2c->adap);
1353
1354 ret = pm_runtime_get_sync(i2c->dev);
1355
1356 if (ret < 0)
1357 dev_warn(&pdev->dev, "Failed to activate device for removal (%pe)\n",
1358 ERR_PTR(ret));
1359 else
1360 xiic_deinit(i2c);
1361
1362 pm_runtime_put_sync(i2c->dev);
1363 pm_runtime_disable(&pdev->dev);
1364 pm_runtime_set_suspended(&pdev->dev);
1365 pm_runtime_dont_use_autosuspend(&pdev->dev);
1366}
1367
1368static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
1369{
1370 struct xiic_i2c *i2c = dev_get_drvdata(dev);
1371
1372 clk_disable(i2c->clk);
1373
1374 return 0;
1375}
1376
1377static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
1378{
1379 struct xiic_i2c *i2c = dev_get_drvdata(dev);
1380 int ret;
1381
1382 ret = clk_enable(i2c->clk);
1383 if (ret) {
1384 dev_err(dev, "Cannot enable clock.\n");
1385 return ret;
1386 }
1387
1388 return 0;
1389}
1390
1391static const struct dev_pm_ops xiic_dev_pm_ops = {
1392 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
1393 xiic_i2c_runtime_resume, NULL)
1394};
1395
1396static struct platform_driver xiic_i2c_driver = {
1397 .probe = xiic_i2c_probe,
1398 .remove = xiic_i2c_remove,
1399 .driver = {
1400 .name = DRIVER_NAME,
1401 .of_match_table = of_match_ptr(xiic_of_match),
1402 .pm = &xiic_dev_pm_ops,
1403 },
1404};
1405
1406module_platform_driver(xiic_i2c_driver);
1407
1408MODULE_ALIAS("platform:" DRIVER_NAME);
1409MODULE_AUTHOR("info@mocean-labs.com");
1410MODULE_DESCRIPTION("Xilinx I2C bus driver");
1411MODULE_LICENSE("GPL v2");
1/*
2 * i2c-xiic.c
3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *
20 * This code was implemented by Mocean Laboratories AB when porting linux
21 * to the automotive development board Russellville. The copyright holder
22 * as seen in the header is Intel corporation.
23 * Mocean Laboratories forked off the GNU/Linux platform work into a
24 * separate company called Pelagicore AB, which committed the code to the
25 * kernel.
26 */
27
28/* Supports:
29 * Xilinx IIC
30 */
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/delay.h>
36#include <linux/platform_device.h>
37#include <linux/i2c.h>
38#include <linux/interrupt.h>
39#include <linux/wait.h>
40#include <linux/i2c-xiic.h>
41#include <linux/io.h>
42#include <linux/slab.h>
43#include <linux/of.h>
44
45#define DRIVER_NAME "xiic-i2c"
46
47enum xilinx_i2c_state {
48 STATE_DONE,
49 STATE_ERROR,
50 STATE_START
51};
52
53/**
54 * struct xiic_i2c - Internal representation of the XIIC I2C bus
55 * @base: Memory base of the HW registers
56 * @wait: Wait queue for callers
57 * @adap: Kernel adapter representation
58 * @tx_msg: Messages from above to be sent
59 * @lock: Mutual exclusion
60 * @tx_pos: Current pos in TX message
61 * @nmsgs: Number of messages in tx_msg
62 * @state: See STATE_
63 * @rx_msg: Current RX message
64 * @rx_pos: Position within current RX message
65 */
66struct xiic_i2c {
67 void __iomem *base;
68 wait_queue_head_t wait;
69 struct i2c_adapter adap;
70 struct i2c_msg *tx_msg;
71 spinlock_t lock;
72 unsigned int tx_pos;
73 unsigned int nmsgs;
74 enum xilinx_i2c_state state;
75 struct i2c_msg *rx_msg;
76 int rx_pos;
77};
78
79
80#define XIIC_MSB_OFFSET 0
81#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
82
83/*
84 * Register offsets in bytes from RegisterBase. Three is added to the
85 * base offset to access LSB (IBM style) of the word
86 */
87#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
88#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
89#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
90#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
91#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
92#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
93#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
94#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
95#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
96#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
97
98/* Control Register masks */
99#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
100#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
101#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
102#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
103#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
104#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
105#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
106
107/* Status Register masks */
108#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
109#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
110#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
111#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
112#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
113#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
114#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
115#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
116
117/* Interrupt Status Register masks Interrupt occurs when... */
118#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
119#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
120#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
121#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
122#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
123#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
124#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
125#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
126
127/* The following constants specify the depth of the FIFOs */
128#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
129#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
130
131/* The following constants specify groups of interrupts that are typically
132 * enabled or disables at the same time
133 */
134#define XIIC_TX_INTERRUPTS \
135(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
136
137#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
138
139/* The following constants are used with the following macros to specify the
140 * operation, a read or write operation.
141 */
142#define XIIC_READ_OPERATION 1
143#define XIIC_WRITE_OPERATION 0
144
145/*
146 * Tx Fifo upper bit masks.
147 */
148#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
149#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
150
151/*
152 * The following constants define the register offsets for the Interrupt
153 * registers. There are some holes in the memory map for reserved addresses
154 * to allow other registers to be added and still match the memory map of the
155 * interrupt controller registers
156 */
157#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
158#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
159#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
160#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
161
162#define XIIC_RESET_MASK 0xAUL
163
164/*
165 * The following constant is used for the device global interrupt enable
166 * register, to enable all interrupts for the device, this is the only bit
167 * in the register
168 */
169#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
170
171#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
172#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
173
174static void xiic_start_xfer(struct xiic_i2c *i2c);
175static void __xiic_start_xfer(struct xiic_i2c *i2c);
176
177static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
178{
179 iowrite8(value, i2c->base + reg);
180}
181
182static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
183{
184 return ioread8(i2c->base + reg);
185}
186
187static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
188{
189 iowrite16(value, i2c->base + reg);
190}
191
192static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
193{
194 iowrite32(value, i2c->base + reg);
195}
196
197static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
198{
199 return ioread32(i2c->base + reg);
200}
201
202static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
203{
204 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
205 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
206}
207
208static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
209{
210 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
211 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
212}
213
214static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
215{
216 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
217 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
218}
219
220static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
221{
222 xiic_irq_clr(i2c, mask);
223 xiic_irq_en(i2c, mask);
224}
225
226static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
227{
228 u8 sr;
229 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
230 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
231 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
232 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
233}
234
235static void xiic_reinit(struct xiic_i2c *i2c)
236{
237 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
238
239 /* Set receive Fifo depth to maximum (zero based). */
240 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
241
242 /* Reset Tx Fifo. */
243 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
244
245 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
246 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
247
248 /* make sure RX fifo is empty */
249 xiic_clear_rx_fifo(i2c);
250
251 /* Enable interrupts */
252 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
253
254 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
255}
256
257static void xiic_deinit(struct xiic_i2c *i2c)
258{
259 u8 cr;
260
261 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
262
263 /* Disable IIC Device. */
264 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
265 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
266}
267
268static void xiic_read_rx(struct xiic_i2c *i2c)
269{
270 u8 bytes_in_fifo;
271 int i;
272
273 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
274
275 dev_dbg(i2c->adap.dev.parent,
276 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
277 __func__, bytes_in_fifo, xiic_rx_space(i2c),
278 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
279 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
280
281 if (bytes_in_fifo > xiic_rx_space(i2c))
282 bytes_in_fifo = xiic_rx_space(i2c);
283
284 for (i = 0; i < bytes_in_fifo; i++)
285 i2c->rx_msg->buf[i2c->rx_pos++] =
286 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
287
288 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
289 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
290 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
291}
292
293static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
294{
295 /* return the actual space left in the FIFO */
296 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
297}
298
299static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
300{
301 u8 fifo_space = xiic_tx_fifo_space(i2c);
302 int len = xiic_tx_space(i2c);
303
304 len = (len > fifo_space) ? fifo_space : len;
305
306 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
307 __func__, len, fifo_space);
308
309 while (len--) {
310 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
311 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
312 /* last message in transfer -> STOP */
313 data |= XIIC_TX_DYN_STOP_MASK;
314 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
315 }
316 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
317 }
318}
319
320static void xiic_wakeup(struct xiic_i2c *i2c, int code)
321{
322 i2c->tx_msg = NULL;
323 i2c->rx_msg = NULL;
324 i2c->nmsgs = 0;
325 i2c->state = code;
326 wake_up(&i2c->wait);
327}
328
329static void xiic_process(struct xiic_i2c *i2c)
330{
331 u32 pend, isr, ier;
332 u32 clr = 0;
333
334 /* Get the interrupt Status from the IPIF. There is no clearing of
335 * interrupts in the IPIF. Interrupts must be cleared at the source.
336 * To find which interrupts are pending; AND interrupts pending with
337 * interrupts masked.
338 */
339 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
340 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
341 pend = isr & ier;
342
343 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
344 __func__, ier, isr, pend);
345 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
346 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
347 i2c->tx_msg, i2c->nmsgs);
348
349 /* Do not processes a devices interrupts if the device has no
350 * interrupts pending
351 */
352 if (!pend)
353 return;
354
355 /* Service requesting interrupt */
356 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
357 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
358 !(pend & XIIC_INTR_RX_FULL_MASK))) {
359 /* bus arbritration lost, or...
360 * Transmit error _OR_ RX completed
361 * if this happens when RX_FULL is not set
362 * this is probably a TX error
363 */
364
365 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
366
367 /* dynamic mode seem to suffer from problems if we just flushes
368 * fifos and the next message is a TX with len 0 (only addr)
369 * reset the IP instead of just flush fifos
370 */
371 xiic_reinit(i2c);
372
373 if (i2c->tx_msg)
374 xiic_wakeup(i2c, STATE_ERROR);
375
376 } else if (pend & XIIC_INTR_RX_FULL_MASK) {
377 /* Receive register/FIFO is full */
378
379 clr = XIIC_INTR_RX_FULL_MASK;
380 if (!i2c->rx_msg) {
381 dev_dbg(i2c->adap.dev.parent,
382 "%s unexpexted RX IRQ\n", __func__);
383 xiic_clear_rx_fifo(i2c);
384 goto out;
385 }
386
387 xiic_read_rx(i2c);
388 if (xiic_rx_space(i2c) == 0) {
389 /* this is the last part of the message */
390 i2c->rx_msg = NULL;
391
392 /* also clear TX error if there (RX complete) */
393 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
394
395 dev_dbg(i2c->adap.dev.parent,
396 "%s end of message, nmsgs: %d\n",
397 __func__, i2c->nmsgs);
398
399 /* send next message if this wasn't the last,
400 * otherwise the transfer will be finialise when
401 * receiving the bus not busy interrupt
402 */
403 if (i2c->nmsgs > 1) {
404 i2c->nmsgs--;
405 i2c->tx_msg++;
406 dev_dbg(i2c->adap.dev.parent,
407 "%s will start next...\n", __func__);
408
409 __xiic_start_xfer(i2c);
410 }
411 }
412 } else if (pend & XIIC_INTR_BNB_MASK) {
413 /* IIC bus has transitioned to not busy */
414 clr = XIIC_INTR_BNB_MASK;
415
416 /* The bus is not busy, disable BusNotBusy interrupt */
417 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
418
419 if (!i2c->tx_msg)
420 goto out;
421
422 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
423 xiic_tx_space(i2c) == 0)
424 xiic_wakeup(i2c, STATE_DONE);
425 else
426 xiic_wakeup(i2c, STATE_ERROR);
427
428 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
429 /* Transmit register/FIFO is empty or ½ empty */
430
431 clr = pend &
432 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
433
434 if (!i2c->tx_msg) {
435 dev_dbg(i2c->adap.dev.parent,
436 "%s unexpexted TX IRQ\n", __func__);
437 goto out;
438 }
439
440 xiic_fill_tx_fifo(i2c);
441
442 /* current message sent and there is space in the fifo */
443 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
444 dev_dbg(i2c->adap.dev.parent,
445 "%s end of message sent, nmsgs: %d\n",
446 __func__, i2c->nmsgs);
447 if (i2c->nmsgs > 1) {
448 i2c->nmsgs--;
449 i2c->tx_msg++;
450 __xiic_start_xfer(i2c);
451 } else {
452 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
453
454 dev_dbg(i2c->adap.dev.parent,
455 "%s Got TX IRQ but no more to do...\n",
456 __func__);
457 }
458 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
459 /* current frame is sent and is last,
460 * make sure to disable tx half
461 */
462 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
463 } else {
464 /* got IRQ which is not acked */
465 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
466 __func__);
467 clr = pend;
468 }
469out:
470 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
471
472 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
473}
474
475static int xiic_bus_busy(struct xiic_i2c *i2c)
476{
477 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
478
479 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
480}
481
482static int xiic_busy(struct xiic_i2c *i2c)
483{
484 int tries = 3;
485 int err;
486
487 if (i2c->tx_msg)
488 return -EBUSY;
489
490 /* for instance if previous transfer was terminated due to TX error
491 * it might be that the bus is on it's way to become available
492 * give it at most 3 ms to wake
493 */
494 err = xiic_bus_busy(i2c);
495 while (err && tries--) {
496 mdelay(1);
497 err = xiic_bus_busy(i2c);
498 }
499
500 return err;
501}
502
503static void xiic_start_recv(struct xiic_i2c *i2c)
504{
505 u8 rx_watermark;
506 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
507
508 /* Clear and enable Rx full interrupt. */
509 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
510
511 /* we want to get all but last byte, because the TX_ERROR IRQ is used
512 * to inidicate error ACK on the address, and negative ack on the last
513 * received byte, so to not mix them receive all but last.
514 * In the case where there is only one byte to receive
515 * we can check if ERROR and RX full is set at the same time
516 */
517 rx_watermark = msg->len;
518 if (rx_watermark > IIC_RX_FIFO_DEPTH)
519 rx_watermark = IIC_RX_FIFO_DEPTH;
520 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
521
522 if (!(msg->flags & I2C_M_NOSTART))
523 /* write the address */
524 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
525 (msg->addr << 1) | XIIC_READ_OPERATION |
526 XIIC_TX_DYN_START_MASK);
527
528 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
529
530 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
531 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
532 if (i2c->nmsgs == 1)
533 /* very last, enable bus not busy as well */
534 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
535
536 /* the message is tx:ed */
537 i2c->tx_pos = msg->len;
538}
539
540static void xiic_start_send(struct xiic_i2c *i2c)
541{
542 struct i2c_msg *msg = i2c->tx_msg;
543
544 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
545
546 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
547 __func__, msg, msg->len);
548 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
549 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
550 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
551
552 if (!(msg->flags & I2C_M_NOSTART)) {
553 /* write the address */
554 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
555 XIIC_TX_DYN_START_MASK;
556 if ((i2c->nmsgs == 1) && msg->len == 0)
557 /* no data and last message -> add STOP */
558 data |= XIIC_TX_DYN_STOP_MASK;
559
560 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
561 }
562
563 xiic_fill_tx_fifo(i2c);
564
565 /* Clear any pending Tx empty, Tx Error and then enable them. */
566 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
567 XIIC_INTR_BNB_MASK);
568}
569
570static irqreturn_t xiic_isr(int irq, void *dev_id)
571{
572 struct xiic_i2c *i2c = dev_id;
573
574 spin_lock(&i2c->lock);
575 /* disable interrupts globally */
576 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
577
578 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
579
580 xiic_process(i2c);
581
582 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
583 spin_unlock(&i2c->lock);
584
585 return IRQ_HANDLED;
586}
587
588static void __xiic_start_xfer(struct xiic_i2c *i2c)
589{
590 int first = 1;
591 int fifo_space = xiic_tx_fifo_space(i2c);
592 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
593 __func__, i2c->tx_msg, fifo_space);
594
595 if (!i2c->tx_msg)
596 return;
597
598 i2c->rx_pos = 0;
599 i2c->tx_pos = 0;
600 i2c->state = STATE_START;
601 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
602 if (!first) {
603 i2c->nmsgs--;
604 i2c->tx_msg++;
605 i2c->tx_pos = 0;
606 } else
607 first = 0;
608
609 if (i2c->tx_msg->flags & I2C_M_RD) {
610 /* we dont date putting several reads in the FIFO */
611 xiic_start_recv(i2c);
612 return;
613 } else {
614 xiic_start_send(i2c);
615 if (xiic_tx_space(i2c) != 0) {
616 /* the message could not be completely sent */
617 break;
618 }
619 }
620
621 fifo_space = xiic_tx_fifo_space(i2c);
622 }
623
624 /* there are more messages or the current one could not be completely
625 * put into the FIFO, also enable the half empty interrupt
626 */
627 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
628 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
629
630}
631
632static void xiic_start_xfer(struct xiic_i2c *i2c)
633{
634 unsigned long flags;
635
636 spin_lock_irqsave(&i2c->lock, flags);
637 xiic_reinit(i2c);
638 /* disable interrupts globally */
639 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
640 spin_unlock_irqrestore(&i2c->lock, flags);
641
642 __xiic_start_xfer(i2c);
643 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
644}
645
646static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
647{
648 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
649 int err;
650
651 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
652 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
653
654 err = xiic_busy(i2c);
655 if (err)
656 return err;
657
658 i2c->tx_msg = msgs;
659 i2c->nmsgs = num;
660
661 xiic_start_xfer(i2c);
662
663 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
664 (i2c->state == STATE_DONE), HZ))
665 return (i2c->state == STATE_DONE) ? num : -EIO;
666 else {
667 i2c->tx_msg = NULL;
668 i2c->rx_msg = NULL;
669 i2c->nmsgs = 0;
670 return -ETIMEDOUT;
671 }
672}
673
674static u32 xiic_func(struct i2c_adapter *adap)
675{
676 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
677}
678
679static const struct i2c_algorithm xiic_algorithm = {
680 .master_xfer = xiic_xfer,
681 .functionality = xiic_func,
682};
683
684static struct i2c_adapter xiic_adapter = {
685 .owner = THIS_MODULE,
686 .name = DRIVER_NAME,
687 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED,
688 .algo = &xiic_algorithm,
689};
690
691
692static int xiic_i2c_probe(struct platform_device *pdev)
693{
694 struct xiic_i2c *i2c;
695 struct xiic_i2c_platform_data *pdata;
696 struct resource *res;
697 int ret, irq;
698 u8 i;
699
700 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
701 if (!i2c)
702 return -ENOMEM;
703
704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 i2c->base = devm_ioremap_resource(&pdev->dev, res);
706 if (IS_ERR(i2c->base))
707 return PTR_ERR(i2c->base);
708
709 irq = platform_get_irq(pdev, 0);
710 if (irq < 0)
711 return irq;
712
713 pdata = dev_get_platdata(&pdev->dev);
714
715 /* hook up driver to tree */
716 platform_set_drvdata(pdev, i2c);
717 i2c->adap = xiic_adapter;
718 i2c_set_adapdata(&i2c->adap, i2c);
719 i2c->adap.dev.parent = &pdev->dev;
720 i2c->adap.dev.of_node = pdev->dev.of_node;
721
722 spin_lock_init(&i2c->lock);
723 init_waitqueue_head(&i2c->wait);
724
725 ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c);
726 if (ret < 0) {
727 dev_err(&pdev->dev, "Cannot claim IRQ\n");
728 return ret;
729 }
730
731 xiic_reinit(i2c);
732
733 /* add i2c adapter to i2c tree */
734 ret = i2c_add_adapter(&i2c->adap);
735 if (ret) {
736 dev_err(&pdev->dev, "Failed to add adapter\n");
737 xiic_deinit(i2c);
738 return ret;
739 }
740
741 if (pdata) {
742 /* add in known devices to the bus */
743 for (i = 0; i < pdata->num_devices; i++)
744 i2c_new_device(&i2c->adap, pdata->devices + i);
745 }
746
747 return 0;
748}
749
750static int xiic_i2c_remove(struct platform_device *pdev)
751{
752 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
753
754 /* remove adapter & data */
755 i2c_del_adapter(&i2c->adap);
756
757 xiic_deinit(i2c);
758
759 return 0;
760}
761
762#if defined(CONFIG_OF)
763static const struct of_device_id xiic_of_match[] = {
764 { .compatible = "xlnx,xps-iic-2.00.a", },
765 {},
766};
767MODULE_DEVICE_TABLE(of, xiic_of_match);
768#endif
769
770static struct platform_driver xiic_i2c_driver = {
771 .probe = xiic_i2c_probe,
772 .remove = xiic_i2c_remove,
773 .driver = {
774 .owner = THIS_MODULE,
775 .name = DRIVER_NAME,
776 .of_match_table = of_match_ptr(xiic_of_match),
777 },
778};
779
780module_platform_driver(xiic_i2c_driver);
781
782MODULE_AUTHOR("info@mocean-labs.com");
783MODULE_DESCRIPTION("Xilinx I2C bus driver");
784MODULE_LICENSE("GPL v2");
785MODULE_ALIAS("platform:"DRIVER_NAME);