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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Seung-Woo Kim <sw0312.kim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 * Joonyoung Shim <jy0922.shim@samsung.com>
8 *
9 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
10 */
11
12#include <drm/exynos_drm.h>
13#include <linux/clk.h>
14#include <linux/component.h>
15#include <linux/delay.h>
16#include <linux/gpio/consumer.h>
17#include <linux/hdmi.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/kernel.h>
23#include <linux/mfd/syscon.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_graph.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/regmap.h>
30#include <linux/regulator/consumer.h>
31#include <linux/wait.h>
32
33#include <sound/hdmi-codec.h>
34#include <media/cec-notifier.h>
35
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_bridge.h>
38#include <drm/drm_edid.h>
39#include <drm/drm_print.h>
40#include <drm/drm_probe_helper.h>
41#include <drm/drm_simple_kms_helper.h>
42
43#include "exynos_drm_crtc.h"
44#include "regs-hdmi.h"
45
46#define HOTPLUG_DEBOUNCE_MS 1100
47
48enum hdmi_type {
49 HDMI_TYPE13,
50 HDMI_TYPE14,
51 HDMI_TYPE_COUNT
52};
53
54#define HDMI_MAPPED_BASE 0xffff0000
55
56enum hdmi_mapped_regs {
57 HDMI_PHY_STATUS = HDMI_MAPPED_BASE,
58 HDMI_PHY_RSTOUT,
59 HDMI_ACR_CON,
60 HDMI_ACR_MCTS0,
61 HDMI_ACR_CTS0,
62 HDMI_ACR_N0
63};
64
65static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = {
66 { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 },
67 { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT },
68 { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON },
69 { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 },
70 { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 },
71 { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 },
72};
73
74static const char * const supply[] = {
75 "vdd",
76 "vdd_osc",
77 "vdd_pll",
78};
79
80struct hdmiphy_config {
81 int pixel_clock;
82 u8 conf[32];
83};
84
85struct hdmiphy_configs {
86 int count;
87 const struct hdmiphy_config *data;
88};
89
90struct string_array_spec {
91 int count;
92 const char * const *data;
93};
94
95#define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a }
96
97struct hdmi_driver_data {
98 unsigned int type;
99 unsigned int is_apb_phy:1;
100 unsigned int has_sysreg:1;
101 struct hdmiphy_configs phy_confs;
102 struct string_array_spec clk_gates;
103 /*
104 * Array of triplets (p_off, p_on, clock), where p_off and p_on are
105 * required parents of clock when HDMI-PHY is respectively off or on.
106 */
107 struct string_array_spec clk_muxes;
108};
109
110struct hdmi_audio {
111 struct platform_device *pdev;
112 struct hdmi_audio_infoframe infoframe;
113 struct hdmi_codec_params params;
114 bool mute;
115};
116
117struct hdmi_context {
118 struct drm_encoder encoder;
119 struct device *dev;
120 struct drm_device *drm_dev;
121 struct drm_connector connector;
122 bool dvi_mode;
123 struct delayed_work hotplug_work;
124 struct cec_notifier *notifier;
125 const struct hdmi_driver_data *drv_data;
126
127 void __iomem *regs;
128 void __iomem *regs_hdmiphy;
129 struct i2c_client *hdmiphy_port;
130 struct i2c_adapter *ddc_adpt;
131 struct gpio_desc *hpd_gpio;
132 int irq;
133 struct regmap *pmureg;
134 struct regmap *sysreg;
135 struct clk **clk_gates;
136 struct clk **clk_muxes;
137 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
138 struct regulator *reg_hdmi_en;
139 struct exynos_drm_clk phy_clk;
140 struct drm_bridge *bridge;
141
142 /* mutex protecting subsequent fields below */
143 struct mutex mutex;
144 struct hdmi_audio audio;
145 bool powered;
146};
147
148static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
149{
150 return container_of(e, struct hdmi_context, encoder);
151}
152
153static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c)
154{
155 return container_of(c, struct hdmi_context, connector);
156}
157
158static const struct hdmiphy_config hdmiphy_v13_configs[] = {
159 {
160 .pixel_clock = 27000000,
161 .conf = {
162 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
163 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
164 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
165 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
166 },
167 },
168 {
169 .pixel_clock = 27027000,
170 .conf = {
171 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
172 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
173 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
174 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
175 },
176 },
177 {
178 .pixel_clock = 74176000,
179 .conf = {
180 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
181 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
182 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
183 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
184 },
185 },
186 {
187 .pixel_clock = 74250000,
188 .conf = {
189 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
190 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
191 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
192 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
193 },
194 },
195 {
196 .pixel_clock = 148500000,
197 .conf = {
198 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
199 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
200 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
201 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
202 },
203 },
204};
205
206static const struct hdmiphy_config hdmiphy_v14_configs[] = {
207 {
208 .pixel_clock = 25200000,
209 .conf = {
210 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
211 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
212 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
213 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
214 },
215 },
216 {
217 .pixel_clock = 27000000,
218 .conf = {
219 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
220 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
221 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
222 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
223 },
224 },
225 {
226 .pixel_clock = 27027000,
227 .conf = {
228 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
229 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
230 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
231 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
232 },
233 },
234 {
235 .pixel_clock = 36000000,
236 .conf = {
237 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
238 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
239 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
240 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
241 },
242 },
243 {
244 .pixel_clock = 40000000,
245 .conf = {
246 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
247 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
248 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
249 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
250 },
251 },
252 {
253 .pixel_clock = 65000000,
254 .conf = {
255 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
256 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
257 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
258 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
259 },
260 },
261 {
262 .pixel_clock = 71000000,
263 .conf = {
264 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
265 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
266 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
267 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
268 },
269 },
270 {
271 .pixel_clock = 73250000,
272 .conf = {
273 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
274 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
275 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
276 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
277 },
278 },
279 {
280 .pixel_clock = 74176000,
281 .conf = {
282 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
283 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
284 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
285 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
286 },
287 },
288 {
289 .pixel_clock = 74250000,
290 .conf = {
291 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
292 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
293 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
294 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
295 },
296 },
297 {
298 .pixel_clock = 83500000,
299 .conf = {
300 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
301 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
302 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
303 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
304 },
305 },
306 {
307 .pixel_clock = 85500000,
308 .conf = {
309 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08,
310 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80,
311 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
312 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
313 },
314 },
315 {
316 .pixel_clock = 106500000,
317 .conf = {
318 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
319 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
320 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
321 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
322 },
323 },
324 {
325 .pixel_clock = 108000000,
326 .conf = {
327 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
328 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
329 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
330 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
331 },
332 },
333 {
334 .pixel_clock = 115500000,
335 .conf = {
336 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
337 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
338 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
339 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
340 },
341 },
342 {
343 .pixel_clock = 119000000,
344 .conf = {
345 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
346 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
347 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
348 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
349 },
350 },
351 {
352 .pixel_clock = 146250000,
353 .conf = {
354 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
355 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
356 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
357 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
358 },
359 },
360 {
361 .pixel_clock = 148500000,
362 .conf = {
363 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
364 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
365 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
366 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
367 },
368 },
369};
370
371static const struct hdmiphy_config hdmiphy_5420_configs[] = {
372 {
373 .pixel_clock = 25200000,
374 .conf = {
375 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
376 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
377 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
378 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
379 },
380 },
381 {
382 .pixel_clock = 27000000,
383 .conf = {
384 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
385 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
386 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
387 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
388 },
389 },
390 {
391 .pixel_clock = 27027000,
392 .conf = {
393 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
394 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
395 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
396 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
397 },
398 },
399 {
400 .pixel_clock = 36000000,
401 .conf = {
402 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
403 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
404 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
405 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
406 },
407 },
408 {
409 .pixel_clock = 40000000,
410 .conf = {
411 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
412 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
413 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
414 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
415 },
416 },
417 {
418 .pixel_clock = 65000000,
419 .conf = {
420 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
421 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
422 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
423 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
424 },
425 },
426 {
427 .pixel_clock = 71000000,
428 .conf = {
429 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
430 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
431 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
432 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
433 },
434 },
435 {
436 .pixel_clock = 73250000,
437 .conf = {
438 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
439 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
440 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
441 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
442 },
443 },
444 {
445 .pixel_clock = 74176000,
446 .conf = {
447 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
448 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
449 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
450 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
451 },
452 },
453 {
454 .pixel_clock = 74250000,
455 .conf = {
456 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
457 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
458 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
459 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
460 },
461 },
462 {
463 .pixel_clock = 83500000,
464 .conf = {
465 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
466 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
467 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
468 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
469 },
470 },
471 {
472 .pixel_clock = 88750000,
473 .conf = {
474 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
475 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
476 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
477 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
478 },
479 },
480 {
481 .pixel_clock = 106500000,
482 .conf = {
483 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
484 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
485 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
486 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
487 },
488 },
489 {
490 .pixel_clock = 108000000,
491 .conf = {
492 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
493 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
494 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
495 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
496 },
497 },
498 {
499 .pixel_clock = 115500000,
500 .conf = {
501 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
502 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
503 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
504 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
505 },
506 },
507 {
508 .pixel_clock = 146250000,
509 .conf = {
510 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
511 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
512 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
513 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
514 },
515 },
516 {
517 .pixel_clock = 148500000,
518 .conf = {
519 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
520 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
521 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
522 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
523 },
524 },
525 {
526 .pixel_clock = 154000000,
527 .conf = {
528 0x01, 0xD1, 0x20, 0x01, 0x40, 0x30, 0x08, 0xCC,
529 0x8C, 0xE8, 0xC1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
530 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86,
531 0x54, 0x3F, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
532 },
533 },
534};
535
536static const struct hdmiphy_config hdmiphy_5433_configs[] = {
537 {
538 .pixel_clock = 27000000,
539 .conf = {
540 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
541 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
542 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
543 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
544 },
545 },
546 {
547 .pixel_clock = 27027000,
548 .conf = {
549 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
550 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
551 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
552 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
553 },
554 },
555 {
556 .pixel_clock = 40000000,
557 .conf = {
558 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02,
559 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
560 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
561 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
562 },
563 },
564 {
565 .pixel_clock = 50000000,
566 .conf = {
567 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3,
568 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
569 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
570 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
571 },
572 },
573 {
574 .pixel_clock = 65000000,
575 .conf = {
576 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6,
577 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
578 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
579 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
580 },
581 },
582 {
583 .pixel_clock = 74176000,
584 .conf = {
585 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42,
586 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
587 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
588 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
589 },
590 },
591 {
592 .pixel_clock = 74250000,
593 .conf = {
594 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2,
595 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
596 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
597 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
598 },
599 },
600 {
601 .pixel_clock = 108000000,
602 .conf = {
603 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02,
604 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
605 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
606 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
607 },
608 },
609 {
610 .pixel_clock = 148500000,
611 .conf = {
612 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1,
613 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
614 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
615 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
616 },
617 },
618 {
619 .pixel_clock = 297000000,
620 .conf = {
621 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
622 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
623 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
624 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
625 },
626 },
627};
628
629static const char * const hdmi_clk_gates4[] = {
630 "hdmi", "sclk_hdmi"
631};
632
633static const char * const hdmi_clk_muxes4[] = {
634 "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"
635};
636
637static const char * const hdmi_clk_gates5433[] = {
638 "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk"
639};
640
641static const char * const hdmi_clk_muxes5433[] = {
642 "oscclk", "tmds_clko", "tmds_clko_user",
643 "oscclk", "pixel_clko", "pixel_clko_user"
644};
645
646static const struct hdmi_driver_data exynos4210_hdmi_driver_data = {
647 .type = HDMI_TYPE13,
648 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs),
649 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
650 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
651};
652
653static const struct hdmi_driver_data exynos4212_hdmi_driver_data = {
654 .type = HDMI_TYPE14,
655 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs),
656 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
657 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
658};
659
660static const struct hdmi_driver_data exynos5420_hdmi_driver_data = {
661 .type = HDMI_TYPE14,
662 .is_apb_phy = 1,
663 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs),
664 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4),
665 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
666};
667
668static const struct hdmi_driver_data exynos5433_hdmi_driver_data = {
669 .type = HDMI_TYPE14,
670 .is_apb_phy = 1,
671 .has_sysreg = 1,
672 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs),
673 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433),
674 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433),
675};
676
677static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id)
678{
679 if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE)
680 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type];
681 return reg_id;
682}
683
684static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
685{
686 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id));
687}
688
689static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
690 u32 reg_id, u8 value)
691{
692 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id));
693}
694
695static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
696 int bytes, u32 val)
697{
698 reg_id = hdmi_map_reg(hdata, reg_id);
699
700 while (--bytes >= 0) {
701 writel(val & 0xff, hdata->regs + reg_id);
702 val >>= 8;
703 reg_id += 4;
704 }
705}
706
707static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id,
708 u8 *buf, int size)
709{
710 for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4)
711 writel(*buf++, hdata->regs + reg_id);
712}
713
714static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
715 u32 reg_id, u32 value, u32 mask)
716{
717 u32 old;
718
719 reg_id = hdmi_map_reg(hdata, reg_id);
720 old = readl(hdata->regs + reg_id);
721 value = (value & mask) | (old & ~mask);
722 writel(value, hdata->regs + reg_id);
723}
724
725static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
726 u32 reg_offset, const u8 *buf, u32 len)
727{
728 if ((reg_offset + len) > 32)
729 return -EINVAL;
730
731 if (hdata->hdmiphy_port) {
732 int ret;
733
734 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
735 if (ret == len)
736 return 0;
737 return ret;
738 } else {
739 int i;
740 for (i = 0; i < len; i++)
741 writel(buf[i], hdata->regs_hdmiphy +
742 ((reg_offset + i)<<2));
743 return 0;
744 }
745}
746
747static int hdmi_clk_enable_gates(struct hdmi_context *hdata)
748{
749 int i, ret;
750
751 for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) {
752 ret = clk_prepare_enable(hdata->clk_gates[i]);
753 if (!ret)
754 continue;
755
756 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n",
757 hdata->drv_data->clk_gates.data[i], ret);
758 while (i--)
759 clk_disable_unprepare(hdata->clk_gates[i]);
760 return ret;
761 }
762
763 return 0;
764}
765
766static void hdmi_clk_disable_gates(struct hdmi_context *hdata)
767{
768 int i = hdata->drv_data->clk_gates.count;
769
770 while (i--)
771 clk_disable_unprepare(hdata->clk_gates[i]);
772}
773
774static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy)
775{
776 struct device *dev = hdata->dev;
777 int ret = 0;
778 int i;
779
780 for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) {
781 struct clk **c = &hdata->clk_muxes[i];
782
783 ret = clk_set_parent(c[2], c[to_phy]);
784 if (!ret)
785 continue;
786
787 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n",
788 hdata->drv_data->clk_muxes.data[i + 2],
789 hdata->drv_data->clk_muxes.data[i + to_phy], ret);
790 }
791
792 return ret;
793}
794
795static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata)
796{
797 struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe;
798 u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];
799 int len;
800
801 len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf));
802 if (len < 0)
803 return len;
804
805 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC);
806 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len);
807
808 return 0;
809}
810
811static void hdmi_reg_infoframes(struct hdmi_context *hdata)
812{
813 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
814 union hdmi_infoframe frm;
815 u8 buf[25];
816 int ret;
817
818 if (hdata->dvi_mode) {
819 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
820 HDMI_AVI_CON_DO_NOT_TRANSMIT);
821 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
822 HDMI_VSI_CON_DO_NOT_TRANSMIT);
823 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
824 return;
825 }
826
827 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi,
828 &hdata->connector, m);
829 if (!ret)
830 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf));
831 if (ret > 0) {
832 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
833 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret);
834 } else {
835 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret);
836 }
837
838 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi,
839 &hdata->connector, m);
840 if (!ret)
841 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf,
842 sizeof(buf));
843 if (ret > 0) {
844 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
845 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3);
846 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
847 }
848
849 hdmi_audio_infoframe_apply(hdata);
850}
851
852static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
853 bool force)
854{
855 struct hdmi_context *hdata = connector_to_hdmi(connector);
856
857 if (gpiod_get_value(hdata->hpd_gpio))
858 return connector_status_connected;
859
860 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
861 return connector_status_disconnected;
862}
863
864static void hdmi_connector_destroy(struct drm_connector *connector)
865{
866 struct hdmi_context *hdata = connector_to_hdmi(connector);
867
868 cec_notifier_conn_unregister(hdata->notifier);
869
870 drm_connector_unregister(connector);
871 drm_connector_cleanup(connector);
872}
873
874static const struct drm_connector_funcs hdmi_connector_funcs = {
875 .fill_modes = drm_helper_probe_single_connector_modes,
876 .detect = hdmi_detect,
877 .destroy = hdmi_connector_destroy,
878 .reset = drm_atomic_helper_connector_reset,
879 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
880 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
881};
882
883static int hdmi_get_modes(struct drm_connector *connector)
884{
885 struct hdmi_context *hdata = connector_to_hdmi(connector);
886 const struct drm_display_info *info = &connector->display_info;
887 const struct drm_edid *drm_edid;
888 int ret;
889
890 if (!hdata->ddc_adpt)
891 goto no_edid;
892
893 drm_edid = drm_edid_read_ddc(connector, hdata->ddc_adpt);
894
895 ret = drm_edid_connector_update(connector, drm_edid);
896 if (ret)
897 return 0;
898
899 cec_notifier_set_phys_addr(hdata->notifier, info->source_physical_address);
900
901 if (!drm_edid)
902 goto no_edid;
903
904 hdata->dvi_mode = !info->is_hdmi;
905 DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n",
906 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
907 info->width_mm / 10, info->height_mm / 10);
908
909 ret = drm_edid_connector_add_modes(connector);
910
911 drm_edid_free(drm_edid);
912
913 return ret;
914
915no_edid:
916 return drm_add_modes_noedid(connector, 640, 480);
917}
918
919static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
920{
921 const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs;
922 int i;
923
924 for (i = 0; i < confs->count; i++)
925 if (confs->data[i].pixel_clock == pixel_clock)
926 return i;
927
928 DRM_DEV_DEBUG_KMS(hdata->dev, "Could not find phy config for %d\n",
929 pixel_clock);
930 return -EINVAL;
931}
932
933static enum drm_mode_status hdmi_mode_valid(struct drm_connector *connector,
934 struct drm_display_mode *mode)
935{
936 struct hdmi_context *hdata = connector_to_hdmi(connector);
937 int ret;
938
939 DRM_DEV_DEBUG_KMS(hdata->dev,
940 "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
941 mode->hdisplay, mode->vdisplay,
942 drm_mode_vrefresh(mode),
943 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
944 false, mode->clock * 1000);
945
946 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
947 if (ret < 0)
948 return MODE_BAD;
949
950 return MODE_OK;
951}
952
953static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
954 .get_modes = hdmi_get_modes,
955 .mode_valid = hdmi_mode_valid,
956};
957
958static int hdmi_create_connector(struct drm_encoder *encoder)
959{
960 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
961 struct drm_connector *connector = &hdata->connector;
962 struct cec_connector_info conn_info;
963 int ret;
964
965 connector->interlace_allowed = true;
966 connector->polled = DRM_CONNECTOR_POLL_HPD;
967
968 ret = drm_connector_init_with_ddc(hdata->drm_dev, connector,
969 &hdmi_connector_funcs,
970 DRM_MODE_CONNECTOR_HDMIA,
971 hdata->ddc_adpt);
972 if (ret) {
973 DRM_DEV_ERROR(hdata->dev,
974 "Failed to initialize connector with drm\n");
975 return ret;
976 }
977
978 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
979 drm_connector_attach_encoder(connector, encoder);
980
981 if (hdata->bridge)
982 ret = drm_bridge_attach(encoder, hdata->bridge, NULL, 0);
983
984 cec_fill_conn_info_from_drm(&conn_info, connector);
985
986 hdata->notifier = cec_notifier_conn_register(hdata->dev, NULL,
987 &conn_info);
988 if (!hdata->notifier) {
989 ret = -ENOMEM;
990 DRM_DEV_ERROR(hdata->dev, "Failed to allocate CEC notifier\n");
991 }
992
993 return ret;
994}
995
996static bool hdmi_mode_fixup(struct drm_encoder *encoder,
997 const struct drm_display_mode *mode,
998 struct drm_display_mode *adjusted_mode)
999{
1000 struct drm_device *dev = encoder->dev;
1001 struct drm_connector *connector;
1002 struct drm_display_mode *m;
1003 struct drm_connector_list_iter conn_iter;
1004 int mode_ok;
1005
1006 drm_mode_set_crtcinfo(adjusted_mode, 0);
1007
1008 drm_connector_list_iter_begin(dev, &conn_iter);
1009 drm_for_each_connector_iter(connector, &conn_iter) {
1010 if (connector->encoder == encoder)
1011 break;
1012 }
1013 if (connector)
1014 drm_connector_get(connector);
1015 drm_connector_list_iter_end(&conn_iter);
1016
1017 if (!connector)
1018 return true;
1019
1020 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
1021
1022 if (mode_ok == MODE_OK)
1023 goto cleanup;
1024
1025 /*
1026 * Find the most suitable mode and copy it to adjusted_mode.
1027 */
1028 list_for_each_entry(m, &connector->modes, head) {
1029 mode_ok = hdmi_mode_valid(connector, m);
1030
1031 if (mode_ok == MODE_OK) {
1032 DRM_INFO("desired mode doesn't exist so\n");
1033 DRM_INFO("use the most suitable mode among modes.\n");
1034
1035 DRM_DEV_DEBUG_KMS(dev->dev,
1036 "Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1037 m->hdisplay, m->vdisplay,
1038 drm_mode_vrefresh(m));
1039
1040 drm_mode_copy(adjusted_mode, m);
1041 break;
1042 }
1043 }
1044
1045cleanup:
1046 drm_connector_put(connector);
1047
1048 return true;
1049}
1050
1051static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)
1052{
1053 u32 n, cts;
1054
1055 cts = (freq % 9) ? 27000 : 30000;
1056 n = 128 * freq / (27000000 / cts);
1057
1058 hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n);
1059 hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts);
1060 hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts);
1061 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1062}
1063
1064static void hdmi_audio_config(struct hdmi_context *hdata)
1065{
1066 u32 bit_ch = 1;
1067 u32 data_num, val;
1068 int i;
1069
1070 switch (hdata->audio.params.sample_width) {
1071 case 20:
1072 data_num = 2;
1073 break;
1074 case 24:
1075 data_num = 3;
1076 break;
1077 default:
1078 data_num = 1;
1079 bit_ch = 0;
1080 break;
1081 }
1082
1083 hdmi_reg_acr(hdata, hdata->audio.params.sample_rate);
1084
1085 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1086 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1087 | HDMI_I2S_MUX_ENABLE);
1088
1089 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1090 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1091
1092 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1093 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1094 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1095
1096 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1097 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1098
1099 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1100 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1101 | HDMI_I2S_SEL_LRCK(6));
1102
1103 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3)
1104 | HDMI_I2S_SEL_SDATA0(4));
1105
1106 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1107 | HDMI_I2S_SEL_SDATA2(2));
1108
1109 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1110
1111 /* I2S_CON_1 & 2 */
1112 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1113 | HDMI_I2S_L_CH_LOW_POL);
1114 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1115 | HDMI_I2S_SET_BIT_CH(bit_ch)
1116 | HDMI_I2S_SET_SDATA_BIT(data_num)
1117 | HDMI_I2S_BASIC_FORMAT);
1118
1119 /* Configuration of the audio channel status registers */
1120 for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++)
1121 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i),
1122 hdata->audio.params.iec.status[i]);
1123
1124 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1125}
1126
1127static void hdmi_audio_control(struct hdmi_context *hdata)
1128{
1129 bool enable = !hdata->audio.mute;
1130
1131 if (hdata->dvi_mode)
1132 return;
1133
1134 hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ?
1135 HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN);
1136 hdmi_reg_writemask(hdata, HDMI_CON_0, enable ?
1137 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1138}
1139
1140static void hdmi_start(struct hdmi_context *hdata, bool start)
1141{
1142 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1143 u32 val = start ? HDMI_TG_EN : 0;
1144
1145 if (m->flags & DRM_MODE_FLAG_INTERLACE)
1146 val |= HDMI_FIELD_EN;
1147
1148 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1149 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1150}
1151
1152static void hdmi_conf_init(struct hdmi_context *hdata)
1153{
1154 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1155 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1156 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1157
1158 /* choose HDMI mode */
1159 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1160 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1161 /* apply video pre-amble and guard band in HDMI mode only */
1162 hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
1163 /* disable bluescreen */
1164 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1165
1166 if (hdata->dvi_mode) {
1167 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1168 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1169 hdmi_reg_writeb(hdata, HDMI_CON_2,
1170 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1171 }
1172
1173 if (hdata->drv_data->type == HDMI_TYPE13) {
1174 /* choose bluescreen (fecal) color */
1175 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1176 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1177 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1178
1179 /* enable AVI packet every vsync, fixes purple line problem */
1180 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1181 /* force RGB, look to CEA-861-D, table 7 for more detail */
1182 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1183 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1184
1185 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1186 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1187 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1188 } else {
1189 hdmi_reg_infoframes(hdata);
1190
1191 /* enable AVI packet every vsync, fixes purple line problem */
1192 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1193 }
1194}
1195
1196static void hdmiphy_wait_for_pll(struct hdmi_context *hdata)
1197{
1198 int tries;
1199
1200 for (tries = 0; tries < 10; ++tries) {
1201 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS);
1202
1203 if (val & HDMI_PHY_STATUS_READY) {
1204 DRM_DEV_DEBUG_KMS(hdata->dev,
1205 "PLL stabilized after %d tries\n",
1206 tries);
1207 return;
1208 }
1209 usleep_range(10, 20);
1210 }
1211
1212 DRM_DEV_ERROR(hdata->dev, "PLL could not reach steady state\n");
1213}
1214
1215static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1216{
1217 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1218 unsigned int val;
1219
1220 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1221 hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
1222 (m->htotal << 12) | m->vtotal);
1223
1224 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1225 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
1226
1227 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1228 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
1229
1230 val = (m->hsync_start - m->hdisplay - 2);
1231 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1232 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1233 hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
1234
1235 /*
1236 * Quirk requirement for exynos HDMI IP design,
1237 * 2 pixels less than the actual calculation for hsync_start
1238 * and end.
1239 */
1240
1241 /* Following values & calculations differ for different type of modes */
1242 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1243 val = ((m->vsync_end - m->vdisplay) / 2);
1244 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1245 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1246
1247 val = m->vtotal / 2;
1248 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1249 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1250
1251 val = (m->vtotal +
1252 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1253 val |= m->vtotal << 11;
1254 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
1255
1256 val = ((m->vtotal / 2) + 7);
1257 val |= ((m->vtotal / 2) + 2) << 12;
1258 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
1259
1260 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1261 val |= ((m->htotal / 2) +
1262 (m->hsync_start - m->hdisplay)) << 12;
1263 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
1264
1265 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1266 (m->vtotal - m->vdisplay) / 2);
1267 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1268
1269 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
1270 } else {
1271 val = m->vtotal;
1272 val |= (m->vtotal - m->vdisplay) << 11;
1273 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1274
1275 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
1276
1277 val = (m->vsync_end - m->vdisplay);
1278 val |= ((m->vsync_start - m->vdisplay) << 12);
1279 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1280
1281 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
1282 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
1283 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1284 m->vtotal - m->vdisplay);
1285 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1286 }
1287
1288 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1289 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1290 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1291 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1292}
1293
1294static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1295{
1296 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1297 struct drm_display_mode *am =
1298 &hdata->encoder.crtc->state->adjusted_mode;
1299 int hquirk = 0;
1300
1301 /*
1302 * In case video mode coming from CRTC differs from requested one HDMI
1303 * sometimes is able to almost properly perform conversion - only
1304 * first line is distorted.
1305 */
1306 if ((m->vdisplay != am->vdisplay) &&
1307 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366))
1308 hquirk = 258;
1309
1310 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1311 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
1312 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
1313 hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
1314 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1315 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
1316 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1317 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
1318 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1319
1320 /*
1321 * Quirk requirement for exynos 5 HDMI IP design,
1322 * 2 pixels less than the actual calculation for hsync_start
1323 * and end.
1324 */
1325
1326 /* Following values & calculations differ for different type of modes */
1327 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1328 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1329 (m->vsync_end - m->vdisplay) / 2);
1330 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1331 (m->vsync_start - m->vdisplay) / 2);
1332 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
1333 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1334 (m->vtotal - m->vdisplay) / 2);
1335 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
1336 m->vtotal - m->vdisplay / 2);
1337 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
1338 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
1339 (m->vtotal / 2) + 7);
1340 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
1341 (m->vtotal / 2) + 2);
1342 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
1343 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1344 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
1345 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1346 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1347 (m->vtotal - m->vdisplay) / 2);
1348 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1349 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
1350 m->vtotal - m->vdisplay / 2);
1351 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
1352 (m->vtotal / 2) + 1);
1353 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
1354 (m->vtotal / 2) + 1);
1355 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
1356 (m->vtotal / 2) + 1);
1357 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
1358 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
1359 } else {
1360 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1361 m->vsync_end - m->vdisplay);
1362 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1363 m->vsync_start - m->vdisplay);
1364 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
1365 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1366 m->vtotal - m->vdisplay);
1367 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
1368 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
1369 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
1370 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
1371 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
1372 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
1373 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1374 m->vtotal - m->vdisplay);
1375 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1376 }
1377
1378 hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
1379 m->hsync_start - m->hdisplay - 2);
1380 hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
1381 m->hsync_end - m->hdisplay - 2);
1382 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
1383 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
1384 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
1385 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
1386 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
1387 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
1388 hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
1389 hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
1390 hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
1391 hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
1392 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
1393 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
1394 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
1395 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
1396 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
1397 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
1398 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
1399 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
1400
1401 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1402 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2,
1403 m->htotal - m->hdisplay - hquirk);
1404 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk);
1405 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1406 if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1407 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
1408}
1409
1410static void hdmi_mode_apply(struct hdmi_context *hdata)
1411{
1412 if (hdata->drv_data->type == HDMI_TYPE13)
1413 hdmi_v13_mode_apply(hdata);
1414 else
1415 hdmi_v14_mode_apply(hdata);
1416
1417 hdmi_start(hdata, true);
1418}
1419
1420static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1421{
1422 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1);
1423 usleep_range(10000, 12000);
1424 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1);
1425 usleep_range(10000, 12000);
1426 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
1427 usleep_range(10000, 12000);
1428 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
1429 usleep_range(10000, 12000);
1430}
1431
1432static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
1433{
1434 u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
1435
1436 if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1437 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
1438}
1439
1440static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1441{
1442 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1443 int ret;
1444 const u8 *phy_conf;
1445
1446 ret = hdmi_find_phy_conf(hdata, m->clock * 1000);
1447 if (ret < 0) {
1448 DRM_DEV_ERROR(hdata->dev, "failed to find hdmiphy conf\n");
1449 return;
1450 }
1451 phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
1452
1453 hdmi_clk_set_parents(hdata, false);
1454
1455 hdmiphy_conf_reset(hdata);
1456
1457 hdmiphy_enable_mode_set(hdata, true);
1458 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
1459 if (ret) {
1460 DRM_DEV_ERROR(hdata->dev, "failed to configure hdmiphy\n");
1461 return;
1462 }
1463 hdmiphy_enable_mode_set(hdata, false);
1464 hdmi_clk_set_parents(hdata, true);
1465 usleep_range(10000, 12000);
1466 hdmiphy_wait_for_pll(hdata);
1467}
1468
1469/* Should be called with hdata->mutex mutex held */
1470static void hdmi_conf_apply(struct hdmi_context *hdata)
1471{
1472 hdmi_start(hdata, false);
1473 hdmi_conf_init(hdata);
1474 hdmi_audio_config(hdata);
1475 hdmi_mode_apply(hdata);
1476 hdmi_audio_control(hdata);
1477}
1478
1479static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
1480{
1481 if (!hdata->sysreg)
1482 return;
1483
1484 regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY,
1485 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
1486}
1487
1488/* Should be called with hdata->mutex mutex held. */
1489static void hdmiphy_enable(struct hdmi_context *hdata)
1490{
1491 int ret;
1492
1493 if (hdata->powered)
1494 return;
1495
1496 ret = pm_runtime_resume_and_get(hdata->dev);
1497 if (ret < 0) {
1498 dev_err(hdata->dev, "failed to enable HDMIPHY device.\n");
1499 return;
1500 }
1501
1502 if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk))
1503 DRM_DEV_DEBUG_KMS(hdata->dev,
1504 "failed to enable regulator bulk\n");
1505
1506 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1507 PMU_HDMI_PHY_ENABLE_BIT, 1);
1508
1509 hdmi_set_refclk(hdata, true);
1510
1511 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
1512
1513 hdmiphy_conf_apply(hdata);
1514
1515 hdata->powered = true;
1516}
1517
1518/* Should be called with hdata->mutex mutex held. */
1519static void hdmiphy_disable(struct hdmi_context *hdata)
1520{
1521 if (!hdata->powered)
1522 return;
1523
1524 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
1525
1526 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
1527
1528 hdmi_set_refclk(hdata, false);
1529
1530 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1531 PMU_HDMI_PHY_ENABLE_BIT, 0);
1532
1533 regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
1534
1535 pm_runtime_put_sync(hdata->dev);
1536
1537 hdata->powered = false;
1538}
1539
1540static void hdmi_enable(struct drm_encoder *encoder)
1541{
1542 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1543
1544 mutex_lock(&hdata->mutex);
1545
1546 hdmiphy_enable(hdata);
1547 hdmi_conf_apply(hdata);
1548
1549 mutex_unlock(&hdata->mutex);
1550}
1551
1552static void hdmi_disable(struct drm_encoder *encoder)
1553{
1554 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1555
1556 mutex_lock(&hdata->mutex);
1557
1558 if (hdata->powered) {
1559 /*
1560 * The SFRs of VP and Mixer are updated by Vertical Sync of
1561 * Timing generator which is a part of HDMI so the sequence
1562 * to disable TV Subsystem should be as following,
1563 * VP -> Mixer -> HDMI
1564 *
1565 * To achieve such sequence HDMI is disabled together with
1566 * HDMI PHY, via pipe clock callback.
1567 */
1568 mutex_unlock(&hdata->mutex);
1569 cancel_delayed_work(&hdata->hotplug_work);
1570 if (hdata->notifier)
1571 cec_notifier_phys_addr_invalidate(hdata->notifier);
1572 return;
1573 }
1574
1575 mutex_unlock(&hdata->mutex);
1576}
1577
1578static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
1579 .mode_fixup = hdmi_mode_fixup,
1580 .enable = hdmi_enable,
1581 .disable = hdmi_disable,
1582};
1583
1584static void hdmi_audio_shutdown(struct device *dev, void *data)
1585{
1586 struct hdmi_context *hdata = dev_get_drvdata(dev);
1587
1588 mutex_lock(&hdata->mutex);
1589
1590 hdata->audio.mute = true;
1591
1592 if (hdata->powered)
1593 hdmi_audio_control(hdata);
1594
1595 mutex_unlock(&hdata->mutex);
1596}
1597
1598static int hdmi_audio_hw_params(struct device *dev, void *data,
1599 struct hdmi_codec_daifmt *daifmt,
1600 struct hdmi_codec_params *params)
1601{
1602 struct hdmi_context *hdata = dev_get_drvdata(dev);
1603
1604 if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv ||
1605 daifmt->frame_clk_inv || daifmt->bit_clk_provider ||
1606 daifmt->frame_clk_provider) {
1607 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1608 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1609 daifmt->bit_clk_provider,
1610 daifmt->frame_clk_provider);
1611 return -EINVAL;
1612 }
1613
1614 mutex_lock(&hdata->mutex);
1615
1616 hdata->audio.params = *params;
1617
1618 if (hdata->powered) {
1619 hdmi_audio_config(hdata);
1620 hdmi_audio_infoframe_apply(hdata);
1621 }
1622
1623 mutex_unlock(&hdata->mutex);
1624
1625 return 0;
1626}
1627
1628static int hdmi_audio_mute(struct device *dev, void *data,
1629 bool mute, int direction)
1630{
1631 struct hdmi_context *hdata = dev_get_drvdata(dev);
1632
1633 mutex_lock(&hdata->mutex);
1634
1635 hdata->audio.mute = mute;
1636
1637 if (hdata->powered)
1638 hdmi_audio_control(hdata);
1639
1640 mutex_unlock(&hdata->mutex);
1641
1642 return 0;
1643}
1644
1645static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
1646 size_t len)
1647{
1648 struct hdmi_context *hdata = dev_get_drvdata(dev);
1649 struct drm_connector *connector = &hdata->connector;
1650
1651 mutex_lock(&connector->eld_mutex);
1652 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1653 mutex_unlock(&connector->eld_mutex);
1654
1655 return 0;
1656}
1657
1658static const struct hdmi_codec_ops audio_codec_ops = {
1659 .hw_params = hdmi_audio_hw_params,
1660 .audio_shutdown = hdmi_audio_shutdown,
1661 .mute_stream = hdmi_audio_mute,
1662 .get_eld = hdmi_audio_get_eld,
1663 .no_capture_mute = 1,
1664};
1665
1666static int hdmi_register_audio_device(struct hdmi_context *hdata)
1667{
1668 struct hdmi_codec_pdata codec_data = {
1669 .ops = &audio_codec_ops,
1670 .max_i2s_channels = 6,
1671 .i2s = 1,
1672 };
1673
1674 hdata->audio.pdev = platform_device_register_data(
1675 hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1676 &codec_data, sizeof(codec_data));
1677
1678 return PTR_ERR_OR_ZERO(hdata->audio.pdev);
1679}
1680
1681static void hdmi_hotplug_work_func(struct work_struct *work)
1682{
1683 struct hdmi_context *hdata;
1684
1685 hdata = container_of(work, struct hdmi_context, hotplug_work.work);
1686
1687 if (hdata->drm_dev)
1688 drm_helper_hpd_irq_event(hdata->drm_dev);
1689}
1690
1691static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1692{
1693 struct hdmi_context *hdata = arg;
1694
1695 mod_delayed_work(system_wq, &hdata->hotplug_work,
1696 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
1697
1698 return IRQ_HANDLED;
1699}
1700
1701static int hdmi_clks_get(struct hdmi_context *hdata,
1702 const struct string_array_spec *names,
1703 struct clk **clks)
1704{
1705 struct device *dev = hdata->dev;
1706 int i;
1707
1708 for (i = 0; i < names->count; ++i) {
1709 struct clk *clk = devm_clk_get(dev, names->data[i]);
1710
1711 if (IS_ERR(clk)) {
1712 int ret = PTR_ERR(clk);
1713
1714 dev_err(dev, "Cannot get clock %s, %d\n",
1715 names->data[i], ret);
1716
1717 return ret;
1718 }
1719
1720 clks[i] = clk;
1721 }
1722
1723 return 0;
1724}
1725
1726static int hdmi_clk_init(struct hdmi_context *hdata)
1727{
1728 const struct hdmi_driver_data *drv_data = hdata->drv_data;
1729 int count = drv_data->clk_gates.count + drv_data->clk_muxes.count;
1730 struct device *dev = hdata->dev;
1731 struct clk **clks;
1732 int ret;
1733
1734 if (!count)
1735 return 0;
1736
1737 clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL);
1738 if (!clks)
1739 return -ENOMEM;
1740
1741 hdata->clk_gates = clks;
1742 hdata->clk_muxes = clks + drv_data->clk_gates.count;
1743
1744 ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates);
1745 if (ret)
1746 return ret;
1747
1748 return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes);
1749}
1750
1751
1752static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
1753{
1754 struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
1755 phy_clk);
1756 mutex_lock(&hdata->mutex);
1757
1758 if (enable)
1759 hdmiphy_enable(hdata);
1760 else
1761 hdmiphy_disable(hdata);
1762
1763 mutex_unlock(&hdata->mutex);
1764}
1765
1766static int hdmi_bridge_init(struct hdmi_context *hdata)
1767{
1768 struct device *dev = hdata->dev;
1769 struct device_node *ep, *np;
1770
1771 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
1772 if (!ep)
1773 return 0;
1774
1775 np = of_graph_get_remote_port_parent(ep);
1776 of_node_put(ep);
1777 if (!np) {
1778 DRM_DEV_ERROR(dev, "failed to get remote port parent");
1779 return -EINVAL;
1780 }
1781
1782 hdata->bridge = of_drm_find_bridge(np);
1783 of_node_put(np);
1784
1785 if (!hdata->bridge)
1786 return -EPROBE_DEFER;
1787
1788 return 0;
1789}
1790
1791static int hdmi_resources_init(struct hdmi_context *hdata)
1792{
1793 struct device *dev = hdata->dev;
1794 int i, ret;
1795
1796 DRM_DEV_DEBUG_KMS(dev, "HDMI resource init\n");
1797
1798 hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN);
1799 if (IS_ERR(hdata->hpd_gpio)) {
1800 DRM_DEV_ERROR(dev, "cannot get hpd gpio property\n");
1801 return PTR_ERR(hdata->hpd_gpio);
1802 }
1803
1804 hdata->irq = gpiod_to_irq(hdata->hpd_gpio);
1805 if (hdata->irq < 0) {
1806 DRM_DEV_ERROR(dev, "failed to get GPIO irq\n");
1807 return hdata->irq;
1808 }
1809
1810 ret = hdmi_clk_init(hdata);
1811 if (ret)
1812 return ret;
1813
1814 ret = hdmi_clk_set_parents(hdata, false);
1815 if (ret)
1816 return ret;
1817
1818 for (i = 0; i < ARRAY_SIZE(supply); ++i)
1819 hdata->regul_bulk[i].supply = supply[i];
1820
1821 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk);
1822 if (ret)
1823 return dev_err_probe(dev, ret, "failed to get regulators\n");
1824
1825 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1826
1827 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV)
1828 if (IS_ERR(hdata->reg_hdmi_en))
1829 return PTR_ERR(hdata->reg_hdmi_en);
1830
1831 return hdmi_bridge_init(hdata);
1832}
1833
1834static const struct of_device_id hdmi_match_types[] = {
1835 {
1836 .compatible = "samsung,exynos4210-hdmi",
1837 .data = &exynos4210_hdmi_driver_data,
1838 }, {
1839 .compatible = "samsung,exynos4212-hdmi",
1840 .data = &exynos4212_hdmi_driver_data,
1841 }, {
1842 .compatible = "samsung,exynos5420-hdmi",
1843 .data = &exynos5420_hdmi_driver_data,
1844 }, {
1845 .compatible = "samsung,exynos5433-hdmi",
1846 .data = &exynos5433_hdmi_driver_data,
1847 }, {
1848 /* end node */
1849 }
1850};
1851MODULE_DEVICE_TABLE (of, hdmi_match_types);
1852
1853static int hdmi_bind(struct device *dev, struct device *master, void *data)
1854{
1855 struct drm_device *drm_dev = data;
1856 struct hdmi_context *hdata = dev_get_drvdata(dev);
1857 struct drm_encoder *encoder = &hdata->encoder;
1858 struct exynos_drm_crtc *crtc;
1859 int ret;
1860
1861 hdata->drm_dev = drm_dev;
1862
1863 hdata->phy_clk.enable = hdmiphy_clk_enable;
1864
1865 drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
1866
1867 drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs);
1868
1869 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI);
1870 if (ret < 0)
1871 return ret;
1872
1873 crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI);
1874 if (IS_ERR(crtc))
1875 return PTR_ERR(crtc);
1876 crtc->pipe_clk = &hdata->phy_clk;
1877
1878 ret = hdmi_create_connector(encoder);
1879 if (ret) {
1880 DRM_DEV_ERROR(dev, "failed to create connector ret = %d\n",
1881 ret);
1882 drm_encoder_cleanup(encoder);
1883 return ret;
1884 }
1885
1886 return 0;
1887}
1888
1889static void hdmi_unbind(struct device *dev, struct device *master, void *data)
1890{
1891}
1892
1893static const struct component_ops hdmi_component_ops = {
1894 .bind = hdmi_bind,
1895 .unbind = hdmi_unbind,
1896};
1897
1898static int hdmi_get_ddc_adapter(struct hdmi_context *hdata)
1899{
1900 const char *compatible_str = "samsung,exynos4210-hdmiddc";
1901 struct device_node *np;
1902 struct i2c_adapter *adpt;
1903
1904 np = of_find_compatible_node(NULL, NULL, compatible_str);
1905 if (np)
1906 np = of_get_next_parent(np);
1907 else
1908 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0);
1909
1910 if (!np) {
1911 DRM_DEV_ERROR(hdata->dev,
1912 "Failed to find ddc node in device tree\n");
1913 return -ENODEV;
1914 }
1915
1916 adpt = of_find_i2c_adapter_by_node(np);
1917 of_node_put(np);
1918
1919 if (!adpt) {
1920 DRM_INFO("Failed to get ddc i2c adapter by node\n");
1921 return -EPROBE_DEFER;
1922 }
1923
1924 hdata->ddc_adpt = adpt;
1925
1926 return 0;
1927}
1928
1929static int hdmi_get_phy_io(struct hdmi_context *hdata)
1930{
1931 const char *compatible_str = "samsung,exynos4212-hdmiphy";
1932 struct device_node *np __free(device_node) =
1933 of_find_compatible_node(NULL, NULL, compatible_str);
1934
1935 if (!np) {
1936 np = of_parse_phandle(hdata->dev->of_node, "phy", 0);
1937 if (!np) {
1938 DRM_DEV_ERROR(hdata->dev,
1939 "Failed to find hdmiphy node in device tree\n");
1940 return -ENODEV;
1941 }
1942 }
1943
1944 if (hdata->drv_data->is_apb_phy) {
1945 hdata->regs_hdmiphy = of_iomap(np, 0);
1946 if (!hdata->regs_hdmiphy) {
1947 DRM_DEV_ERROR(hdata->dev,
1948 "failed to ioremap hdmi phy\n");
1949 return -ENOMEM;
1950 }
1951 } else {
1952 hdata->hdmiphy_port = of_find_i2c_device_by_node(np);
1953 if (!hdata->hdmiphy_port) {
1954 DRM_INFO("Failed to get hdmi phy i2c client\n");
1955 return -EPROBE_DEFER;
1956 }
1957 }
1958
1959 return 0;
1960}
1961
1962static int hdmi_probe(struct platform_device *pdev)
1963{
1964 struct hdmi_audio_infoframe *audio_infoframe;
1965 struct device *dev = &pdev->dev;
1966 struct hdmi_context *hdata;
1967 int ret;
1968
1969 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
1970 if (!hdata)
1971 return -ENOMEM;
1972
1973 hdata->drv_data = of_device_get_match_data(dev);
1974
1975 platform_set_drvdata(pdev, hdata);
1976
1977 hdata->dev = dev;
1978
1979 mutex_init(&hdata->mutex);
1980
1981 ret = hdmi_resources_init(hdata);
1982 if (ret) {
1983 if (ret != -EPROBE_DEFER)
1984 DRM_DEV_ERROR(dev, "hdmi_resources_init failed\n");
1985 return ret;
1986 }
1987
1988 hdata->regs = devm_platform_ioremap_resource(pdev, 0);
1989 if (IS_ERR(hdata->regs)) {
1990 ret = PTR_ERR(hdata->regs);
1991 return ret;
1992 }
1993
1994 ret = hdmi_get_ddc_adapter(hdata);
1995 if (ret)
1996 return ret;
1997
1998 ret = hdmi_get_phy_io(hdata);
1999 if (ret)
2000 goto err_ddc;
2001
2002 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2003
2004 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2005 hdmi_irq_thread, IRQF_TRIGGER_RISING |
2006 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2007 "hdmi", hdata);
2008 if (ret) {
2009 DRM_DEV_ERROR(dev, "failed to register hdmi interrupt\n");
2010 goto err_hdmiphy;
2011 }
2012
2013 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2014 "samsung,syscon-phandle");
2015 if (IS_ERR(hdata->pmureg)) {
2016 DRM_DEV_ERROR(dev, "syscon regmap lookup failed.\n");
2017 ret = -EPROBE_DEFER;
2018 goto err_hdmiphy;
2019 }
2020
2021 if (hdata->drv_data->has_sysreg) {
2022 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
2023 "samsung,sysreg-phandle");
2024 if (IS_ERR(hdata->sysreg)) {
2025 DRM_DEV_ERROR(dev, "sysreg regmap lookup failed.\n");
2026 ret = -EPROBE_DEFER;
2027 goto err_hdmiphy;
2028 }
2029 }
2030
2031 if (!IS_ERR(hdata->reg_hdmi_en)) {
2032 ret = regulator_enable(hdata->reg_hdmi_en);
2033 if (ret) {
2034 DRM_DEV_ERROR(dev,
2035 "failed to enable hdmi-en regulator\n");
2036 goto err_hdmiphy;
2037 }
2038 }
2039
2040 pm_runtime_enable(dev);
2041
2042 audio_infoframe = &hdata->audio.infoframe;
2043 hdmi_audio_infoframe_init(audio_infoframe);
2044 audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
2045 audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
2046 audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
2047 audio_infoframe->channels = 2;
2048
2049 ret = hdmi_register_audio_device(hdata);
2050 if (ret)
2051 goto err_rpm_disable;
2052
2053 ret = component_add(&pdev->dev, &hdmi_component_ops);
2054 if (ret)
2055 goto err_unregister_audio;
2056
2057 return ret;
2058
2059err_unregister_audio:
2060 platform_device_unregister(hdata->audio.pdev);
2061
2062err_rpm_disable:
2063 pm_runtime_disable(dev);
2064 if (!IS_ERR(hdata->reg_hdmi_en))
2065 regulator_disable(hdata->reg_hdmi_en);
2066err_hdmiphy:
2067 if (hdata->hdmiphy_port)
2068 put_device(&hdata->hdmiphy_port->dev);
2069 if (hdata->regs_hdmiphy)
2070 iounmap(hdata->regs_hdmiphy);
2071err_ddc:
2072 put_device(&hdata->ddc_adpt->dev);
2073
2074 return ret;
2075}
2076
2077static void hdmi_remove(struct platform_device *pdev)
2078{
2079 struct hdmi_context *hdata = platform_get_drvdata(pdev);
2080
2081 cancel_delayed_work_sync(&hdata->hotplug_work);
2082
2083 component_del(&pdev->dev, &hdmi_component_ops);
2084 platform_device_unregister(hdata->audio.pdev);
2085
2086 pm_runtime_disable(&pdev->dev);
2087
2088 if (!IS_ERR(hdata->reg_hdmi_en))
2089 regulator_disable(hdata->reg_hdmi_en);
2090
2091 if (hdata->hdmiphy_port)
2092 put_device(&hdata->hdmiphy_port->dev);
2093
2094 if (hdata->regs_hdmiphy)
2095 iounmap(hdata->regs_hdmiphy);
2096
2097 put_device(&hdata->ddc_adpt->dev);
2098
2099 mutex_destroy(&hdata->mutex);
2100}
2101
2102static int __maybe_unused exynos_hdmi_suspend(struct device *dev)
2103{
2104 struct hdmi_context *hdata = dev_get_drvdata(dev);
2105
2106 hdmi_clk_disable_gates(hdata);
2107
2108 return 0;
2109}
2110
2111static int __maybe_unused exynos_hdmi_resume(struct device *dev)
2112{
2113 struct hdmi_context *hdata = dev_get_drvdata(dev);
2114 int ret;
2115
2116 ret = hdmi_clk_enable_gates(hdata);
2117 if (ret < 0)
2118 return ret;
2119
2120 return 0;
2121}
2122
2123static const struct dev_pm_ops exynos_hdmi_pm_ops = {
2124 SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL)
2125 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2126 pm_runtime_force_resume)
2127};
2128
2129struct platform_driver hdmi_driver = {
2130 .probe = hdmi_probe,
2131 .remove = hdmi_remove,
2132 .driver = {
2133 .name = "exynos-hdmi",
2134 .pm = &exynos_hdmi_pm_ops,
2135 .of_match_table = hdmi_match_types,
2136 },
2137};
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Authors:
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 *
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#include <drm/drmP.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_crtc_helper.h>
20
21#include "regs-hdmi.h"
22
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/wait.h>
26#include <linux/i2c.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/delay.h>
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
33#include <linux/regulator/consumer.h>
34#include <linux/io.h>
35#include <linux/of.h>
36#include <linux/i2c.h>
37#include <linux/of_gpio.h>
38#include <linux/hdmi.h>
39
40#include <drm/exynos_drm.h>
41
42#include "exynos_drm_drv.h"
43#include "exynos_mixer.h"
44
45#include <linux/gpio.h>
46#include <media/s5p_hdmi.h>
47
48#define get_hdmi_display(dev) platform_get_drvdata(to_platform_device(dev))
49#define ctx_from_connector(c) container_of(c, struct hdmi_context, connector)
50
51/* AVI header and aspect ratio */
52#define HDMI_AVI_VERSION 0x02
53#define HDMI_AVI_LENGTH 0x0D
54
55/* AUI header info */
56#define HDMI_AUI_VERSION 0x01
57#define HDMI_AUI_LENGTH 0x0A
58#define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
59#define AVI_4_3_CENTER_RATIO 0x9
60#define AVI_16_9_CENTER_RATIO 0xa
61
62enum hdmi_type {
63 HDMI_TYPE13,
64 HDMI_TYPE14,
65};
66
67struct hdmi_driver_data {
68 unsigned int type;
69 unsigned int is_apb_phy:1;
70};
71
72struct hdmi_resources {
73 struct clk *hdmi;
74 struct clk *sclk_hdmi;
75 struct clk *sclk_pixel;
76 struct clk *sclk_hdmiphy;
77 struct clk *hdmiphy;
78 struct clk *mout_hdmi;
79 struct regulator_bulk_data *regul_bulk;
80 int regul_count;
81};
82
83struct hdmi_tg_regs {
84 u8 cmd[1];
85 u8 h_fsz[2];
86 u8 hact_st[2];
87 u8 hact_sz[2];
88 u8 v_fsz[2];
89 u8 vsync[2];
90 u8 vsync2[2];
91 u8 vact_st[2];
92 u8 vact_sz[2];
93 u8 field_chg[2];
94 u8 vact_st2[2];
95 u8 vact_st3[2];
96 u8 vact_st4[2];
97 u8 vsync_top_hdmi[2];
98 u8 vsync_bot_hdmi[2];
99 u8 field_top_hdmi[2];
100 u8 field_bot_hdmi[2];
101 u8 tg_3d[1];
102};
103
104struct hdmi_v13_core_regs {
105 u8 h_blank[2];
106 u8 v_blank[3];
107 u8 h_v_line[3];
108 u8 vsync_pol[1];
109 u8 int_pro_mode[1];
110 u8 v_blank_f[3];
111 u8 h_sync_gen[3];
112 u8 v_sync_gen1[3];
113 u8 v_sync_gen2[3];
114 u8 v_sync_gen3[3];
115};
116
117struct hdmi_v14_core_regs {
118 u8 h_blank[2];
119 u8 v2_blank[2];
120 u8 v1_blank[2];
121 u8 v_line[2];
122 u8 h_line[2];
123 u8 hsync_pol[1];
124 u8 vsync_pol[1];
125 u8 int_pro_mode[1];
126 u8 v_blank_f0[2];
127 u8 v_blank_f1[2];
128 u8 h_sync_start[2];
129 u8 h_sync_end[2];
130 u8 v_sync_line_bef_2[2];
131 u8 v_sync_line_bef_1[2];
132 u8 v_sync_line_aft_2[2];
133 u8 v_sync_line_aft_1[2];
134 u8 v_sync_line_aft_pxl_2[2];
135 u8 v_sync_line_aft_pxl_1[2];
136 u8 v_blank_f2[2]; /* for 3D mode */
137 u8 v_blank_f3[2]; /* for 3D mode */
138 u8 v_blank_f4[2]; /* for 3D mode */
139 u8 v_blank_f5[2]; /* for 3D mode */
140 u8 v_sync_line_aft_3[2];
141 u8 v_sync_line_aft_4[2];
142 u8 v_sync_line_aft_5[2];
143 u8 v_sync_line_aft_6[2];
144 u8 v_sync_line_aft_pxl_3[2];
145 u8 v_sync_line_aft_pxl_4[2];
146 u8 v_sync_line_aft_pxl_5[2];
147 u8 v_sync_line_aft_pxl_6[2];
148 u8 vact_space_1[2];
149 u8 vact_space_2[2];
150 u8 vact_space_3[2];
151 u8 vact_space_4[2];
152 u8 vact_space_5[2];
153 u8 vact_space_6[2];
154};
155
156struct hdmi_v13_conf {
157 struct hdmi_v13_core_regs core;
158 struct hdmi_tg_regs tg;
159};
160
161struct hdmi_v14_conf {
162 struct hdmi_v14_core_regs core;
163 struct hdmi_tg_regs tg;
164};
165
166struct hdmi_conf_regs {
167 int pixel_clock;
168 int cea_video_id;
169 enum hdmi_picture_aspect aspect_ratio;
170 union {
171 struct hdmi_v13_conf v13_conf;
172 struct hdmi_v14_conf v14_conf;
173 } conf;
174};
175
176struct hdmi_context {
177 struct device *dev;
178 struct drm_device *drm_dev;
179 struct drm_connector connector;
180 struct drm_encoder *encoder;
181 bool hpd;
182 bool powered;
183 bool dvi_mode;
184 struct mutex hdmi_mutex;
185
186 void __iomem *regs;
187 int irq;
188
189 struct i2c_adapter *ddc_adpt;
190 struct i2c_client *hdmiphy_port;
191
192 /* current hdmiphy conf regs */
193 struct hdmi_conf_regs mode_conf;
194
195 struct hdmi_resources res;
196
197 int hpd_gpio;
198
199 enum hdmi_type type;
200};
201
202struct hdmiphy_config {
203 int pixel_clock;
204 u8 conf[32];
205};
206
207struct hdmi_driver_data exynos4212_hdmi_driver_data = {
208 .type = HDMI_TYPE14,
209};
210
211struct hdmi_driver_data exynos5_hdmi_driver_data = {
212 .type = HDMI_TYPE14,
213};
214
215/* list of phy config settings */
216static const struct hdmiphy_config hdmiphy_v13_configs[] = {
217 {
218 .pixel_clock = 27000000,
219 .conf = {
220 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
221 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
222 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
223 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
224 },
225 },
226 {
227 .pixel_clock = 27027000,
228 .conf = {
229 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
230 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
231 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
232 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
233 },
234 },
235 {
236 .pixel_clock = 74176000,
237 .conf = {
238 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
239 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
240 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
241 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
242 },
243 },
244 {
245 .pixel_clock = 74250000,
246 .conf = {
247 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
248 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
249 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
250 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
251 },
252 },
253 {
254 .pixel_clock = 148500000,
255 .conf = {
256 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
257 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
258 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
259 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
260 },
261 },
262};
263
264static const struct hdmiphy_config hdmiphy_v14_configs[] = {
265 {
266 .pixel_clock = 25200000,
267 .conf = {
268 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
269 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
270 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
271 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
272 },
273 },
274 {
275 .pixel_clock = 27000000,
276 .conf = {
277 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
278 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
279 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
280 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
281 },
282 },
283 {
284 .pixel_clock = 27027000,
285 .conf = {
286 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
287 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
288 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
289 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
290 },
291 },
292 {
293 .pixel_clock = 36000000,
294 .conf = {
295 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
296 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
297 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
298 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
299 },
300 },
301 {
302 .pixel_clock = 40000000,
303 .conf = {
304 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
305 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
306 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
307 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
308 },
309 },
310 {
311 .pixel_clock = 65000000,
312 .conf = {
313 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
314 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
315 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
316 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
317 },
318 },
319 {
320 .pixel_clock = 71000000,
321 .conf = {
322 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
323 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
324 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
325 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
326 },
327 },
328 {
329 .pixel_clock = 73250000,
330 .conf = {
331 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
332 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
333 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
334 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
335 },
336 },
337 {
338 .pixel_clock = 74176000,
339 .conf = {
340 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
341 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
342 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
343 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
344 },
345 },
346 {
347 .pixel_clock = 74250000,
348 .conf = {
349 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
350 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
351 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
352 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
353 },
354 },
355 {
356 .pixel_clock = 83500000,
357 .conf = {
358 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
359 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
360 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
361 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
362 },
363 },
364 {
365 .pixel_clock = 88750000,
366 .conf = {
367 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
368 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
369 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
370 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
371 },
372 },
373 {
374 .pixel_clock = 106500000,
375 .conf = {
376 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
377 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
378 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
379 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
380 },
381 },
382 {
383 .pixel_clock = 108000000,
384 .conf = {
385 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
386 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
387 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
388 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
389 },
390 },
391 {
392 .pixel_clock = 115500000,
393 .conf = {
394 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
395 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
396 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
397 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
398 },
399 },
400 {
401 .pixel_clock = 119000000,
402 .conf = {
403 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
404 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
405 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
406 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
407 },
408 },
409 {
410 .pixel_clock = 146250000,
411 .conf = {
412 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
413 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
414 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
415 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
416 },
417 },
418 {
419 .pixel_clock = 148500000,
420 .conf = {
421 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
422 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
423 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
424 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
425 },
426 },
427};
428
429static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
430{
431 return readl(hdata->regs + reg_id);
432}
433
434static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
435 u32 reg_id, u8 value)
436{
437 writeb(value, hdata->regs + reg_id);
438}
439
440static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
441 u32 reg_id, u32 value, u32 mask)
442{
443 u32 old = readl(hdata->regs + reg_id);
444 value = (value & mask) | (old & ~mask);
445 writel(value, hdata->regs + reg_id);
446}
447
448static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
449{
450#define DUMPREG(reg_id) \
451 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
452 readl(hdata->regs + reg_id))
453 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
454 DUMPREG(HDMI_INTC_FLAG);
455 DUMPREG(HDMI_INTC_CON);
456 DUMPREG(HDMI_HPD_STATUS);
457 DUMPREG(HDMI_V13_PHY_RSTOUT);
458 DUMPREG(HDMI_V13_PHY_VPLL);
459 DUMPREG(HDMI_V13_PHY_CMU);
460 DUMPREG(HDMI_V13_CORE_RSTOUT);
461
462 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
463 DUMPREG(HDMI_CON_0);
464 DUMPREG(HDMI_CON_1);
465 DUMPREG(HDMI_CON_2);
466 DUMPREG(HDMI_SYS_STATUS);
467 DUMPREG(HDMI_V13_PHY_STATUS);
468 DUMPREG(HDMI_STATUS_EN);
469 DUMPREG(HDMI_HPD);
470 DUMPREG(HDMI_MODE_SEL);
471 DUMPREG(HDMI_V13_HPD_GEN);
472 DUMPREG(HDMI_V13_DC_CONTROL);
473 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
474
475 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
476 DUMPREG(HDMI_H_BLANK_0);
477 DUMPREG(HDMI_H_BLANK_1);
478 DUMPREG(HDMI_V13_V_BLANK_0);
479 DUMPREG(HDMI_V13_V_BLANK_1);
480 DUMPREG(HDMI_V13_V_BLANK_2);
481 DUMPREG(HDMI_V13_H_V_LINE_0);
482 DUMPREG(HDMI_V13_H_V_LINE_1);
483 DUMPREG(HDMI_V13_H_V_LINE_2);
484 DUMPREG(HDMI_VSYNC_POL);
485 DUMPREG(HDMI_INT_PRO_MODE);
486 DUMPREG(HDMI_V13_V_BLANK_F_0);
487 DUMPREG(HDMI_V13_V_BLANK_F_1);
488 DUMPREG(HDMI_V13_V_BLANK_F_2);
489 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
490 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
491 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
492 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
493 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
494 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
495 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
496 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
497 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
498 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
499 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
500 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
501
502 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
503 DUMPREG(HDMI_TG_CMD);
504 DUMPREG(HDMI_TG_H_FSZ_L);
505 DUMPREG(HDMI_TG_H_FSZ_H);
506 DUMPREG(HDMI_TG_HACT_ST_L);
507 DUMPREG(HDMI_TG_HACT_ST_H);
508 DUMPREG(HDMI_TG_HACT_SZ_L);
509 DUMPREG(HDMI_TG_HACT_SZ_H);
510 DUMPREG(HDMI_TG_V_FSZ_L);
511 DUMPREG(HDMI_TG_V_FSZ_H);
512 DUMPREG(HDMI_TG_VSYNC_L);
513 DUMPREG(HDMI_TG_VSYNC_H);
514 DUMPREG(HDMI_TG_VSYNC2_L);
515 DUMPREG(HDMI_TG_VSYNC2_H);
516 DUMPREG(HDMI_TG_VACT_ST_L);
517 DUMPREG(HDMI_TG_VACT_ST_H);
518 DUMPREG(HDMI_TG_VACT_SZ_L);
519 DUMPREG(HDMI_TG_VACT_SZ_H);
520 DUMPREG(HDMI_TG_FIELD_CHG_L);
521 DUMPREG(HDMI_TG_FIELD_CHG_H);
522 DUMPREG(HDMI_TG_VACT_ST2_L);
523 DUMPREG(HDMI_TG_VACT_ST2_H);
524 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
525 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
526 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
527 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
528 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
529 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
530 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
531 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
532#undef DUMPREG
533}
534
535static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
536{
537 int i;
538
539#define DUMPREG(reg_id) \
540 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
541 readl(hdata->regs + reg_id))
542
543 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
544 DUMPREG(HDMI_INTC_CON);
545 DUMPREG(HDMI_INTC_FLAG);
546 DUMPREG(HDMI_HPD_STATUS);
547 DUMPREG(HDMI_INTC_CON_1);
548 DUMPREG(HDMI_INTC_FLAG_1);
549 DUMPREG(HDMI_PHY_STATUS_0);
550 DUMPREG(HDMI_PHY_STATUS_PLL);
551 DUMPREG(HDMI_PHY_CON_0);
552 DUMPREG(HDMI_PHY_RSTOUT);
553 DUMPREG(HDMI_PHY_VPLL);
554 DUMPREG(HDMI_PHY_CMU);
555 DUMPREG(HDMI_CORE_RSTOUT);
556
557 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
558 DUMPREG(HDMI_CON_0);
559 DUMPREG(HDMI_CON_1);
560 DUMPREG(HDMI_CON_2);
561 DUMPREG(HDMI_SYS_STATUS);
562 DUMPREG(HDMI_PHY_STATUS_0);
563 DUMPREG(HDMI_STATUS_EN);
564 DUMPREG(HDMI_HPD);
565 DUMPREG(HDMI_MODE_SEL);
566 DUMPREG(HDMI_ENC_EN);
567 DUMPREG(HDMI_DC_CONTROL);
568 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
569
570 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
571 DUMPREG(HDMI_H_BLANK_0);
572 DUMPREG(HDMI_H_BLANK_1);
573 DUMPREG(HDMI_V2_BLANK_0);
574 DUMPREG(HDMI_V2_BLANK_1);
575 DUMPREG(HDMI_V1_BLANK_0);
576 DUMPREG(HDMI_V1_BLANK_1);
577 DUMPREG(HDMI_V_LINE_0);
578 DUMPREG(HDMI_V_LINE_1);
579 DUMPREG(HDMI_H_LINE_0);
580 DUMPREG(HDMI_H_LINE_1);
581 DUMPREG(HDMI_HSYNC_POL);
582
583 DUMPREG(HDMI_VSYNC_POL);
584 DUMPREG(HDMI_INT_PRO_MODE);
585 DUMPREG(HDMI_V_BLANK_F0_0);
586 DUMPREG(HDMI_V_BLANK_F0_1);
587 DUMPREG(HDMI_V_BLANK_F1_0);
588 DUMPREG(HDMI_V_BLANK_F1_1);
589
590 DUMPREG(HDMI_H_SYNC_START_0);
591 DUMPREG(HDMI_H_SYNC_START_1);
592 DUMPREG(HDMI_H_SYNC_END_0);
593 DUMPREG(HDMI_H_SYNC_END_1);
594
595 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
596 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
597 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
598 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
599
600 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
601 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
602 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
603 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
604
605 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
606 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
607 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
608 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
609
610 DUMPREG(HDMI_V_BLANK_F2_0);
611 DUMPREG(HDMI_V_BLANK_F2_1);
612 DUMPREG(HDMI_V_BLANK_F3_0);
613 DUMPREG(HDMI_V_BLANK_F3_1);
614 DUMPREG(HDMI_V_BLANK_F4_0);
615 DUMPREG(HDMI_V_BLANK_F4_1);
616 DUMPREG(HDMI_V_BLANK_F5_0);
617 DUMPREG(HDMI_V_BLANK_F5_1);
618
619 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
620 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
621 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
622 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
623 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
624 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
625 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
626 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
627
628 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
629 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
630 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
631 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
632 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
633 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
634 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
635 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
636
637 DUMPREG(HDMI_VACT_SPACE_1_0);
638 DUMPREG(HDMI_VACT_SPACE_1_1);
639 DUMPREG(HDMI_VACT_SPACE_2_0);
640 DUMPREG(HDMI_VACT_SPACE_2_1);
641 DUMPREG(HDMI_VACT_SPACE_3_0);
642 DUMPREG(HDMI_VACT_SPACE_3_1);
643 DUMPREG(HDMI_VACT_SPACE_4_0);
644 DUMPREG(HDMI_VACT_SPACE_4_1);
645 DUMPREG(HDMI_VACT_SPACE_5_0);
646 DUMPREG(HDMI_VACT_SPACE_5_1);
647 DUMPREG(HDMI_VACT_SPACE_6_0);
648 DUMPREG(HDMI_VACT_SPACE_6_1);
649
650 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
651 DUMPREG(HDMI_TG_CMD);
652 DUMPREG(HDMI_TG_H_FSZ_L);
653 DUMPREG(HDMI_TG_H_FSZ_H);
654 DUMPREG(HDMI_TG_HACT_ST_L);
655 DUMPREG(HDMI_TG_HACT_ST_H);
656 DUMPREG(HDMI_TG_HACT_SZ_L);
657 DUMPREG(HDMI_TG_HACT_SZ_H);
658 DUMPREG(HDMI_TG_V_FSZ_L);
659 DUMPREG(HDMI_TG_V_FSZ_H);
660 DUMPREG(HDMI_TG_VSYNC_L);
661 DUMPREG(HDMI_TG_VSYNC_H);
662 DUMPREG(HDMI_TG_VSYNC2_L);
663 DUMPREG(HDMI_TG_VSYNC2_H);
664 DUMPREG(HDMI_TG_VACT_ST_L);
665 DUMPREG(HDMI_TG_VACT_ST_H);
666 DUMPREG(HDMI_TG_VACT_SZ_L);
667 DUMPREG(HDMI_TG_VACT_SZ_H);
668 DUMPREG(HDMI_TG_FIELD_CHG_L);
669 DUMPREG(HDMI_TG_FIELD_CHG_H);
670 DUMPREG(HDMI_TG_VACT_ST2_L);
671 DUMPREG(HDMI_TG_VACT_ST2_H);
672 DUMPREG(HDMI_TG_VACT_ST3_L);
673 DUMPREG(HDMI_TG_VACT_ST3_H);
674 DUMPREG(HDMI_TG_VACT_ST4_L);
675 DUMPREG(HDMI_TG_VACT_ST4_H);
676 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
677 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
678 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
679 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
680 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
681 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
682 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
683 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
684 DUMPREG(HDMI_TG_3D);
685
686 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
687 DUMPREG(HDMI_AVI_CON);
688 DUMPREG(HDMI_AVI_HEADER0);
689 DUMPREG(HDMI_AVI_HEADER1);
690 DUMPREG(HDMI_AVI_HEADER2);
691 DUMPREG(HDMI_AVI_CHECK_SUM);
692 DUMPREG(HDMI_VSI_CON);
693 DUMPREG(HDMI_VSI_HEADER0);
694 DUMPREG(HDMI_VSI_HEADER1);
695 DUMPREG(HDMI_VSI_HEADER2);
696 for (i = 0; i < 7; ++i)
697 DUMPREG(HDMI_VSI_DATA(i));
698
699#undef DUMPREG
700}
701
702static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
703{
704 if (hdata->type == HDMI_TYPE13)
705 hdmi_v13_regs_dump(hdata, prefix);
706 else
707 hdmi_v14_regs_dump(hdata, prefix);
708}
709
710static u8 hdmi_chksum(struct hdmi_context *hdata,
711 u32 start, u8 len, u32 hdr_sum)
712{
713 int i;
714
715 /* hdr_sum : header0 + header1 + header2
716 * start : start address of packet byte1
717 * len : packet bytes - 1 */
718 for (i = 0; i < len; ++i)
719 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
720
721 /* return 2's complement of 8 bit hdr_sum */
722 return (u8)(~(hdr_sum & 0xff) + 1);
723}
724
725static void hdmi_reg_infoframe(struct hdmi_context *hdata,
726 union hdmi_infoframe *infoframe)
727{
728 u32 hdr_sum;
729 u8 chksum;
730 u32 mod;
731 u32 vic;
732
733 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
734 if (hdata->dvi_mode) {
735 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
736 HDMI_VSI_CON_DO_NOT_TRANSMIT);
737 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
738 HDMI_AVI_CON_DO_NOT_TRANSMIT);
739 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
740 return;
741 }
742
743 switch (infoframe->any.type) {
744 case HDMI_INFOFRAME_TYPE_AVI:
745 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
746 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
747 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
748 infoframe->any.version);
749 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
750 hdr_sum = infoframe->any.type + infoframe->any.version +
751 infoframe->any.length;
752
753 /* Output format zero hardcoded ,RGB YBCR selection */
754 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
755 AVI_ACTIVE_FORMAT_VALID |
756 AVI_UNDERSCANNED_DISPLAY_VALID);
757
758 /*
759 * Set the aspect ratio as per the mode, mentioned in
760 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
761 */
762 switch (hdata->mode_conf.aspect_ratio) {
763 case HDMI_PICTURE_ASPECT_4_3:
764 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
765 hdata->mode_conf.aspect_ratio |
766 AVI_4_3_CENTER_RATIO);
767 break;
768 case HDMI_PICTURE_ASPECT_16_9:
769 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
770 hdata->mode_conf.aspect_ratio |
771 AVI_16_9_CENTER_RATIO);
772 break;
773 case HDMI_PICTURE_ASPECT_NONE:
774 default:
775 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
776 hdata->mode_conf.aspect_ratio |
777 AVI_SAME_AS_PIC_ASPECT_RATIO);
778 break;
779 }
780
781 vic = hdata->mode_conf.cea_video_id;
782 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
783
784 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
785 infoframe->any.length, hdr_sum);
786 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
787 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
788 break;
789 case HDMI_INFOFRAME_TYPE_AUDIO:
790 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
791 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
792 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
793 infoframe->any.version);
794 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
795 hdr_sum = infoframe->any.type + infoframe->any.version +
796 infoframe->any.length;
797 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
798 infoframe->any.length, hdr_sum);
799 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
800 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
801 break;
802 default:
803 break;
804 }
805}
806
807static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
808 bool force)
809{
810 struct hdmi_context *hdata = ctx_from_connector(connector);
811
812 return hdata->hpd ? connector_status_connected :
813 connector_status_disconnected;
814}
815
816static void hdmi_connector_destroy(struct drm_connector *connector)
817{
818}
819
820static struct drm_connector_funcs hdmi_connector_funcs = {
821 .dpms = drm_helper_connector_dpms,
822 .fill_modes = drm_helper_probe_single_connector_modes,
823 .detect = hdmi_detect,
824 .destroy = hdmi_connector_destroy,
825};
826
827static int hdmi_get_modes(struct drm_connector *connector)
828{
829 struct hdmi_context *hdata = ctx_from_connector(connector);
830 struct edid *edid;
831
832 if (!hdata->ddc_adpt)
833 return -ENODEV;
834
835 edid = drm_get_edid(connector, hdata->ddc_adpt);
836 if (!edid)
837 return -ENODEV;
838
839 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
840 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
841 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
842 edid->width_cm, edid->height_cm);
843
844 drm_mode_connector_update_edid_property(connector, edid);
845
846 return drm_add_edid_modes(connector, edid);
847}
848
849static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
850{
851 const struct hdmiphy_config *confs;
852 int count, i;
853
854 if (hdata->type == HDMI_TYPE13) {
855 confs = hdmiphy_v13_configs;
856 count = ARRAY_SIZE(hdmiphy_v13_configs);
857 } else if (hdata->type == HDMI_TYPE14) {
858 confs = hdmiphy_v14_configs;
859 count = ARRAY_SIZE(hdmiphy_v14_configs);
860 } else
861 return -EINVAL;
862
863 for (i = 0; i < count; i++)
864 if (confs[i].pixel_clock == pixel_clock)
865 return i;
866
867 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
868 return -EINVAL;
869}
870
871static int hdmi_mode_valid(struct drm_connector *connector,
872 struct drm_display_mode *mode)
873{
874 struct hdmi_context *hdata = ctx_from_connector(connector);
875 int ret;
876
877 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
878 mode->hdisplay, mode->vdisplay, mode->vrefresh,
879 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
880 false, mode->clock * 1000);
881
882 ret = mixer_check_mode(mode);
883 if (ret)
884 return MODE_BAD;
885
886 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
887 if (ret < 0)
888 return MODE_BAD;
889
890 return MODE_OK;
891}
892
893static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
894{
895 struct hdmi_context *hdata = ctx_from_connector(connector);
896
897 return hdata->encoder;
898}
899
900static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
901 .get_modes = hdmi_get_modes,
902 .mode_valid = hdmi_mode_valid,
903 .best_encoder = hdmi_best_encoder,
904};
905
906static int hdmi_create_connector(struct exynos_drm_display *display,
907 struct drm_encoder *encoder)
908{
909 struct hdmi_context *hdata = display->ctx;
910 struct drm_connector *connector = &hdata->connector;
911 int ret;
912
913 hdata->encoder = encoder;
914 connector->interlace_allowed = true;
915 connector->polled = DRM_CONNECTOR_POLL_HPD;
916
917 ret = drm_connector_init(hdata->drm_dev, connector,
918 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
919 if (ret) {
920 DRM_ERROR("Failed to initialize connector with drm\n");
921 return ret;
922 }
923
924 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
925 drm_sysfs_connector_add(connector);
926 drm_mode_connector_attach_encoder(connector, encoder);
927
928 return 0;
929}
930
931static int hdmi_initialize(struct exynos_drm_display *display,
932 struct drm_device *drm_dev)
933{
934 struct hdmi_context *hdata = display->ctx;
935
936 hdata->drm_dev = drm_dev;
937
938 return 0;
939}
940
941static void hdmi_mode_fixup(struct exynos_drm_display *display,
942 struct drm_connector *connector,
943 const struct drm_display_mode *mode,
944 struct drm_display_mode *adjusted_mode)
945{
946 struct drm_display_mode *m;
947 int mode_ok;
948
949 DRM_DEBUG_KMS("%s\n", __FILE__);
950
951 drm_mode_set_crtcinfo(adjusted_mode, 0);
952
953 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
954
955 /* just return if user desired mode exists. */
956 if (mode_ok == MODE_OK)
957 return;
958
959 /*
960 * otherwise, find the most suitable mode among modes and change it
961 * to adjusted_mode.
962 */
963 list_for_each_entry(m, &connector->modes, head) {
964 mode_ok = hdmi_mode_valid(connector, m);
965
966 if (mode_ok == MODE_OK) {
967 DRM_INFO("desired mode doesn't exist so\n");
968 DRM_INFO("use the most suitable mode among modes.\n");
969
970 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
971 m->hdisplay, m->vdisplay, m->vrefresh);
972
973 drm_mode_copy(adjusted_mode, m);
974 break;
975 }
976 }
977}
978
979static void hdmi_set_acr(u32 freq, u8 *acr)
980{
981 u32 n, cts;
982
983 switch (freq) {
984 case 32000:
985 n = 4096;
986 cts = 27000;
987 break;
988 case 44100:
989 n = 6272;
990 cts = 30000;
991 break;
992 case 88200:
993 n = 12544;
994 cts = 30000;
995 break;
996 case 176400:
997 n = 25088;
998 cts = 30000;
999 break;
1000 case 48000:
1001 n = 6144;
1002 cts = 27000;
1003 break;
1004 case 96000:
1005 n = 12288;
1006 cts = 27000;
1007 break;
1008 case 192000:
1009 n = 24576;
1010 cts = 27000;
1011 break;
1012 default:
1013 n = 0;
1014 cts = 0;
1015 break;
1016 }
1017
1018 acr[1] = cts >> 16;
1019 acr[2] = cts >> 8 & 0xff;
1020 acr[3] = cts & 0xff;
1021
1022 acr[4] = n >> 16;
1023 acr[5] = n >> 8 & 0xff;
1024 acr[6] = n & 0xff;
1025}
1026
1027static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1028{
1029 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1030 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1031 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1032 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1033 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1034 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1035 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1036 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1037 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1038
1039 if (hdata->type == HDMI_TYPE13)
1040 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1041 else
1042 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1043}
1044
1045static void hdmi_audio_init(struct hdmi_context *hdata)
1046{
1047 u32 sample_rate, bits_per_sample, frame_size_code;
1048 u32 data_num, bit_ch, sample_frq;
1049 u32 val;
1050 u8 acr[7];
1051
1052 sample_rate = 44100;
1053 bits_per_sample = 16;
1054 frame_size_code = 0;
1055
1056 switch (bits_per_sample) {
1057 case 20:
1058 data_num = 2;
1059 bit_ch = 1;
1060 break;
1061 case 24:
1062 data_num = 3;
1063 bit_ch = 1;
1064 break;
1065 default:
1066 data_num = 1;
1067 bit_ch = 0;
1068 break;
1069 }
1070
1071 hdmi_set_acr(sample_rate, acr);
1072 hdmi_reg_acr(hdata, acr);
1073
1074 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1075 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1076 | HDMI_I2S_MUX_ENABLE);
1077
1078 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1079 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1080
1081 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1082
1083 sample_frq = (sample_rate == 44100) ? 0 :
1084 (sample_rate == 48000) ? 2 :
1085 (sample_rate == 32000) ? 3 :
1086 (sample_rate == 96000) ? 0xa : 0x0;
1087
1088 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1089 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1090
1091 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1092 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1093
1094 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1095 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1096 | HDMI_I2S_SEL_LRCK(6));
1097 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1098 | HDMI_I2S_SEL_SDATA2(4));
1099 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1100 | HDMI_I2S_SEL_SDATA2(2));
1101 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1102
1103 /* I2S_CON_1 & 2 */
1104 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1105 | HDMI_I2S_L_CH_LOW_POL);
1106 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1107 | HDMI_I2S_SET_BIT_CH(bit_ch)
1108 | HDMI_I2S_SET_SDATA_BIT(data_num)
1109 | HDMI_I2S_BASIC_FORMAT);
1110
1111 /* Configure register related to CUV information */
1112 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1113 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1114 | HDMI_I2S_COPYRIGHT
1115 | HDMI_I2S_LINEAR_PCM
1116 | HDMI_I2S_CONSUMER_FORMAT);
1117 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1118 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1119 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1120 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1121 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1122 HDMI_I2S_ORG_SMP_FREQ_44_1
1123 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1124 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1125
1126 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1127}
1128
1129static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1130{
1131 if (hdata->dvi_mode)
1132 return;
1133
1134 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1135 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1136 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1137}
1138
1139static void hdmi_conf_reset(struct hdmi_context *hdata)
1140{
1141 u32 reg;
1142
1143 if (hdata->type == HDMI_TYPE13)
1144 reg = HDMI_V13_CORE_RSTOUT;
1145 else
1146 reg = HDMI_CORE_RSTOUT;
1147
1148 /* resetting HDMI core */
1149 hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
1150 usleep_range(10000, 12000);
1151 hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1152 usleep_range(10000, 12000);
1153}
1154
1155static void hdmi_conf_init(struct hdmi_context *hdata)
1156{
1157 union hdmi_infoframe infoframe;
1158
1159 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1160 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1161 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1162
1163 /* choose HDMI mode */
1164 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1165 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1166 /* disable bluescreen */
1167 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1168
1169 if (hdata->dvi_mode) {
1170 /* choose DVI mode */
1171 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1172 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1173 hdmi_reg_writeb(hdata, HDMI_CON_2,
1174 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1175 }
1176
1177 if (hdata->type == HDMI_TYPE13) {
1178 /* choose bluescreen (fecal) color */
1179 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1180 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1181 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1182
1183 /* enable AVI packet every vsync, fixes purple line problem */
1184 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1185 /* force RGB, look to CEA-861-D, table 7 for more detail */
1186 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1187 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1188
1189 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1190 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1191 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1192 } else {
1193 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1194 infoframe.any.version = HDMI_AVI_VERSION;
1195 infoframe.any.length = HDMI_AVI_LENGTH;
1196 hdmi_reg_infoframe(hdata, &infoframe);
1197
1198 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1199 infoframe.any.version = HDMI_AUI_VERSION;
1200 infoframe.any.length = HDMI_AUI_LENGTH;
1201 hdmi_reg_infoframe(hdata, &infoframe);
1202
1203 /* enable AVI packet every vsync, fixes purple line problem */
1204 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1205 }
1206}
1207
1208static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1209{
1210 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1211 const struct hdmi_v13_core_regs *core =
1212 &hdata->mode_conf.conf.v13_conf.core;
1213 int tries;
1214
1215 /* setting core registers */
1216 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1217 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1218 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1219 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1220 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1221 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1222 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1223 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1224 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1225 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1226 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1227 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1228 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1229 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1230 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1231 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1232 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1233 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1234 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1235 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1236 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1237 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1238 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1239 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1240 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1241 /* Timing generator registers */
1242 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1243 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1244 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1245 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1246 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1247 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1248 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1249 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1250 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1251 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1252 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1253 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1254 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1255 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1256 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1257 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1258 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1259 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1260 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1261 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1262 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1263 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1264 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1265 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1266 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1267 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1268 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1269 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1270
1271 /* waiting for HDMIPHY's PLL to get to steady state */
1272 for (tries = 100; tries; --tries) {
1273 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1274 if (val & HDMI_PHY_STATUS_READY)
1275 break;
1276 usleep_range(1000, 2000);
1277 }
1278 /* steady state not achieved */
1279 if (tries == 0) {
1280 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1281 hdmi_regs_dump(hdata, "timing apply");
1282 }
1283
1284 clk_disable_unprepare(hdata->res.sclk_hdmi);
1285 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1286 clk_prepare_enable(hdata->res.sclk_hdmi);
1287
1288 /* enable HDMI and timing generator */
1289 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1290 if (core->int_pro_mode[0])
1291 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1292 HDMI_FIELD_EN);
1293 else
1294 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1295}
1296
1297static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1298{
1299 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1300 const struct hdmi_v14_core_regs *core =
1301 &hdata->mode_conf.conf.v14_conf.core;
1302 int tries;
1303
1304 /* setting core registers */
1305 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1306 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1307 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1308 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1309 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1310 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1311 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1312 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1313 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1314 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1315 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1316 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1317 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1318 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1319 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1320 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1321 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1322 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1323 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1324 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1325 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1326 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1327 core->v_sync_line_bef_2[0]);
1328 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1329 core->v_sync_line_bef_2[1]);
1330 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1331 core->v_sync_line_bef_1[0]);
1332 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1333 core->v_sync_line_bef_1[1]);
1334 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1335 core->v_sync_line_aft_2[0]);
1336 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1337 core->v_sync_line_aft_2[1]);
1338 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1339 core->v_sync_line_aft_1[0]);
1340 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1341 core->v_sync_line_aft_1[1]);
1342 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1343 core->v_sync_line_aft_pxl_2[0]);
1344 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1345 core->v_sync_line_aft_pxl_2[1]);
1346 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1347 core->v_sync_line_aft_pxl_1[0]);
1348 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1349 core->v_sync_line_aft_pxl_1[1]);
1350 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1351 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1352 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1353 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1354 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1355 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1356 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1357 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1358 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1359 core->v_sync_line_aft_3[0]);
1360 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1361 core->v_sync_line_aft_3[1]);
1362 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1363 core->v_sync_line_aft_4[0]);
1364 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1365 core->v_sync_line_aft_4[1]);
1366 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1367 core->v_sync_line_aft_5[0]);
1368 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1369 core->v_sync_line_aft_5[1]);
1370 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1371 core->v_sync_line_aft_6[0]);
1372 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1373 core->v_sync_line_aft_6[1]);
1374 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1375 core->v_sync_line_aft_pxl_3[0]);
1376 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1377 core->v_sync_line_aft_pxl_3[1]);
1378 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1379 core->v_sync_line_aft_pxl_4[0]);
1380 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1381 core->v_sync_line_aft_pxl_4[1]);
1382 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1383 core->v_sync_line_aft_pxl_5[0]);
1384 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1385 core->v_sync_line_aft_pxl_5[1]);
1386 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1387 core->v_sync_line_aft_pxl_6[0]);
1388 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1389 core->v_sync_line_aft_pxl_6[1]);
1390 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1391 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1392 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1393 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1394 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1395 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1396 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1397 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1398 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1399 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1400 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1401 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1402
1403 /* Timing generator registers */
1404 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1405 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1406 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1407 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1408 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1409 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1410 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1411 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1412 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1413 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1414 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1415 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1416 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1417 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1418 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1419 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1420 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1421 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1422 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1423 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1424 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1425 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1426 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1427 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1428 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1429 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1430 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1431 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1432 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1433 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1434 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1435 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1436 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1437
1438 /* waiting for HDMIPHY's PLL to get to steady state */
1439 for (tries = 100; tries; --tries) {
1440 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1441 if (val & HDMI_PHY_STATUS_READY)
1442 break;
1443 usleep_range(1000, 2000);
1444 }
1445 /* steady state not achieved */
1446 if (tries == 0) {
1447 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1448 hdmi_regs_dump(hdata, "timing apply");
1449 }
1450
1451 clk_disable_unprepare(hdata->res.sclk_hdmi);
1452 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1453 clk_prepare_enable(hdata->res.sclk_hdmi);
1454
1455 /* enable HDMI and timing generator */
1456 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1457 if (core->int_pro_mode[0])
1458 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1459 HDMI_FIELD_EN);
1460 else
1461 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1462}
1463
1464static void hdmi_mode_apply(struct hdmi_context *hdata)
1465{
1466 if (hdata->type == HDMI_TYPE13)
1467 hdmi_v13_mode_apply(hdata);
1468 else
1469 hdmi_v14_mode_apply(hdata);
1470}
1471
1472static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1473{
1474 u8 buffer[2];
1475 u32 reg;
1476
1477 clk_disable_unprepare(hdata->res.sclk_hdmi);
1478 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
1479 clk_prepare_enable(hdata->res.sclk_hdmi);
1480
1481 /* operation mode */
1482 buffer[0] = 0x1f;
1483 buffer[1] = 0x00;
1484
1485 if (hdata->hdmiphy_port)
1486 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1487
1488 if (hdata->type == HDMI_TYPE13)
1489 reg = HDMI_V13_PHY_RSTOUT;
1490 else
1491 reg = HDMI_PHY_RSTOUT;
1492
1493 /* reset hdmiphy */
1494 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1495 usleep_range(10000, 12000);
1496 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
1497 usleep_range(10000, 12000);
1498}
1499
1500static void hdmiphy_poweron(struct hdmi_context *hdata)
1501{
1502 if (hdata->type == HDMI_TYPE14)
1503 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
1504 HDMI_PHY_POWER_OFF_EN);
1505}
1506
1507static void hdmiphy_poweroff(struct hdmi_context *hdata)
1508{
1509 if (hdata->type == HDMI_TYPE14)
1510 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
1511 HDMI_PHY_POWER_OFF_EN);
1512}
1513
1514static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1515{
1516 const u8 *hdmiphy_data;
1517 u8 buffer[32];
1518 u8 operation[2];
1519 u8 read_buffer[32] = {0, };
1520 int ret;
1521 int i;
1522
1523 if (!hdata->hdmiphy_port) {
1524 DRM_ERROR("hdmiphy is not attached\n");
1525 return;
1526 }
1527
1528 /* pixel clock */
1529 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1530 if (i < 0) {
1531 DRM_ERROR("failed to find hdmiphy conf\n");
1532 return;
1533 }
1534
1535 if (hdata->type == HDMI_TYPE13)
1536 hdmiphy_data = hdmiphy_v13_configs[i].conf;
1537 else
1538 hdmiphy_data = hdmiphy_v14_configs[i].conf;
1539
1540 memcpy(buffer, hdmiphy_data, 32);
1541 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1542 if (ret != 32) {
1543 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1544 return;
1545 }
1546
1547 usleep_range(10000, 12000);
1548
1549 /* operation mode */
1550 operation[0] = 0x1f;
1551 operation[1] = 0x80;
1552
1553 ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1554 if (ret != 2) {
1555 DRM_ERROR("failed to enable hdmiphy\n");
1556 return;
1557 }
1558
1559 ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1560 if (ret < 0) {
1561 DRM_ERROR("failed to read hdmiphy config\n");
1562 return;
1563 }
1564
1565 for (i = 0; i < ret; i++)
1566 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1567 "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1568}
1569
1570static void hdmi_conf_apply(struct hdmi_context *hdata)
1571{
1572 hdmiphy_conf_reset(hdata);
1573 hdmiphy_conf_apply(hdata);
1574
1575 mutex_lock(&hdata->hdmi_mutex);
1576 hdmi_conf_reset(hdata);
1577 hdmi_conf_init(hdata);
1578 mutex_unlock(&hdata->hdmi_mutex);
1579
1580 hdmi_audio_init(hdata);
1581
1582 /* setting core registers */
1583 hdmi_mode_apply(hdata);
1584 hdmi_audio_control(hdata, true);
1585
1586 hdmi_regs_dump(hdata, "start");
1587}
1588
1589static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1590{
1591 int i;
1592 BUG_ON(num_bytes > 4);
1593 for (i = 0; i < num_bytes; i++)
1594 reg_pair[i] = (value >> (8 * i)) & 0xff;
1595}
1596
1597static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1598 struct drm_display_mode *m)
1599{
1600 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1601 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1602 unsigned int val;
1603
1604 hdata->mode_conf.cea_video_id =
1605 drm_match_cea_mode((struct drm_display_mode *)m);
1606 hdata->mode_conf.pixel_clock = m->clock * 1000;
1607 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1608
1609 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1610 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1611
1612 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1613 hdmi_set_reg(core->vsync_pol, 1, val);
1614
1615 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1616 hdmi_set_reg(core->int_pro_mode, 1, val);
1617
1618 val = (m->hsync_start - m->hdisplay - 2);
1619 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1620 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1621 hdmi_set_reg(core->h_sync_gen, 3, val);
1622
1623 /*
1624 * Quirk requirement for exynos HDMI IP design,
1625 * 2 pixels less than the actual calculation for hsync_start
1626 * and end.
1627 */
1628
1629 /* Following values & calculations differ for different type of modes */
1630 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1631 /* Interlaced Mode */
1632 val = ((m->vsync_end - m->vdisplay) / 2);
1633 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1634 hdmi_set_reg(core->v_sync_gen1, 3, val);
1635
1636 val = m->vtotal / 2;
1637 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1638 hdmi_set_reg(core->v_blank, 3, val);
1639
1640 val = (m->vtotal +
1641 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1642 val |= m->vtotal << 11;
1643 hdmi_set_reg(core->v_blank_f, 3, val);
1644
1645 val = ((m->vtotal / 2) + 7);
1646 val |= ((m->vtotal / 2) + 2) << 12;
1647 hdmi_set_reg(core->v_sync_gen2, 3, val);
1648
1649 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1650 val |= ((m->htotal / 2) +
1651 (m->hsync_start - m->hdisplay)) << 12;
1652 hdmi_set_reg(core->v_sync_gen3, 3, val);
1653
1654 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1655 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1656
1657 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1658 } else {
1659 /* Progressive Mode */
1660
1661 val = m->vtotal;
1662 val |= (m->vtotal - m->vdisplay) << 11;
1663 hdmi_set_reg(core->v_blank, 3, val);
1664
1665 hdmi_set_reg(core->v_blank_f, 3, 0);
1666
1667 val = (m->vsync_end - m->vdisplay);
1668 val |= ((m->vsync_start - m->vdisplay) << 12);
1669 hdmi_set_reg(core->v_sync_gen1, 3, val);
1670
1671 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1672 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1673 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1674 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1675 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1676 }
1677
1678 /* Timing generator registers */
1679 hdmi_set_reg(tg->cmd, 1, 0x0);
1680 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1681 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1682 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1683 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1684 hdmi_set_reg(tg->vsync, 2, 0x1);
1685 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1686 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1687 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1688 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1689 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1690 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1691 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1692}
1693
1694static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1695 struct drm_display_mode *m)
1696{
1697 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1698 struct hdmi_v14_core_regs *core =
1699 &hdata->mode_conf.conf.v14_conf.core;
1700
1701 hdata->mode_conf.cea_video_id =
1702 drm_match_cea_mode((struct drm_display_mode *)m);
1703 hdata->mode_conf.pixel_clock = m->clock * 1000;
1704 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1705
1706 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1707 hdmi_set_reg(core->v_line, 2, m->vtotal);
1708 hdmi_set_reg(core->h_line, 2, m->htotal);
1709 hdmi_set_reg(core->hsync_pol, 1,
1710 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1711 hdmi_set_reg(core->vsync_pol, 1,
1712 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1713 hdmi_set_reg(core->int_pro_mode, 1,
1714 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1715
1716 /*
1717 * Quirk requirement for exynos 5 HDMI IP design,
1718 * 2 pixels less than the actual calculation for hsync_start
1719 * and end.
1720 */
1721
1722 /* Following values & calculations differ for different type of modes */
1723 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1724 /* Interlaced Mode */
1725 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1726 (m->vsync_end - m->vdisplay) / 2);
1727 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1728 (m->vsync_start - m->vdisplay) / 2);
1729 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1730 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1731 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
1732 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1733 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1734 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1735 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1736 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1737 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1738 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1739 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1740 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1741 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1742 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1743 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1744 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
1745 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1746 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1747 } else {
1748 /* Progressive Mode */
1749 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1750 m->vsync_end - m->vdisplay);
1751 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1752 m->vsync_start - m->vdisplay);
1753 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1754 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1755 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1756 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1757 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1758 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1759 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1760 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1761 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1762 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1763 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1764 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1765 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1766 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1767 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1768 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1769 }
1770
1771 /* Following values & calculations are same irrespective of mode type */
1772 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1773 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1774 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1775 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1776 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1777 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1778 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1779 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1780 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1781 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1782 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1783 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1784 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1785 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1786 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1787 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1788 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1789 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1790 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1791 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1792
1793 /* Timing generator registers */
1794 hdmi_set_reg(tg->cmd, 1, 0x0);
1795 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1796 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1797 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1798 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1799 hdmi_set_reg(tg->vsync, 2, 0x1);
1800 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1801 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1802 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1803 hdmi_set_reg(tg->tg_3d, 1, 0x0);
1804}
1805
1806static void hdmi_mode_set(struct exynos_drm_display *display,
1807 struct drm_display_mode *mode)
1808{
1809 struct hdmi_context *hdata = display->ctx;
1810 struct drm_display_mode *m = mode;
1811
1812 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1813 m->hdisplay, m->vdisplay,
1814 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1815 "INTERLACED" : "PROGERESSIVE");
1816
1817 if (hdata->type == HDMI_TYPE13)
1818 hdmi_v13_mode_set(hdata, mode);
1819 else
1820 hdmi_v14_mode_set(hdata, mode);
1821}
1822
1823static void hdmi_commit(struct exynos_drm_display *display)
1824{
1825 struct hdmi_context *hdata = display->ctx;
1826
1827 mutex_lock(&hdata->hdmi_mutex);
1828 if (!hdata->powered) {
1829 mutex_unlock(&hdata->hdmi_mutex);
1830 return;
1831 }
1832 mutex_unlock(&hdata->hdmi_mutex);
1833
1834 hdmi_conf_apply(hdata);
1835}
1836
1837static void hdmi_poweron(struct exynos_drm_display *display)
1838{
1839 struct hdmi_context *hdata = display->ctx;
1840 struct hdmi_resources *res = &hdata->res;
1841
1842 mutex_lock(&hdata->hdmi_mutex);
1843 if (hdata->powered) {
1844 mutex_unlock(&hdata->hdmi_mutex);
1845 return;
1846 }
1847
1848 hdata->powered = true;
1849
1850 mutex_unlock(&hdata->hdmi_mutex);
1851
1852 pm_runtime_get_sync(hdata->dev);
1853
1854 if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
1855 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1856
1857 clk_prepare_enable(res->hdmiphy);
1858 clk_prepare_enable(res->hdmi);
1859 clk_prepare_enable(res->sclk_hdmi);
1860
1861 hdmiphy_poweron(hdata);
1862 hdmi_commit(display);
1863}
1864
1865static void hdmi_poweroff(struct exynos_drm_display *display)
1866{
1867 struct hdmi_context *hdata = display->ctx;
1868 struct hdmi_resources *res = &hdata->res;
1869
1870 mutex_lock(&hdata->hdmi_mutex);
1871 if (!hdata->powered)
1872 goto out;
1873 mutex_unlock(&hdata->hdmi_mutex);
1874
1875 /*
1876 * The TV power domain needs any condition of hdmiphy to turn off and
1877 * its reset state seems to meet the condition.
1878 */
1879 hdmiphy_conf_reset(hdata);
1880 hdmiphy_poweroff(hdata);
1881
1882 clk_disable_unprepare(res->sclk_hdmi);
1883 clk_disable_unprepare(res->hdmi);
1884 clk_disable_unprepare(res->hdmiphy);
1885 regulator_bulk_disable(res->regul_count, res->regul_bulk);
1886
1887 pm_runtime_put_sync(hdata->dev);
1888
1889 mutex_lock(&hdata->hdmi_mutex);
1890 hdata->powered = false;
1891
1892out:
1893 mutex_unlock(&hdata->hdmi_mutex);
1894}
1895
1896static void hdmi_dpms(struct exynos_drm_display *display, int mode)
1897{
1898 DRM_DEBUG_KMS("mode %d\n", mode);
1899
1900 switch (mode) {
1901 case DRM_MODE_DPMS_ON:
1902 hdmi_poweron(display);
1903 break;
1904 case DRM_MODE_DPMS_STANDBY:
1905 case DRM_MODE_DPMS_SUSPEND:
1906 case DRM_MODE_DPMS_OFF:
1907 hdmi_poweroff(display);
1908 break;
1909 default:
1910 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1911 break;
1912 }
1913}
1914
1915static struct exynos_drm_display_ops hdmi_display_ops = {
1916 .initialize = hdmi_initialize,
1917 .create_connector = hdmi_create_connector,
1918 .mode_fixup = hdmi_mode_fixup,
1919 .mode_set = hdmi_mode_set,
1920 .dpms = hdmi_dpms,
1921 .commit = hdmi_commit,
1922};
1923
1924static struct exynos_drm_display hdmi_display = {
1925 .type = EXYNOS_DISPLAY_TYPE_HDMI,
1926 .ops = &hdmi_display_ops,
1927};
1928
1929static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1930{
1931 struct hdmi_context *hdata = arg;
1932
1933 mutex_lock(&hdata->hdmi_mutex);
1934 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1935 mutex_unlock(&hdata->hdmi_mutex);
1936
1937 if (hdata->drm_dev)
1938 drm_helper_hpd_irq_event(hdata->drm_dev);
1939
1940 return IRQ_HANDLED;
1941}
1942
1943static int hdmi_resources_init(struct hdmi_context *hdata)
1944{
1945 struct device *dev = hdata->dev;
1946 struct hdmi_resources *res = &hdata->res;
1947 static char *supply[] = {
1948 "hdmi-en",
1949 "vdd",
1950 "vdd_osc",
1951 "vdd_pll",
1952 };
1953 int i, ret;
1954
1955 DRM_DEBUG_KMS("HDMI resource init\n");
1956
1957 memset(res, 0, sizeof(*res));
1958
1959 /* get clocks, power */
1960 res->hdmi = devm_clk_get(dev, "hdmi");
1961 if (IS_ERR(res->hdmi)) {
1962 DRM_ERROR("failed to get clock 'hdmi'\n");
1963 goto fail;
1964 }
1965 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
1966 if (IS_ERR(res->sclk_hdmi)) {
1967 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1968 goto fail;
1969 }
1970 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
1971 if (IS_ERR(res->sclk_pixel)) {
1972 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1973 goto fail;
1974 }
1975 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
1976 if (IS_ERR(res->sclk_hdmiphy)) {
1977 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1978 goto fail;
1979 }
1980 res->hdmiphy = devm_clk_get(dev, "hdmiphy");
1981 if (IS_ERR(res->hdmiphy)) {
1982 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1983 goto fail;
1984 }
1985 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
1986 if (IS_ERR(res->mout_hdmi)) {
1987 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
1988 goto fail;
1989 }
1990
1991 clk_set_parent(res->mout_hdmi, res->sclk_pixel);
1992
1993 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
1994 sizeof(res->regul_bulk[0]), GFP_KERNEL);
1995 if (!res->regul_bulk)
1996 goto fail;
1997 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1998 res->regul_bulk[i].supply = supply[i];
1999 res->regul_bulk[i].consumer = NULL;
2000 }
2001 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2002 if (ret) {
2003 DRM_ERROR("failed to get regulators\n");
2004 goto fail;
2005 }
2006 res->regul_count = ARRAY_SIZE(supply);
2007
2008 return 0;
2009fail:
2010 DRM_ERROR("HDMI resource init - failed\n");
2011 return -ENODEV;
2012}
2013
2014static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
2015 (struct device *dev)
2016{
2017 struct device_node *np = dev->of_node;
2018 struct s5p_hdmi_platform_data *pd;
2019 u32 value;
2020
2021 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
2022 if (!pd)
2023 goto err_data;
2024
2025 if (!of_find_property(np, "hpd-gpio", &value)) {
2026 DRM_ERROR("no hpd gpio property found\n");
2027 goto err_data;
2028 }
2029
2030 pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
2031
2032 return pd;
2033
2034err_data:
2035 return NULL;
2036}
2037
2038static struct of_device_id hdmi_match_types[] = {
2039 {
2040 .compatible = "samsung,exynos5-hdmi",
2041 .data = &exynos5_hdmi_driver_data,
2042 }, {
2043 .compatible = "samsung,exynos4212-hdmi",
2044 .data = &exynos4212_hdmi_driver_data,
2045 }, {
2046 /* end node */
2047 }
2048};
2049
2050static int hdmi_probe(struct platform_device *pdev)
2051{
2052 struct device *dev = &pdev->dev;
2053 struct hdmi_context *hdata;
2054 struct s5p_hdmi_platform_data *pdata;
2055 struct resource *res;
2056 const struct of_device_id *match;
2057 struct device_node *ddc_node, *phy_node;
2058 struct hdmi_driver_data *drv_data;
2059 int ret;
2060
2061 if (!dev->of_node)
2062 return -ENODEV;
2063
2064 pdata = drm_hdmi_dt_parse_pdata(dev);
2065 if (!pdata)
2066 return -EINVAL;
2067
2068 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2069 if (!hdata)
2070 return -ENOMEM;
2071
2072 mutex_init(&hdata->hdmi_mutex);
2073
2074 platform_set_drvdata(pdev, &hdmi_display);
2075
2076 match = of_match_node(hdmi_match_types, dev->of_node);
2077 if (!match)
2078 return -ENODEV;
2079
2080 drv_data = (struct hdmi_driver_data *)match->data;
2081 hdata->type = drv_data->type;
2082
2083 hdata->hpd_gpio = pdata->hpd_gpio;
2084 hdata->dev = dev;
2085
2086 ret = hdmi_resources_init(hdata);
2087 if (ret) {
2088 DRM_ERROR("hdmi_resources_init failed\n");
2089 return -EINVAL;
2090 }
2091
2092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2093 hdata->regs = devm_ioremap_resource(dev, res);
2094 if (IS_ERR(hdata->regs))
2095 return PTR_ERR(hdata->regs);
2096
2097 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
2098 if (ret) {
2099 DRM_ERROR("failed to request HPD gpio\n");
2100 return ret;
2101 }
2102
2103 /* DDC i2c driver */
2104 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2105 if (!ddc_node) {
2106 DRM_ERROR("Failed to find ddc node in device tree\n");
2107 return -ENODEV;
2108 }
2109 hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2110 if (!hdata->ddc_adpt) {
2111 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
2112 return -ENODEV;
2113 }
2114
2115 /* Not support APB PHY yet. */
2116 if (drv_data->is_apb_phy)
2117 return -EPERM;
2118
2119 /* hdmiphy i2c driver */
2120 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2121 if (!phy_node) {
2122 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2123 ret = -ENODEV;
2124 goto err_ddc;
2125 }
2126 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2127 if (!hdata->hdmiphy_port) {
2128 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2129 ret = -ENODEV;
2130 goto err_ddc;
2131 }
2132
2133 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2134 if (hdata->irq < 0) {
2135 DRM_ERROR("failed to get GPIO irq\n");
2136 ret = hdata->irq;
2137 goto err_hdmiphy;
2138 }
2139
2140 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2141
2142 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2143 hdmi_irq_thread, IRQF_TRIGGER_RISING |
2144 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2145 "hdmi", hdata);
2146 if (ret) {
2147 DRM_ERROR("failed to register hdmi interrupt\n");
2148 goto err_hdmiphy;
2149 }
2150
2151 pm_runtime_enable(dev);
2152
2153 hdmi_display.ctx = hdata;
2154 exynos_drm_display_register(&hdmi_display);
2155
2156 return 0;
2157
2158err_hdmiphy:
2159 put_device(&hdata->hdmiphy_port->dev);
2160err_ddc:
2161 put_device(&hdata->ddc_adpt->dev);
2162 return ret;
2163}
2164
2165static int hdmi_remove(struct platform_device *pdev)
2166{
2167 struct device *dev = &pdev->dev;
2168 struct exynos_drm_display *display = get_hdmi_display(dev);
2169 struct hdmi_context *hdata = display->ctx;
2170
2171 put_device(&hdata->hdmiphy_port->dev);
2172 put_device(&hdata->ddc_adpt->dev);
2173 pm_runtime_disable(&pdev->dev);
2174
2175 return 0;
2176}
2177
2178struct platform_driver hdmi_driver = {
2179 .probe = hdmi_probe,
2180 .remove = hdmi_remove,
2181 .driver = {
2182 .name = "exynos-hdmi",
2183 .owner = THIS_MODULE,
2184 .of_match_table = hdmi_match_types,
2185 },
2186};