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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for x86 and x86_64 platform bugs.
4 */
5#include <linux/dmi.h>
6#include <linux/pci.h>
7#include <linux/irq.h>
8
9#include <asm/hpet.h>
10#include <asm/setup.h>
11#include <asm/mce.h>
12
13#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
14
15static void quirk_intel_irqbalance(struct pci_dev *dev)
16{
17 u8 config;
18 u16 word;
19
20 /* BIOS may enable hardware IRQ balancing for
21 * E7520/E7320/E7525(revision ID 0x9 and below)
22 * based platforms.
23 * Disable SW irqbalance/affinity on those platforms.
24 */
25 if (dev->revision > 0x9)
26 return;
27
28 /* enable access to config space*/
29 pci_read_config_byte(dev, 0xf4, &config);
30 pci_write_config_byte(dev, 0xf4, config|0x2);
31
32 /*
33 * read xTPR register. We may not have a pci_dev for device 8
34 * because it might be hidden until the above write.
35 */
36 pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
37
38 if (!(word & (1 << 13))) {
39 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
40 "disabling irq balancing and affinity\n");
41 noirqdebug_setup("");
42#ifdef CONFIG_PROC_FS
43 no_irq_affinity = 1;
44#endif
45 }
46
47 /* put back the original value for config space*/
48 if (!(config & 0x2))
49 pci_write_config_byte(dev, 0xf4, config);
50}
51DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
52 quirk_intel_irqbalance);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
54 quirk_intel_irqbalance);
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
56 quirk_intel_irqbalance);
57#endif
58
59#if defined(CONFIG_HPET_TIMER)
60unsigned long force_hpet_address;
61
62static enum {
63 NONE_FORCE_HPET_RESUME,
64 OLD_ICH_FORCE_HPET_RESUME,
65 ICH_FORCE_HPET_RESUME,
66 VT8237_FORCE_HPET_RESUME,
67 NVIDIA_FORCE_HPET_RESUME,
68 ATI_FORCE_HPET_RESUME,
69} force_hpet_resume_type;
70
71static void __iomem *rcba_base;
72
73static void ich_force_hpet_resume(void)
74{
75 u32 val;
76
77 if (!force_hpet_address)
78 return;
79
80 BUG_ON(rcba_base == NULL);
81
82 /* read the Function Disable register, dword mode only */
83 val = readl(rcba_base + 0x3404);
84 if (!(val & 0x80)) {
85 /* HPET disabled in HPTC. Trying to enable */
86 writel(val | 0x80, rcba_base + 0x3404);
87 }
88
89 val = readl(rcba_base + 0x3404);
90 if (!(val & 0x80))
91 BUG();
92 else
93 printk(KERN_DEBUG "Force enabled HPET at resume\n");
94}
95
96static void ich_force_enable_hpet(struct pci_dev *dev)
97{
98 u32 val;
99 u32 rcba;
100 int err = 0;
101
102 if (hpet_address || force_hpet_address)
103 return;
104
105 pci_read_config_dword(dev, 0xF0, &rcba);
106 rcba &= 0xFFFFC000;
107 if (rcba == 0) {
108 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
109 "cannot force enable HPET\n");
110 return;
111 }
112
113 /* use bits 31:14, 16 kB aligned */
114 rcba_base = ioremap(rcba, 0x4000);
115 if (rcba_base == NULL) {
116 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
117 "cannot force enable HPET\n");
118 return;
119 }
120
121 /* read the Function Disable register, dword mode only */
122 val = readl(rcba_base + 0x3404);
123
124 if (val & 0x80) {
125 /* HPET is enabled in HPTC. Just not reported by BIOS */
126 val = val & 0x3;
127 force_hpet_address = 0xFED00000 | (val << 12);
128 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
129 "0x%lx\n", force_hpet_address);
130 iounmap(rcba_base);
131 return;
132 }
133
134 /* HPET disabled in HPTC. Trying to enable */
135 writel(val | 0x80, rcba_base + 0x3404);
136
137 val = readl(rcba_base + 0x3404);
138 if (!(val & 0x80)) {
139 err = 1;
140 } else {
141 val = val & 0x3;
142 force_hpet_address = 0xFED00000 | (val << 12);
143 }
144
145 if (err) {
146 force_hpet_address = 0;
147 iounmap(rcba_base);
148 dev_printk(KERN_DEBUG, &dev->dev,
149 "Failed to force enable HPET\n");
150 } else {
151 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
152 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
153 "0x%lx\n", force_hpet_address);
154 }
155}
156
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
158 ich_force_enable_hpet);
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
160 ich_force_enable_hpet);
161DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
162 ich_force_enable_hpet);
163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
164 ich_force_enable_hpet);
165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
166 ich_force_enable_hpet);
167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
168 ich_force_enable_hpet);
169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
170 ich_force_enable_hpet);
171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
172 ich_force_enable_hpet);
173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
174 ich_force_enable_hpet);
175DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */
176 ich_force_enable_hpet);
177
178static struct pci_dev *cached_dev;
179
180static void hpet_print_force_info(void)
181{
182 printk(KERN_INFO "HPET not enabled in BIOS. "
183 "You might try hpet=force boot option\n");
184}
185
186static void old_ich_force_hpet_resume(void)
187{
188 u32 val;
189 u32 gen_cntl;
190
191 if (!force_hpet_address || !cached_dev)
192 return;
193
194 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
195 gen_cntl &= (~(0x7 << 15));
196 gen_cntl |= (0x4 << 15);
197
198 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
199 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
200 val = gen_cntl >> 15;
201 val &= 0x7;
202 if (val == 0x4)
203 printk(KERN_DEBUG "Force enabled HPET at resume\n");
204 else
205 BUG();
206}
207
208static void old_ich_force_enable_hpet(struct pci_dev *dev)
209{
210 u32 val;
211 u32 gen_cntl;
212
213 if (hpet_address || force_hpet_address)
214 return;
215
216 pci_read_config_dword(dev, 0xD0, &gen_cntl);
217 /*
218 * Bit 17 is HPET enable bit.
219 * Bit 16:15 control the HPET base address.
220 */
221 val = gen_cntl >> 15;
222 val &= 0x7;
223 if (val & 0x4) {
224 val &= 0x3;
225 force_hpet_address = 0xFED00000 | (val << 12);
226 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
227 force_hpet_address);
228 return;
229 }
230
231 /*
232 * HPET is disabled. Trying enabling at FED00000 and check
233 * whether it sticks
234 */
235 gen_cntl &= (~(0x7 << 15));
236 gen_cntl |= (0x4 << 15);
237 pci_write_config_dword(dev, 0xD0, gen_cntl);
238
239 pci_read_config_dword(dev, 0xD0, &gen_cntl);
240
241 val = gen_cntl >> 15;
242 val &= 0x7;
243 if (val & 0x4) {
244 /* HPET is enabled in HPTC. Just not reported by BIOS */
245 val &= 0x3;
246 force_hpet_address = 0xFED00000 | (val << 12);
247 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
248 "0x%lx\n", force_hpet_address);
249 cached_dev = dev;
250 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
251 return;
252 }
253
254 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
255}
256
257/*
258 * Undocumented chipset features. Make sure that the user enforced
259 * this.
260 */
261static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
262{
263 if (hpet_force_user)
264 old_ich_force_enable_hpet(dev);
265}
266
267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
268 old_ich_force_enable_hpet_user);
269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
270 old_ich_force_enable_hpet_user);
271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
272 old_ich_force_enable_hpet_user);
273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
274 old_ich_force_enable_hpet_user);
275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
276 old_ich_force_enable_hpet_user);
277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
278 old_ich_force_enable_hpet);
279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
280 old_ich_force_enable_hpet);
281
282
283static void vt8237_force_hpet_resume(void)
284{
285 u32 val;
286
287 if (!force_hpet_address || !cached_dev)
288 return;
289
290 val = 0xfed00000 | 0x80;
291 pci_write_config_dword(cached_dev, 0x68, val);
292
293 pci_read_config_dword(cached_dev, 0x68, &val);
294 if (val & 0x80)
295 printk(KERN_DEBUG "Force enabled HPET at resume\n");
296 else
297 BUG();
298}
299
300static void vt8237_force_enable_hpet(struct pci_dev *dev)
301{
302 u32 val;
303
304 if (hpet_address || force_hpet_address)
305 return;
306
307 if (!hpet_force_user) {
308 hpet_print_force_info();
309 return;
310 }
311
312 pci_read_config_dword(dev, 0x68, &val);
313 /*
314 * Bit 7 is HPET enable bit.
315 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
316 */
317 if (val & 0x80) {
318 force_hpet_address = (val & ~0x3ff);
319 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
320 force_hpet_address);
321 return;
322 }
323
324 /*
325 * HPET is disabled. Trying enabling at FED00000 and check
326 * whether it sticks
327 */
328 val = 0xfed00000 | 0x80;
329 pci_write_config_dword(dev, 0x68, val);
330
331 pci_read_config_dword(dev, 0x68, &val);
332 if (val & 0x80) {
333 force_hpet_address = (val & ~0x3ff);
334 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
335 "0x%lx\n", force_hpet_address);
336 cached_dev = dev;
337 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
338 return;
339 }
340
341 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
342}
343
344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
345 vt8237_force_enable_hpet);
346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
347 vt8237_force_enable_hpet);
348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
349 vt8237_force_enable_hpet);
350
351static void ati_force_hpet_resume(void)
352{
353 pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
354 printk(KERN_DEBUG "Force enabled HPET at resume\n");
355}
356
357static u32 ati_ixp4x0_rev(struct pci_dev *dev)
358{
359 int err = 0;
360 u32 d = 0;
361 u8 b = 0;
362
363 err = pci_read_config_byte(dev, 0xac, &b);
364 b &= ~(1<<5);
365 err |= pci_write_config_byte(dev, 0xac, b);
366 err |= pci_read_config_dword(dev, 0x70, &d);
367 d |= 1<<8;
368 err |= pci_write_config_dword(dev, 0x70, d);
369 err |= pci_read_config_dword(dev, 0x8, &d);
370 d &= 0xff;
371 dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
372
373 WARN_ON_ONCE(err);
374
375 return d;
376}
377
378static void ati_force_enable_hpet(struct pci_dev *dev)
379{
380 u32 d, val;
381 u8 b;
382
383 if (hpet_address || force_hpet_address)
384 return;
385
386 if (!hpet_force_user) {
387 hpet_print_force_info();
388 return;
389 }
390
391 d = ati_ixp4x0_rev(dev);
392 if (d < 0x82)
393 return;
394
395 /* base address */
396 pci_write_config_dword(dev, 0x14, 0xfed00000);
397 pci_read_config_dword(dev, 0x14, &val);
398
399 /* enable interrupt */
400 outb(0x72, 0xcd6); b = inb(0xcd7);
401 b |= 0x1;
402 outb(0x72, 0xcd6); outb(b, 0xcd7);
403 outb(0x72, 0xcd6); b = inb(0xcd7);
404 if (!(b & 0x1))
405 return;
406 pci_read_config_dword(dev, 0x64, &d);
407 d |= (1<<10);
408 pci_write_config_dword(dev, 0x64, d);
409 pci_read_config_dword(dev, 0x64, &d);
410 if (!(d & (1<<10)))
411 return;
412
413 force_hpet_address = val;
414 force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
415 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
416 force_hpet_address);
417 cached_dev = dev;
418}
419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
420 ati_force_enable_hpet);
421
422/*
423 * Undocumented chipset feature taken from LinuxBIOS.
424 */
425static void nvidia_force_hpet_resume(void)
426{
427 pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
428 printk(KERN_DEBUG "Force enabled HPET at resume\n");
429}
430
431static void nvidia_force_enable_hpet(struct pci_dev *dev)
432{
433 u32 val;
434
435 if (hpet_address || force_hpet_address)
436 return;
437
438 if (!hpet_force_user) {
439 hpet_print_force_info();
440 return;
441 }
442
443 pci_write_config_dword(dev, 0x44, 0xfed00001);
444 pci_read_config_dword(dev, 0x44, &val);
445 force_hpet_address = val & 0xfffffffe;
446 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
447 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
448 force_hpet_address);
449 cached_dev = dev;
450}
451
452/* ISA Bridges */
453DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
454 nvidia_force_enable_hpet);
455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
456 nvidia_force_enable_hpet);
457
458/* LPC bridges */
459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
460 nvidia_force_enable_hpet);
461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
462 nvidia_force_enable_hpet);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
464 nvidia_force_enable_hpet);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
466 nvidia_force_enable_hpet);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
468 nvidia_force_enable_hpet);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
470 nvidia_force_enable_hpet);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
472 nvidia_force_enable_hpet);
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
474 nvidia_force_enable_hpet);
475DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
476 nvidia_force_enable_hpet);
477
478void force_hpet_resume(void)
479{
480 switch (force_hpet_resume_type) {
481 case ICH_FORCE_HPET_RESUME:
482 ich_force_hpet_resume();
483 return;
484 case OLD_ICH_FORCE_HPET_RESUME:
485 old_ich_force_hpet_resume();
486 return;
487 case VT8237_FORCE_HPET_RESUME:
488 vt8237_force_hpet_resume();
489 return;
490 case NVIDIA_FORCE_HPET_RESUME:
491 nvidia_force_hpet_resume();
492 return;
493 case ATI_FORCE_HPET_RESUME:
494 ati_force_hpet_resume();
495 return;
496 default:
497 break;
498 }
499}
500
501/*
502 * According to the datasheet e6xx systems have the HPET hardwired to
503 * 0xfed00000
504 */
505static void e6xx_force_enable_hpet(struct pci_dev *dev)
506{
507 if (hpet_address || force_hpet_address)
508 return;
509
510 force_hpet_address = 0xFED00000;
511 force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
512 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
513 "0x%lx\n", force_hpet_address);
514}
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
516 e6xx_force_enable_hpet);
517
518/*
519 * HPET MSI on some boards (ATI SB700/SB800) has side effect on
520 * floppy DMA. Disable HPET MSI on such platforms.
521 * See erratum #27 (Misinterpreted MSI Requests May Result in
522 * Corrupted LPC DMA Data) in AMD Publication #46837,
523 * "SB700 Family Product Errata", Rev. 1.0, March 2010.
524 */
525static void force_disable_hpet_msi(struct pci_dev *unused)
526{
527 hpet_msi_disable = true;
528}
529
530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
531 force_disable_hpet_msi);
532
533#endif
534
535#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
536/* Set correct numa_node information for AMD NB functions */
537static void quirk_amd_nb_node(struct pci_dev *dev)
538{
539 struct pci_dev *nb_ht;
540 unsigned int devfn;
541 u32 node;
542 u32 val;
543
544 devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
545 nb_ht = pci_get_slot(dev->bus, devfn);
546 if (!nb_ht)
547 return;
548
549 pci_read_config_dword(nb_ht, 0x60, &val);
550 node = pcibus_to_node(dev->bus) | (val & 7);
551 /*
552 * Some hardware may return an invalid node ID,
553 * so check it first:
554 */
555 if (node_online(node))
556 set_dev_node(&dev->dev, node);
557 pci_dev_put(nb_ht);
558}
559
560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
561 quirk_amd_nb_node);
562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
563 quirk_amd_nb_node);
564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
565 quirk_amd_nb_node);
566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
567 quirk_amd_nb_node);
568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
569 quirk_amd_nb_node);
570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
571 quirk_amd_nb_node);
572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
573 quirk_amd_nb_node);
574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
575 quirk_amd_nb_node);
576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
577 quirk_amd_nb_node);
578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0,
579 quirk_amd_nb_node);
580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1,
581 quirk_amd_nb_node);
582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2,
583 quirk_amd_nb_node);
584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3,
585 quirk_amd_nb_node);
586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4,
587 quirk_amd_nb_node);
588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
589 quirk_amd_nb_node);
590
591#endif
592
593#ifdef CONFIG_PCI
594/*
595 * Processor does not ensure DRAM scrub read/write sequence
596 * is atomic wrt accesses to CC6 save state area. Therefore
597 * if a concurrent scrub read/write access is to same address
598 * the entry may appear as if it is not written. This quirk
599 * applies to Fam16h models 00h-0Fh
600 *
601 * See "Revision Guide" for AMD F16h models 00h-0fh,
602 * document 51810 rev. 3.04, Nov 2013
603 */
604static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
605{
606 u32 val;
607
608 /*
609 * Suggested workaround:
610 * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
611 */
612 pci_read_config_dword(dev, 0x58, &val);
613 if (val & 0x1F) {
614 val &= ~(0x1F);
615 pci_write_config_dword(dev, 0x58, val);
616 }
617
618 pci_read_config_dword(dev, 0x5C, &val);
619 if (val & BIT(0)) {
620 val &= ~BIT(0);
621 pci_write_config_dword(dev, 0x5c, val);
622 }
623}
624
625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
626 amd_disable_seq_and_redirect_scrub);
627
628/* Ivy Bridge, Haswell, Broadwell */
629static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev)
630{
631 u32 capid0;
632
633 pci_read_config_dword(pdev, 0x84, &capid0);
634
635 if (capid0 & 0x10)
636 enable_copy_mc_fragile();
637}
638
639/* Skylake */
640static void quirk_intel_purley_xeon_ras_cap(struct pci_dev *pdev)
641{
642 u32 capid0, capid5;
643
644 pci_read_config_dword(pdev, 0x84, &capid0);
645 pci_read_config_dword(pdev, 0x98, &capid5);
646
647 /*
648 * CAPID0{7:6} indicate whether this is an advanced RAS SKU
649 * CAPID5{8:5} indicate that various NVDIMM usage modes are
650 * enabled, so memory machine check recovery is also enabled.
651 */
652 if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
653 enable_copy_mc_fragile();
654
655}
656DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
657DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);
658DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap);
659DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap);
660#endif
661
662bool x86_apple_machine;
663EXPORT_SYMBOL(x86_apple_machine);
664
665void __init early_platform_quirks(void)
666{
667 x86_apple_machine = dmi_match(DMI_SYS_VENDOR, "Apple Inc.") ||
668 dmi_match(DMI_SYS_VENDOR, "Apple Computer, Inc.");
669}
1/*
2 * This file contains work-arounds for x86 and x86_64 platform bugs.
3 */
4#include <linux/pci.h>
5#include <linux/irq.h>
6
7#include <asm/hpet.h>
8
9#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
10
11static void quirk_intel_irqbalance(struct pci_dev *dev)
12{
13 u8 config;
14 u16 word;
15
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
18 * based platforms.
19 * Disable SW irqbalance/affinity on those platforms.
20 */
21 if (dev->revision > 0x9)
22 return;
23
24 /* enable access to config space*/
25 pci_read_config_byte(dev, 0xf4, &config);
26 pci_write_config_byte(dev, 0xf4, config|0x2);
27
28 /*
29 * read xTPR register. We may not have a pci_dev for device 8
30 * because it might be hidden until the above write.
31 */
32 pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
33
34 if (!(word & (1 << 13))) {
35 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
36 "disabling irq balancing and affinity\n");
37 noirqdebug_setup("");
38#ifdef CONFIG_PROC_FS
39 no_irq_affinity = 1;
40#endif
41 }
42
43 /* put back the original value for config space*/
44 if (!(config & 0x2))
45 pci_write_config_byte(dev, 0xf4, config);
46}
47DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
48 quirk_intel_irqbalance);
49DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
50 quirk_intel_irqbalance);
51DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
52 quirk_intel_irqbalance);
53#endif
54
55#if defined(CONFIG_HPET_TIMER)
56unsigned long force_hpet_address;
57
58static enum {
59 NONE_FORCE_HPET_RESUME,
60 OLD_ICH_FORCE_HPET_RESUME,
61 ICH_FORCE_HPET_RESUME,
62 VT8237_FORCE_HPET_RESUME,
63 NVIDIA_FORCE_HPET_RESUME,
64 ATI_FORCE_HPET_RESUME,
65} force_hpet_resume_type;
66
67static void __iomem *rcba_base;
68
69static void ich_force_hpet_resume(void)
70{
71 u32 val;
72
73 if (!force_hpet_address)
74 return;
75
76 BUG_ON(rcba_base == NULL);
77
78 /* read the Function Disable register, dword mode only */
79 val = readl(rcba_base + 0x3404);
80 if (!(val & 0x80)) {
81 /* HPET disabled in HPTC. Trying to enable */
82 writel(val | 0x80, rcba_base + 0x3404);
83 }
84
85 val = readl(rcba_base + 0x3404);
86 if (!(val & 0x80))
87 BUG();
88 else
89 printk(KERN_DEBUG "Force enabled HPET at resume\n");
90
91 return;
92}
93
94static void ich_force_enable_hpet(struct pci_dev *dev)
95{
96 u32 val;
97 u32 uninitialized_var(rcba);
98 int err = 0;
99
100 if (hpet_address || force_hpet_address)
101 return;
102
103 pci_read_config_dword(dev, 0xF0, &rcba);
104 rcba &= 0xFFFFC000;
105 if (rcba == 0) {
106 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
107 "cannot force enable HPET\n");
108 return;
109 }
110
111 /* use bits 31:14, 16 kB aligned */
112 rcba_base = ioremap_nocache(rcba, 0x4000);
113 if (rcba_base == NULL) {
114 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
115 "cannot force enable HPET\n");
116 return;
117 }
118
119 /* read the Function Disable register, dword mode only */
120 val = readl(rcba_base + 0x3404);
121
122 if (val & 0x80) {
123 /* HPET is enabled in HPTC. Just not reported by BIOS */
124 val = val & 0x3;
125 force_hpet_address = 0xFED00000 | (val << 12);
126 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
127 "0x%lx\n", force_hpet_address);
128 iounmap(rcba_base);
129 return;
130 }
131
132 /* HPET disabled in HPTC. Trying to enable */
133 writel(val | 0x80, rcba_base + 0x3404);
134
135 val = readl(rcba_base + 0x3404);
136 if (!(val & 0x80)) {
137 err = 1;
138 } else {
139 val = val & 0x3;
140 force_hpet_address = 0xFED00000 | (val << 12);
141 }
142
143 if (err) {
144 force_hpet_address = 0;
145 iounmap(rcba_base);
146 dev_printk(KERN_DEBUG, &dev->dev,
147 "Failed to force enable HPET\n");
148 } else {
149 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
150 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
151 "0x%lx\n", force_hpet_address);
152 }
153}
154
155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
156 ich_force_enable_hpet);
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
158 ich_force_enable_hpet);
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
160 ich_force_enable_hpet);
161DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
162 ich_force_enable_hpet);
163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
164 ich_force_enable_hpet);
165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
166 ich_force_enable_hpet);
167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
168 ich_force_enable_hpet);
169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4,
170 ich_force_enable_hpet);
171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
172 ich_force_enable_hpet);
173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3a16, /* ICH10 */
174 ich_force_enable_hpet);
175
176static struct pci_dev *cached_dev;
177
178static void hpet_print_force_info(void)
179{
180 printk(KERN_INFO "HPET not enabled in BIOS. "
181 "You might try hpet=force boot option\n");
182}
183
184static void old_ich_force_hpet_resume(void)
185{
186 u32 val;
187 u32 uninitialized_var(gen_cntl);
188
189 if (!force_hpet_address || !cached_dev)
190 return;
191
192 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
193 gen_cntl &= (~(0x7 << 15));
194 gen_cntl |= (0x4 << 15);
195
196 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
197 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
198 val = gen_cntl >> 15;
199 val &= 0x7;
200 if (val == 0x4)
201 printk(KERN_DEBUG "Force enabled HPET at resume\n");
202 else
203 BUG();
204}
205
206static void old_ich_force_enable_hpet(struct pci_dev *dev)
207{
208 u32 val;
209 u32 uninitialized_var(gen_cntl);
210
211 if (hpet_address || force_hpet_address)
212 return;
213
214 pci_read_config_dword(dev, 0xD0, &gen_cntl);
215 /*
216 * Bit 17 is HPET enable bit.
217 * Bit 16:15 control the HPET base address.
218 */
219 val = gen_cntl >> 15;
220 val &= 0x7;
221 if (val & 0x4) {
222 val &= 0x3;
223 force_hpet_address = 0xFED00000 | (val << 12);
224 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
225 force_hpet_address);
226 return;
227 }
228
229 /*
230 * HPET is disabled. Trying enabling at FED00000 and check
231 * whether it sticks
232 */
233 gen_cntl &= (~(0x7 << 15));
234 gen_cntl |= (0x4 << 15);
235 pci_write_config_dword(dev, 0xD0, gen_cntl);
236
237 pci_read_config_dword(dev, 0xD0, &gen_cntl);
238
239 val = gen_cntl >> 15;
240 val &= 0x7;
241 if (val & 0x4) {
242 /* HPET is enabled in HPTC. Just not reported by BIOS */
243 val &= 0x3;
244 force_hpet_address = 0xFED00000 | (val << 12);
245 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
246 "0x%lx\n", force_hpet_address);
247 cached_dev = dev;
248 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
249 return;
250 }
251
252 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
253}
254
255/*
256 * Undocumented chipset features. Make sure that the user enforced
257 * this.
258 */
259static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
260{
261 if (hpet_force_user)
262 old_ich_force_enable_hpet(dev);
263}
264
265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
266 old_ich_force_enable_hpet_user);
267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
268 old_ich_force_enable_hpet_user);
269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
270 old_ich_force_enable_hpet_user);
271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
272 old_ich_force_enable_hpet_user);
273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
274 old_ich_force_enable_hpet_user);
275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
276 old_ich_force_enable_hpet);
277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
278 old_ich_force_enable_hpet);
279
280
281static void vt8237_force_hpet_resume(void)
282{
283 u32 val;
284
285 if (!force_hpet_address || !cached_dev)
286 return;
287
288 val = 0xfed00000 | 0x80;
289 pci_write_config_dword(cached_dev, 0x68, val);
290
291 pci_read_config_dword(cached_dev, 0x68, &val);
292 if (val & 0x80)
293 printk(KERN_DEBUG "Force enabled HPET at resume\n");
294 else
295 BUG();
296}
297
298static void vt8237_force_enable_hpet(struct pci_dev *dev)
299{
300 u32 uninitialized_var(val);
301
302 if (hpet_address || force_hpet_address)
303 return;
304
305 if (!hpet_force_user) {
306 hpet_print_force_info();
307 return;
308 }
309
310 pci_read_config_dword(dev, 0x68, &val);
311 /*
312 * Bit 7 is HPET enable bit.
313 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
314 */
315 if (val & 0x80) {
316 force_hpet_address = (val & ~0x3ff);
317 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
318 force_hpet_address);
319 return;
320 }
321
322 /*
323 * HPET is disabled. Trying enabling at FED00000 and check
324 * whether it sticks
325 */
326 val = 0xfed00000 | 0x80;
327 pci_write_config_dword(dev, 0x68, val);
328
329 pci_read_config_dword(dev, 0x68, &val);
330 if (val & 0x80) {
331 force_hpet_address = (val & ~0x3ff);
332 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
333 "0x%lx\n", force_hpet_address);
334 cached_dev = dev;
335 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
336 return;
337 }
338
339 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
340}
341
342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
343 vt8237_force_enable_hpet);
344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
345 vt8237_force_enable_hpet);
346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700,
347 vt8237_force_enable_hpet);
348
349static void ati_force_hpet_resume(void)
350{
351 pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
352 printk(KERN_DEBUG "Force enabled HPET at resume\n");
353}
354
355static u32 ati_ixp4x0_rev(struct pci_dev *dev)
356{
357 int err = 0;
358 u32 d = 0;
359 u8 b = 0;
360
361 err = pci_read_config_byte(dev, 0xac, &b);
362 b &= ~(1<<5);
363 err |= pci_write_config_byte(dev, 0xac, b);
364 err |= pci_read_config_dword(dev, 0x70, &d);
365 d |= 1<<8;
366 err |= pci_write_config_dword(dev, 0x70, d);
367 err |= pci_read_config_dword(dev, 0x8, &d);
368 d &= 0xff;
369 dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
370
371 WARN_ON_ONCE(err);
372
373 return d;
374}
375
376static void ati_force_enable_hpet(struct pci_dev *dev)
377{
378 u32 d, val;
379 u8 b;
380
381 if (hpet_address || force_hpet_address)
382 return;
383
384 if (!hpet_force_user) {
385 hpet_print_force_info();
386 return;
387 }
388
389 d = ati_ixp4x0_rev(dev);
390 if (d < 0x82)
391 return;
392
393 /* base address */
394 pci_write_config_dword(dev, 0x14, 0xfed00000);
395 pci_read_config_dword(dev, 0x14, &val);
396
397 /* enable interrupt */
398 outb(0x72, 0xcd6); b = inb(0xcd7);
399 b |= 0x1;
400 outb(0x72, 0xcd6); outb(b, 0xcd7);
401 outb(0x72, 0xcd6); b = inb(0xcd7);
402 if (!(b & 0x1))
403 return;
404 pci_read_config_dword(dev, 0x64, &d);
405 d |= (1<<10);
406 pci_write_config_dword(dev, 0x64, d);
407 pci_read_config_dword(dev, 0x64, &d);
408 if (!(d & (1<<10)))
409 return;
410
411 force_hpet_address = val;
412 force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
413 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
414 force_hpet_address);
415 cached_dev = dev;
416}
417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
418 ati_force_enable_hpet);
419
420/*
421 * Undocumented chipset feature taken from LinuxBIOS.
422 */
423static void nvidia_force_hpet_resume(void)
424{
425 pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
426 printk(KERN_DEBUG "Force enabled HPET at resume\n");
427}
428
429static void nvidia_force_enable_hpet(struct pci_dev *dev)
430{
431 u32 uninitialized_var(val);
432
433 if (hpet_address || force_hpet_address)
434 return;
435
436 if (!hpet_force_user) {
437 hpet_print_force_info();
438 return;
439 }
440
441 pci_write_config_dword(dev, 0x44, 0xfed00001);
442 pci_read_config_dword(dev, 0x44, &val);
443 force_hpet_address = val & 0xfffffffe;
444 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
445 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
446 force_hpet_address);
447 cached_dev = dev;
448 return;
449}
450
451/* ISA Bridges */
452DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
453 nvidia_force_enable_hpet);
454DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
455 nvidia_force_enable_hpet);
456
457/* LPC bridges */
458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
459 nvidia_force_enable_hpet);
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
461 nvidia_force_enable_hpet);
462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
463 nvidia_force_enable_hpet);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
465 nvidia_force_enable_hpet);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
467 nvidia_force_enable_hpet);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
469 nvidia_force_enable_hpet);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
471 nvidia_force_enable_hpet);
472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
473 nvidia_force_enable_hpet);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
475 nvidia_force_enable_hpet);
476
477void force_hpet_resume(void)
478{
479 switch (force_hpet_resume_type) {
480 case ICH_FORCE_HPET_RESUME:
481 ich_force_hpet_resume();
482 return;
483 case OLD_ICH_FORCE_HPET_RESUME:
484 old_ich_force_hpet_resume();
485 return;
486 case VT8237_FORCE_HPET_RESUME:
487 vt8237_force_hpet_resume();
488 return;
489 case NVIDIA_FORCE_HPET_RESUME:
490 nvidia_force_hpet_resume();
491 return;
492 case ATI_FORCE_HPET_RESUME:
493 ati_force_hpet_resume();
494 return;
495 default:
496 break;
497 }
498}
499
500/*
501 * HPET MSI on some boards (ATI SB700/SB800) has side effect on
502 * floppy DMA. Disable HPET MSI on such platforms.
503 * See erratum #27 (Misinterpreted MSI Requests May Result in
504 * Corrupted LPC DMA Data) in AMD Publication #46837,
505 * "SB700 Family Product Errata", Rev. 1.0, March 2010.
506 */
507static void force_disable_hpet_msi(struct pci_dev *unused)
508{
509 hpet_msi_disable = 1;
510}
511
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
513 force_disable_hpet_msi);
514
515#endif
516
517#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
518/* Set correct numa_node information for AMD NB functions */
519static void quirk_amd_nb_node(struct pci_dev *dev)
520{
521 struct pci_dev *nb_ht;
522 unsigned int devfn;
523 u32 node;
524 u32 val;
525
526 devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
527 nb_ht = pci_get_slot(dev->bus, devfn);
528 if (!nb_ht)
529 return;
530
531 pci_read_config_dword(nb_ht, 0x60, &val);
532 node = pcibus_to_node(dev->bus) | (val & 7);
533 /*
534 * Some hardware may return an invalid node ID,
535 * so check it first:
536 */
537 if (node_online(node))
538 set_dev_node(&dev->dev, node);
539 pci_dev_put(nb_ht);
540}
541
542DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
543 quirk_amd_nb_node);
544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
545 quirk_amd_nb_node);
546DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
547 quirk_amd_nb_node);
548DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC,
549 quirk_amd_nb_node);
550DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_HT,
551 quirk_amd_nb_node);
552DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MAP,
553 quirk_amd_nb_node);
554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM,
555 quirk_amd_nb_node);
556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC,
557 quirk_amd_nb_node);
558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_LINK,
559 quirk_amd_nb_node);
560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F0,
561 quirk_amd_nb_node);
562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F1,
563 quirk_amd_nb_node);
564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F2,
565 quirk_amd_nb_node);
566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3,
567 quirk_amd_nb_node);
568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4,
569 quirk_amd_nb_node);
570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
571 quirk_amd_nb_node);
572
573#endif
574
575#ifdef CONFIG_PCI
576/*
577 * Processor does not ensure DRAM scrub read/write sequence
578 * is atomic wrt accesses to CC6 save state area. Therefore
579 * if a concurrent scrub read/write access is to same address
580 * the entry may appear as if it is not written. This quirk
581 * applies to Fam16h models 00h-0Fh
582 *
583 * See "Revision Guide" for AMD F16h models 00h-0fh,
584 * document 51810 rev. 3.04, Nov 2013
585 */
586static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
587{
588 u32 val;
589
590 /*
591 * Suggested workaround:
592 * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
593 */
594 pci_read_config_dword(dev, 0x58, &val);
595 if (val & 0x1F) {
596 val &= ~(0x1F);
597 pci_write_config_dword(dev, 0x58, val);
598 }
599
600 pci_read_config_dword(dev, 0x5C, &val);
601 if (val & BIT(0)) {
602 val &= ~BIT(0);
603 pci_write_config_dword(dev, 0x5c, val);
604 }
605}
606
607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
608 amd_disable_seq_and_redirect_scrub);
609
610#endif