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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Intel CPU Microcode Update Driver for Linux
4 *
5 * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com>
6 * 2006 Shaohua Li <shaohua.li@intel.com>
7 *
8 * Intel CPU microcode early update for Linux
9 *
10 * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com>
11 * H Peter Anvin" <hpa@zytor.com>
12 */
13#define pr_fmt(fmt) "microcode: " fmt
14#include <linux/earlycpio.h>
15#include <linux/firmware.h>
16#include <linux/uaccess.h>
17#include <linux/initrd.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/cpu.h>
21#include <linux/uio.h>
22#include <linux/mm.h>
23
24#include <asm/cpu_device_id.h>
25#include <asm/processor.h>
26#include <asm/tlbflush.h>
27#include <asm/setup.h>
28#include <asm/msr.h>
29
30#include "internal.h"
31
32static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin";
33
34#define UCODE_BSP_LOADED ((struct microcode_intel *)0x1UL)
35
36/* Current microcode patch used in early patching on the APs. */
37static struct microcode_intel *ucode_patch_va __read_mostly;
38static struct microcode_intel *ucode_patch_late __read_mostly;
39
40/* last level cache size per core */
41static unsigned int llc_size_per_core __ro_after_init;
42
43/* microcode format is extended from prescott processors */
44struct extended_signature {
45 unsigned int sig;
46 unsigned int pf;
47 unsigned int cksum;
48};
49
50struct extended_sigtable {
51 unsigned int count;
52 unsigned int cksum;
53 unsigned int reserved[3];
54 struct extended_signature sigs[];
55};
56
57#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
58#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
59#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
60
61static inline unsigned int get_totalsize(struct microcode_header_intel *hdr)
62{
63 return hdr->datasize ? hdr->totalsize : DEFAULT_UCODE_TOTALSIZE;
64}
65
66static inline unsigned int exttable_size(struct extended_sigtable *et)
67{
68 return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;
69}
70
71void intel_collect_cpu_info(struct cpu_signature *sig)
72{
73 sig->sig = cpuid_eax(1);
74 sig->pf = 0;
75 sig->rev = intel_get_microcode_revision();
76
77 if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) {
78 unsigned int val[2];
79
80 /* get processor flags from MSR 0x17 */
81 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
82 sig->pf = 1 << ((val[1] >> 18) & 7);
83 }
84}
85EXPORT_SYMBOL_GPL(intel_collect_cpu_info);
86
87static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int sig2,
88 unsigned int pf2)
89{
90 if (s1->sig != sig2)
91 return false;
92
93 /* Processor flags are either both 0 or they intersect. */
94 return ((!s1->pf && !pf2) || (s1->pf & pf2));
95}
96
97bool intel_find_matching_signature(void *mc, struct cpu_signature *sig)
98{
99 struct microcode_header_intel *mc_hdr = mc;
100 struct extended_signature *ext_sig;
101 struct extended_sigtable *ext_hdr;
102 int i;
103
104 if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf))
105 return true;
106
107 /* Look for ext. headers: */
108 if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE)
109 return false;
110
111 ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE;
112 ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE;
113
114 for (i = 0; i < ext_hdr->count; i++) {
115 if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf))
116 return true;
117 ext_sig++;
118 }
119 return 0;
120}
121EXPORT_SYMBOL_GPL(intel_find_matching_signature);
122
123/**
124 * intel_microcode_sanity_check() - Sanity check microcode file.
125 * @mc: Pointer to the microcode file contents.
126 * @print_err: Display failure reason if true, silent if false.
127 * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file.
128 * Validate if the microcode header type matches with the type
129 * specified here.
130 *
131 * Validate certain header fields and verify if computed checksum matches
132 * with the one specified in the header.
133 *
134 * Return: 0 if the file passes all the checks, -EINVAL if any of the checks
135 * fail.
136 */
137int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type)
138{
139 unsigned long total_size, data_size, ext_table_size;
140 struct microcode_header_intel *mc_header = mc;
141 struct extended_sigtable *ext_header = NULL;
142 u32 sum, orig_sum, ext_sigcount = 0, i;
143 struct extended_signature *ext_sig;
144
145 total_size = get_totalsize(mc_header);
146 data_size = intel_microcode_get_datasize(mc_header);
147
148 if (data_size + MC_HEADER_SIZE > total_size) {
149 if (print_err)
150 pr_err("Error: bad microcode data file size.\n");
151 return -EINVAL;
152 }
153
154 if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) {
155 if (print_err)
156 pr_err("Error: invalid/unknown microcode update format. Header type %d\n",
157 mc_header->hdrver);
158 return -EINVAL;
159 }
160
161 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
162 if (ext_table_size) {
163 u32 ext_table_sum = 0;
164 u32 *ext_tablep;
165
166 if (ext_table_size < EXT_HEADER_SIZE ||
167 ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
168 if (print_err)
169 pr_err("Error: truncated extended signature table.\n");
170 return -EINVAL;
171 }
172
173 ext_header = mc + MC_HEADER_SIZE + data_size;
174 if (ext_table_size != exttable_size(ext_header)) {
175 if (print_err)
176 pr_err("Error: extended signature table size mismatch.\n");
177 return -EFAULT;
178 }
179
180 ext_sigcount = ext_header->count;
181
182 /*
183 * Check extended table checksum: the sum of all dwords that
184 * comprise a valid table must be 0.
185 */
186 ext_tablep = (u32 *)ext_header;
187
188 i = ext_table_size / sizeof(u32);
189 while (i--)
190 ext_table_sum += ext_tablep[i];
191
192 if (ext_table_sum) {
193 if (print_err)
194 pr_warn("Bad extended signature table checksum, aborting.\n");
195 return -EINVAL;
196 }
197 }
198
199 /*
200 * Calculate the checksum of update data and header. The checksum of
201 * valid update data and header including the extended signature table
202 * must be 0.
203 */
204 orig_sum = 0;
205 i = (MC_HEADER_SIZE + data_size) / sizeof(u32);
206 while (i--)
207 orig_sum += ((u32 *)mc)[i];
208
209 if (orig_sum) {
210 if (print_err)
211 pr_err("Bad microcode data checksum, aborting.\n");
212 return -EINVAL;
213 }
214
215 if (!ext_table_size)
216 return 0;
217
218 /*
219 * Check extended signature checksum: 0 => valid.
220 */
221 for (i = 0; i < ext_sigcount; i++) {
222 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
223 EXT_SIGNATURE_SIZE * i;
224
225 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) -
226 (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
227 if (sum) {
228 if (print_err)
229 pr_err("Bad extended signature checksum, aborting.\n");
230 return -EINVAL;
231 }
232 }
233 return 0;
234}
235EXPORT_SYMBOL_GPL(intel_microcode_sanity_check);
236
237static void update_ucode_pointer(struct microcode_intel *mc)
238{
239 kvfree(ucode_patch_va);
240
241 /*
242 * Save the virtual address for early loading and for eventual free
243 * on late loading.
244 */
245 ucode_patch_va = mc;
246}
247
248static void save_microcode_patch(struct microcode_intel *patch)
249{
250 unsigned int size = get_totalsize(&patch->hdr);
251 struct microcode_intel *mc;
252
253 mc = kvmemdup(patch, size, GFP_KERNEL);
254 if (mc)
255 update_ucode_pointer(mc);
256 else
257 pr_err("Unable to allocate microcode memory size: %u\n", size);
258}
259
260/* Scan blob for microcode matching the boot CPUs family, model, stepping */
261static __init struct microcode_intel *scan_microcode(void *data, size_t size,
262 struct ucode_cpu_info *uci,
263 bool save)
264{
265 struct microcode_header_intel *mc_header;
266 struct microcode_intel *patch = NULL;
267 u32 cur_rev = uci->cpu_sig.rev;
268 unsigned int mc_size;
269
270 for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) {
271 mc_header = (struct microcode_header_intel *)data;
272
273 mc_size = get_totalsize(mc_header);
274 if (!mc_size || mc_size > size ||
275 intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0)
276 break;
277
278 if (!intel_find_matching_signature(data, &uci->cpu_sig))
279 continue;
280
281 /*
282 * For saving the early microcode, find the matching revision which
283 * was loaded on the BSP.
284 *
285 * On the BSP during early boot, find a newer revision than
286 * actually loaded in the CPU.
287 */
288 if (save) {
289 if (cur_rev != mc_header->rev)
290 continue;
291 } else if (cur_rev >= mc_header->rev) {
292 continue;
293 }
294
295 patch = data;
296 cur_rev = mc_header->rev;
297 }
298
299 return size ? NULL : patch;
300}
301
302static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci,
303 struct microcode_intel *mc,
304 u32 *cur_rev)
305{
306 u32 rev;
307
308 if (!mc)
309 return UCODE_NFOUND;
310
311 /*
312 * Save us the MSR write below - which is a particular expensive
313 * operation - when the other hyperthread has updated the microcode
314 * already.
315 */
316 *cur_rev = intel_get_microcode_revision();
317 if (*cur_rev >= mc->hdr.rev) {
318 uci->cpu_sig.rev = *cur_rev;
319 return UCODE_OK;
320 }
321
322 /* write microcode via MSR 0x79 */
323 native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
324
325 rev = intel_get_microcode_revision();
326 if (rev != mc->hdr.rev)
327 return UCODE_ERROR;
328
329 uci->cpu_sig.rev = rev;
330 return UCODE_UPDATED;
331}
332
333static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci)
334{
335 struct microcode_intel *mc = uci->mc;
336 u32 cur_rev;
337
338 return __apply_microcode(uci, mc, &cur_rev);
339}
340
341static __init bool load_builtin_intel_microcode(struct cpio_data *cp)
342{
343 unsigned int eax = 1, ebx, ecx = 0, edx;
344 struct firmware fw;
345 char name[30];
346
347 if (IS_ENABLED(CONFIG_X86_32))
348 return false;
349
350 native_cpuid(&eax, &ebx, &ecx, &edx);
351
352 sprintf(name, "intel-ucode/%02x-%02x-%02x",
353 x86_family(eax), x86_model(eax), x86_stepping(eax));
354
355 if (firmware_request_builtin(&fw, name)) {
356 cp->size = fw.size;
357 cp->data = (void *)fw.data;
358 return true;
359 }
360 return false;
361}
362
363static __init struct microcode_intel *get_microcode_blob(struct ucode_cpu_info *uci, bool save)
364{
365 struct cpio_data cp;
366
367 intel_collect_cpu_info(&uci->cpu_sig);
368
369 if (!load_builtin_intel_microcode(&cp))
370 cp = find_microcode_in_initrd(ucode_path);
371
372 if (!(cp.data && cp.size))
373 return NULL;
374
375 return scan_microcode(cp.data, cp.size, uci, save);
376}
377
378/*
379 * Invoked from an early init call to save the microcode blob which was
380 * selected during early boot when mm was not usable. The microcode must be
381 * saved because initrd is going away. It's an early init call so the APs
382 * just can use the pointer and do not have to scan initrd/builtin firmware
383 * again.
384 */
385static int __init save_builtin_microcode(void)
386{
387 struct ucode_cpu_info uci;
388
389 if (xchg(&ucode_patch_va, NULL) != UCODE_BSP_LOADED)
390 return 0;
391
392 if (dis_ucode_ldr || boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
393 return 0;
394
395 uci.mc = get_microcode_blob(&uci, true);
396 if (uci.mc)
397 save_microcode_patch(uci.mc);
398 return 0;
399}
400early_initcall(save_builtin_microcode);
401
402/* Load microcode on BSP from initrd or builtin blobs */
403void __init load_ucode_intel_bsp(struct early_load_data *ed)
404{
405 struct ucode_cpu_info uci;
406
407 uci.mc = get_microcode_blob(&uci, false);
408 ed->old_rev = uci.cpu_sig.rev;
409
410 if (uci.mc && apply_microcode_early(&uci) == UCODE_UPDATED) {
411 ucode_patch_va = UCODE_BSP_LOADED;
412 ed->new_rev = uci.cpu_sig.rev;
413 }
414}
415
416void load_ucode_intel_ap(void)
417{
418 struct ucode_cpu_info uci;
419
420 uci.mc = ucode_patch_va;
421 if (uci.mc)
422 apply_microcode_early(&uci);
423}
424
425/* Reload microcode on resume */
426void reload_ucode_intel(void)
427{
428 struct ucode_cpu_info uci = { .mc = ucode_patch_va, };
429
430 if (uci.mc)
431 apply_microcode_early(&uci);
432}
433
434static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
435{
436 intel_collect_cpu_info(csig);
437 return 0;
438}
439
440static enum ucode_state apply_microcode_late(int cpu)
441{
442 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
443 struct microcode_intel *mc = ucode_patch_late;
444 enum ucode_state ret;
445 u32 cur_rev;
446
447 if (WARN_ON_ONCE(smp_processor_id() != cpu))
448 return UCODE_ERROR;
449
450 ret = __apply_microcode(uci, mc, &cur_rev);
451 if (ret != UCODE_UPDATED && ret != UCODE_OK)
452 return ret;
453
454 cpu_data(cpu).microcode = uci->cpu_sig.rev;
455 if (!cpu)
456 boot_cpu_data.microcode = uci->cpu_sig.rev;
457
458 return ret;
459}
460
461static bool ucode_validate_minrev(struct microcode_header_intel *mc_header)
462{
463 int cur_rev = boot_cpu_data.microcode;
464
465 /*
466 * When late-loading, ensure the header declares a minimum revision
467 * required to perform a late-load. The previously reserved field
468 * is 0 in older microcode blobs.
469 */
470 if (!mc_header->min_req_ver) {
471 pr_info("Unsafe microcode update: Microcode header does not specify a required min version\n");
472 return false;
473 }
474
475 /*
476 * Check whether the current revision is either greater or equal to
477 * to the minimum revision specified in the header.
478 */
479 if (cur_rev < mc_header->min_req_ver) {
480 pr_info("Unsafe microcode update: Current revision 0x%x too old\n", cur_rev);
481 pr_info("Current should be at 0x%x or higher. Use early loading instead\n", mc_header->min_req_ver);
482 return false;
483 }
484 return true;
485}
486
487static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter)
488{
489 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
490 bool is_safe, new_is_safe = false;
491 int cur_rev = uci->cpu_sig.rev;
492 unsigned int curr_mc_size = 0;
493 u8 *new_mc = NULL, *mc = NULL;
494
495 while (iov_iter_count(iter)) {
496 struct microcode_header_intel mc_header;
497 unsigned int mc_size, data_size;
498 u8 *data;
499
500 if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) {
501 pr_err("error! Truncated or inaccessible header in microcode data file\n");
502 goto fail;
503 }
504
505 mc_size = get_totalsize(&mc_header);
506 if (mc_size < sizeof(mc_header)) {
507 pr_err("error! Bad data in microcode data file (totalsize too small)\n");
508 goto fail;
509 }
510 data_size = mc_size - sizeof(mc_header);
511 if (data_size > iov_iter_count(iter)) {
512 pr_err("error! Bad data in microcode data file (truncated file?)\n");
513 goto fail;
514 }
515
516 /* For performance reasons, reuse mc area when possible */
517 if (!mc || mc_size > curr_mc_size) {
518 kvfree(mc);
519 mc = kvmalloc(mc_size, GFP_KERNEL);
520 if (!mc)
521 goto fail;
522 curr_mc_size = mc_size;
523 }
524
525 memcpy(mc, &mc_header, sizeof(mc_header));
526 data = mc + sizeof(mc_header);
527 if (!copy_from_iter_full(data, data_size, iter) ||
528 intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0)
529 goto fail;
530
531 if (cur_rev >= mc_header.rev)
532 continue;
533
534 if (!intel_find_matching_signature(mc, &uci->cpu_sig))
535 continue;
536
537 is_safe = ucode_validate_minrev(&mc_header);
538 if (force_minrev && !is_safe)
539 continue;
540
541 kvfree(new_mc);
542 cur_rev = mc_header.rev;
543 new_mc = mc;
544 new_is_safe = is_safe;
545 mc = NULL;
546 }
547
548 if (iov_iter_count(iter))
549 goto fail;
550
551 kvfree(mc);
552 if (!new_mc)
553 return UCODE_NFOUND;
554
555 ucode_patch_late = (struct microcode_intel *)new_mc;
556 return new_is_safe ? UCODE_NEW_SAFE : UCODE_NEW;
557
558fail:
559 kvfree(mc);
560 kvfree(new_mc);
561 return UCODE_ERROR;
562}
563
564static bool is_blacklisted(unsigned int cpu)
565{
566 struct cpuinfo_x86 *c = &cpu_data(cpu);
567
568 /*
569 * Late loading on model 79 with microcode revision less than 0x0b000021
570 * and LLC size per core bigger than 2.5MB may result in a system hang.
571 * This behavior is documented in item BDX90, #334165 (Intel Xeon
572 * Processor E7-8800/4800 v4 Product Family).
573 */
574 if (c->x86_vfm == INTEL_BROADWELL_X &&
575 c->x86_stepping == 0x01 &&
576 llc_size_per_core > 2621440 &&
577 c->microcode < 0x0b000021) {
578 pr_err_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
579 pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
580 return true;
581 }
582
583 return false;
584}
585
586static enum ucode_state request_microcode_fw(int cpu, struct device *device)
587{
588 struct cpuinfo_x86 *c = &cpu_data(cpu);
589 const struct firmware *firmware;
590 struct iov_iter iter;
591 enum ucode_state ret;
592 struct kvec kvec;
593 char name[30];
594
595 if (is_blacklisted(cpu))
596 return UCODE_NFOUND;
597
598 sprintf(name, "intel-ucode/%02x-%02x-%02x",
599 c->x86, c->x86_model, c->x86_stepping);
600
601 if (request_firmware_direct(&firmware, name, device)) {
602 pr_debug("data file %s load failed\n", name);
603 return UCODE_NFOUND;
604 }
605
606 kvec.iov_base = (void *)firmware->data;
607 kvec.iov_len = firmware->size;
608 iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size);
609 ret = parse_microcode_blobs(cpu, &iter);
610
611 release_firmware(firmware);
612
613 return ret;
614}
615
616static void finalize_late_load(int result)
617{
618 if (!result)
619 update_ucode_pointer(ucode_patch_late);
620 else
621 kvfree(ucode_patch_late);
622 ucode_patch_late = NULL;
623}
624
625static struct microcode_ops microcode_intel_ops = {
626 .request_microcode_fw = request_microcode_fw,
627 .collect_cpu_info = collect_cpu_info,
628 .apply_microcode = apply_microcode_late,
629 .finalize_late_load = finalize_late_load,
630 .use_nmi = IS_ENABLED(CONFIG_X86_64),
631};
632
633static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c)
634{
635 u64 llc_size = c->x86_cache_size * 1024ULL;
636
637 do_div(llc_size, topology_num_cores_per_package());
638 llc_size_per_core = (unsigned int)llc_size;
639}
640
641struct microcode_ops * __init init_intel_microcode(void)
642{
643 struct cpuinfo_x86 *c = &boot_cpu_data;
644
645 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
646 cpu_has(c, X86_FEATURE_IA64)) {
647 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
648 return NULL;
649 }
650
651 calc_llc_size_per_core(c);
652
653 return µcode_intel_ops;
654}
1/*
2 * Intel CPU Microcode Update Driver for Linux
3 *
4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
5 * 2006 Shaohua Li <shaohua.li@intel.com>
6 *
7 * This driver allows to upgrade microcode on Intel processors
8 * belonging to IA-32 family - PentiumPro, Pentium II,
9 * Pentium III, Xeon, Pentium 4, etc.
10 *
11 * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 * Software Developer's Manual
13 * Order Number 253668 or free download from:
14 *
15 * http://developer.intel.com/Assets/PDF/manual/253668.pdf
16 *
17 * For more information, go to http://www.urbanmyth.org/microcode
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 * Initial release.
26 * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 * Added read() support + cleanups.
28 * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 * Added 'device trimming' support. open(O_WRONLY) zeroes
30 * and frees the saved copy of applied microcode.
31 * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 * Made to use devfs (/dev/cpu/microcode) + cleanups.
33 * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 * Added misc device support (now uses both devfs and misc).
35 * Added MICROCODE_IOCFREE ioctl to clear memory.
36 * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 * Messages for error cases (non Intel & no suitable microcode).
38 * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 * Removed ->release(). Removed exclusive open and status bitmap.
40 * Added microcode_rwsem to serialize read()/write()/ioctl().
41 * Removed global kernel lock usage.
42 * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 * Write 0 to 0x8B msr and then cpuid before reading revision,
44 * so that it works even if there were no update done by the
45 * BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 * to be 0 on my machine which is why it worked even when I
47 * disabled update by the BIOS)
48 * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 * Tigran Aivazian <tigran@veritas.com>
51 * Intel Pentium 4 processor support and bugfixes.
52 * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 * Bugfix for HT (Hyper-Threading) enabled processors
54 * whereby processor resources are shared by all logical processors
55 * in a single CPU package.
56 * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 * Tigran Aivazian <tigran@veritas.com>,
58 * Serialize updates as required on HT processors due to
59 * speculative nature of implementation.
60 * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 * Fix the panic when writing zero-length microcode chunk.
62 * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
63 * Jun Nakajima <jun.nakajima@intel.com>
64 * Support for the microcode updates in the new format.
65 * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
67 * because we no longer hold a copy of applied microcode
68 * in kernel memory.
69 * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 * Fix sigmatch() macro to handle old CPUs with pf == 0.
71 * Thanks to Stuart Swales for pointing out this bug.
72 */
73
74#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
75
76#include <linux/firmware.h>
77#include <linux/uaccess.h>
78#include <linux/kernel.h>
79#include <linux/module.h>
80#include <linux/vmalloc.h>
81
82#include <asm/microcode_intel.h>
83#include <asm/processor.h>
84#include <asm/msr.h>
85
86MODULE_DESCRIPTION("Microcode Update Driver");
87MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
88MODULE_LICENSE("GPL");
89
90static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
91{
92 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
93 unsigned int val[2];
94
95 memset(csig, 0, sizeof(*csig));
96
97 csig->sig = cpuid_eax(0x00000001);
98
99 if ((c->x86_model >= 5) || (c->x86 > 6)) {
100 /* get processor flags from MSR 0x17 */
101 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
102 csig->pf = 1 << ((val[1] >> 18) & 7);
103 }
104
105 csig->rev = c->microcode;
106 pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
107 cpu_num, csig->sig, csig->pf, csig->rev);
108
109 return 0;
110}
111
112/*
113 * return 0 - no update found
114 * return 1 - found update
115 */
116static int get_matching_mc(struct microcode_intel *mc_intel, int cpu)
117{
118 struct cpu_signature cpu_sig;
119 unsigned int csig, cpf, crev;
120
121 collect_cpu_info(cpu, &cpu_sig);
122
123 csig = cpu_sig.sig;
124 cpf = cpu_sig.pf;
125 crev = cpu_sig.rev;
126
127 return get_matching_microcode(csig, cpf, mc_intel, crev);
128}
129
130int apply_microcode(int cpu)
131{
132 struct microcode_intel *mc_intel;
133 struct ucode_cpu_info *uci;
134 unsigned int val[2];
135 int cpu_num = raw_smp_processor_id();
136 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
137
138 uci = ucode_cpu_info + cpu;
139 mc_intel = uci->mc;
140
141 /* We should bind the task to the CPU */
142 BUG_ON(cpu_num != cpu);
143
144 if (mc_intel == NULL)
145 return 0;
146
147 /*
148 * Microcode on this CPU could be updated earlier. Only apply the
149 * microcode patch in mc_intel when it is newer than the one on this
150 * CPU.
151 */
152 if (get_matching_mc(mc_intel, cpu) == 0)
153 return 0;
154
155 /* write microcode via MSR 0x79 */
156 wrmsr(MSR_IA32_UCODE_WRITE,
157 (unsigned long) mc_intel->bits,
158 (unsigned long) mc_intel->bits >> 16 >> 16);
159 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
160
161 /* As documented in the SDM: Do a CPUID 1 here */
162 sync_core();
163
164 /* get the current revision from MSR 0x8B */
165 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
166
167 if (val[1] != mc_intel->hdr.rev) {
168 pr_err("CPU%d update to revision 0x%x failed\n",
169 cpu_num, mc_intel->hdr.rev);
170 return -1;
171 }
172 pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
173 cpu_num, val[1],
174 mc_intel->hdr.date & 0xffff,
175 mc_intel->hdr.date >> 24,
176 (mc_intel->hdr.date >> 16) & 0xff);
177
178 uci->cpu_sig.rev = val[1];
179 c->microcode = val[1];
180
181 return 0;
182}
183
184static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
185 int (*get_ucode_data)(void *, const void *, size_t))
186{
187 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
188 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
189 int new_rev = uci->cpu_sig.rev;
190 unsigned int leftover = size;
191 enum ucode_state state = UCODE_OK;
192 unsigned int curr_mc_size = 0;
193 unsigned int csig, cpf;
194
195 while (leftover) {
196 struct microcode_header_intel mc_header;
197 unsigned int mc_size;
198
199 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
200 break;
201
202 mc_size = get_totalsize(&mc_header);
203 if (!mc_size || mc_size > leftover) {
204 pr_err("error! Bad data in microcode data file\n");
205 break;
206 }
207
208 /* For performance reasons, reuse mc area when possible */
209 if (!mc || mc_size > curr_mc_size) {
210 vfree(mc);
211 mc = vmalloc(mc_size);
212 if (!mc)
213 break;
214 curr_mc_size = mc_size;
215 }
216
217 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
218 microcode_sanity_check(mc, 1) < 0) {
219 break;
220 }
221
222 csig = uci->cpu_sig.sig;
223 cpf = uci->cpu_sig.pf;
224 if (get_matching_microcode(csig, cpf, mc, new_rev)) {
225 vfree(new_mc);
226 new_rev = mc_header.rev;
227 new_mc = mc;
228 mc = NULL; /* trigger new vmalloc */
229 }
230
231 ucode_ptr += mc_size;
232 leftover -= mc_size;
233 }
234
235 vfree(mc);
236
237 if (leftover) {
238 vfree(new_mc);
239 state = UCODE_ERROR;
240 goto out;
241 }
242
243 if (!new_mc) {
244 state = UCODE_NFOUND;
245 goto out;
246 }
247
248 vfree(uci->mc);
249 uci->mc = (struct microcode_intel *)new_mc;
250
251 /*
252 * If early loading microcode is supported, save this mc into
253 * permanent memory. So it will be loaded early when a CPU is hot added
254 * or resumes.
255 */
256 save_mc_for_early(new_mc);
257
258 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
259 cpu, new_rev, uci->cpu_sig.rev);
260out:
261 return state;
262}
263
264static int get_ucode_fw(void *to, const void *from, size_t n)
265{
266 memcpy(to, from, n);
267 return 0;
268}
269
270static enum ucode_state request_microcode_fw(int cpu, struct device *device,
271 bool refresh_fw)
272{
273 char name[30];
274 struct cpuinfo_x86 *c = &cpu_data(cpu);
275 const struct firmware *firmware;
276 enum ucode_state ret;
277
278 sprintf(name, "intel-ucode/%02x-%02x-%02x",
279 c->x86, c->x86_model, c->x86_mask);
280
281 if (request_firmware_direct(&firmware, name, device)) {
282 pr_debug("data file %s load failed\n", name);
283 return UCODE_NFOUND;
284 }
285
286 ret = generic_load_microcode(cpu, (void *)firmware->data,
287 firmware->size, &get_ucode_fw);
288
289 release_firmware(firmware);
290
291 return ret;
292}
293
294static int get_ucode_user(void *to, const void *from, size_t n)
295{
296 return copy_from_user(to, from, n);
297}
298
299static enum ucode_state
300request_microcode_user(int cpu, const void __user *buf, size_t size)
301{
302 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
303}
304
305static void microcode_fini_cpu(int cpu)
306{
307 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
308
309 vfree(uci->mc);
310 uci->mc = NULL;
311}
312
313static struct microcode_ops microcode_intel_ops = {
314 .request_microcode_user = request_microcode_user,
315 .request_microcode_fw = request_microcode_fw,
316 .collect_cpu_info = collect_cpu_info,
317 .apply_microcode = apply_microcode,
318 .microcode_fini_cpu = microcode_fini_cpu,
319};
320
321struct microcode_ops * __init init_intel_microcode(void)
322{
323 struct cpuinfo_x86 *c = &cpu_data(0);
324
325 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
326 cpu_has(c, X86_FEATURE_IA64)) {
327 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
328 return NULL;
329 }
330
331 return µcode_intel_ops;
332}
333