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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mm/proc-sa110.S
4 *
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * MMU functions for SA110
9 *
10 * These are the low level assembler for performing cache and TLB
11 * functions on the StrongARM-110.
12 */
13#include <linux/linkage.h>
14#include <linux/init.h>
15#include <linux/cfi_types.h>
16#include <linux/pgtable.h>
17#include <asm/assembler.h>
18#include <asm/asm-offsets.h>
19#include <asm/hwcap.h>
20#include <mach/hardware.h>
21#include <asm/pgtable-hwdef.h>
22#include <asm/ptrace.h>
23
24#include "proc-macros.S"
25
26/*
27 * the cache line size of the I and D cache
28 */
29#define DCACHELINESIZE 32
30
31 .text
32
33/*
34 * cpu_sa110_proc_init()
35 */
36SYM_TYPED_FUNC_START(cpu_sa110_proc_init)
37 mov r0, #0
38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
39 ret lr
40SYM_FUNC_END(cpu_sa110_proc_init)
41
42/*
43 * cpu_sa110_proc_fin()
44 */
45SYM_TYPED_FUNC_START(cpu_sa110_proc_fin)
46 mov r0, #0
47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x000e @ ............wca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ret lr
53SYM_FUNC_END(cpu_sa110_proc_fin)
54
55/*
56 * cpu_sa110_reset(loc)
57 *
58 * Perform a soft reset of the system. Put the CPU into the
59 * same state as it would be if it had been reset, and branch
60 * to what would be the reset vector.
61 *
62 * loc: location to jump to for soft reset
63 */
64 .align 5
65 .pushsection .idmap.text, "ax"
66SYM_TYPED_FUNC_START(cpu_sa110_reset)
67 mov ip, #0
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70#ifdef CONFIG_MMU
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
72#endif
73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
74 bic ip, ip, #0x000f @ ............wcam
75 bic ip, ip, #0x1100 @ ...i...s........
76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
77 ret r0
78SYM_FUNC_END(cpu_sa110_reset)
79 .popsection
80
81/*
82 * cpu_sa110_do_idle(type)
83 *
84 * Cause the processor to idle
85 *
86 * type: call type:
87 * 0 = slow idle
88 * 1 = fast idle
89 * 2 = switch to slow processor clock
90 * 3 = switch to fast processor clock
91 */
92 .align 5
93
94SYM_TYPED_FUNC_START(cpu_sa110_do_idle)
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
96 ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
97 ldr r1, [r1, #0] @ force switch to MCLK
98 mov r0, r0 @ safety
99 mov r0, r0 @ safety
100 mov r0, r0 @ safety
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mov r0, r0 @ safety
103 mov r0, r0 @ safety
104 mov r0, r0 @ safety
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
106 ret lr
107SYM_FUNC_END(cpu_sa110_do_idle)
108
109/* ================================= CACHE ================================ */
110
111/*
112 * cpu_sa110_dcache_clean_area(addr,sz)
113 *
114 * Clean the specified entry of any caches such that the MMU
115 * translation fetches will obtain correct data.
116 *
117 * addr: cache-unaligned virtual address
118 */
119 .align 5
120SYM_TYPED_FUNC_START(cpu_sa110_dcache_clean_area)
1211: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
122 add r0, r0, #DCACHELINESIZE
123 subs r1, r1, #DCACHELINESIZE
124 bhi 1b
125 ret lr
126SYM_FUNC_END(cpu_sa110_dcache_clean_area)
127
128/* =============================== PageTable ============================== */
129
130/*
131 * cpu_sa110_switch_mm(pgd)
132 *
133 * Set the translation base pointer to be as described by pgd.
134 *
135 * pgd: new page tables
136 */
137 .align 5
138SYM_TYPED_FUNC_START(cpu_sa110_switch_mm)
139#ifdef CONFIG_MMU
140 str lr, [sp, #-4]!
141 bl v4wb_flush_kern_cache_all @ clears IP
142 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
144 ldr pc, [sp], #4
145#else
146 ret lr
147#endif
148SYM_FUNC_END(cpu_sa110_switch_mm)
149
150/*
151 * cpu_sa110_set_pte_ext(ptep, pte, ext)
152 *
153 * Set a PTE and flush it out
154 */
155 .align 5
156SYM_TYPED_FUNC_START(cpu_sa110_set_pte_ext)
157#ifdef CONFIG_MMU
158 armv3_set_pte_ext wc_disable=0
159 mov r0, r0
160 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
161 mcr p15, 0, r0, c7, c10, 4 @ drain WB
162#endif
163 ret lr
164SYM_FUNC_END(cpu_sa110_set_pte_ext)
165
166 .type __sa110_setup, #function
167__sa110_setup:
168 mov r10, #0
169 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
170 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
171#ifdef CONFIG_MMU
172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
173#endif
174
175 adr r5, sa110_crval
176 ldmia r5, {r5, r6}
177 mrc p15, 0, r0, c1, c0 @ get control register v4
178 bic r0, r0, r5
179 orr r0, r0, r6
180 ret lr
181 .size __sa110_setup, . - __sa110_setup
182
183 /*
184 * R
185 * .RVI ZFRS BLDP WCAM
186 * ..01 0001 ..11 1101
187 *
188 */
189 .type sa110_crval, #object
190sa110_crval:
191 crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
192
193 __INITDATA
194
195 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
196 define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
197
198 .section ".rodata"
199
200 string cpu_arch_name, "armv4"
201 string cpu_elf_name, "v4"
202 string cpu_sa110_name, "StrongARM-110"
203
204 .align
205
206 .section ".proc.info.init", "a"
207
208 .type __sa110_proc_info,#object
209__sa110_proc_info:
210 .long 0x4401a100
211 .long 0xfffffff0
212 .long PMD_TYPE_SECT | \
213 PMD_SECT_BUFFERABLE | \
214 PMD_SECT_CACHEABLE | \
215 PMD_SECT_AP_WRITE | \
216 PMD_SECT_AP_READ
217 .long PMD_TYPE_SECT | \
218 PMD_SECT_AP_WRITE | \
219 PMD_SECT_AP_READ
220 initfn __sa110_setup, __sa110_proc_info
221 .long cpu_arch_name
222 .long cpu_elf_name
223 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
224 .long cpu_sa110_name
225 .long sa110_processor_functions
226 .long v4wb_tlb_fns
227 .long v4wb_user_fns
228 .long v4wb_cache_fns
229 .size __sa110_proc_info, . - __sa110_proc_info
1/*
2 * linux/arch/arm/mm/proc-sa110.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * MMU functions for SA110
12 *
13 * These are the low level assembler for performing cache and TLB
14 * functions on the StrongARM-110.
15 */
16#include <linux/linkage.h>
17#include <linux/init.h>
18#include <asm/assembler.h>
19#include <asm/asm-offsets.h>
20#include <asm/hwcap.h>
21#include <mach/hardware.h>
22#include <asm/pgtable-hwdef.h>
23#include <asm/pgtable.h>
24#include <asm/ptrace.h>
25
26#include "proc-macros.S"
27
28/*
29 * the cache line size of the I and D cache
30 */
31#define DCACHELINESIZE 32
32
33 .text
34
35/*
36 * cpu_sa110_proc_init()
37 */
38ENTRY(cpu_sa110_proc_init)
39 mov r0, #0
40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
41 mov pc, lr
42
43/*
44 * cpu_sa110_proc_fin()
45 */
46ENTRY(cpu_sa110_proc_fin)
47 mov r0, #0
48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
50 bic r0, r0, #0x1000 @ ...i............
51 bic r0, r0, #0x000e @ ............wca.
52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
53 mov pc, lr
54
55/*
56 * cpu_sa110_reset(loc)
57 *
58 * Perform a soft reset of the system. Put the CPU into the
59 * same state as it would be if it had been reset, and branch
60 * to what would be the reset vector.
61 *
62 * loc: location to jump to for soft reset
63 */
64 .align 5
65 .pushsection .idmap.text, "ax"
66ENTRY(cpu_sa110_reset)
67 mov ip, #0
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70#ifdef CONFIG_MMU
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
72#endif
73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
74 bic ip, ip, #0x000f @ ............wcam
75 bic ip, ip, #0x1100 @ ...i...s........
76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
77 mov pc, r0
78ENDPROC(cpu_sa110_reset)
79 .popsection
80
81/*
82 * cpu_sa110_do_idle(type)
83 *
84 * Cause the processor to idle
85 *
86 * type: call type:
87 * 0 = slow idle
88 * 1 = fast idle
89 * 2 = switch to slow processor clock
90 * 3 = switch to fast processor clock
91 */
92 .align 5
93
94ENTRY(cpu_sa110_do_idle)
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
96 ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
97 ldr r1, [r1, #0] @ force switch to MCLK
98 mov r0, r0 @ safety
99 mov r0, r0 @ safety
100 mov r0, r0 @ safety
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mov r0, r0 @ safety
103 mov r0, r0 @ safety
104 mov r0, r0 @ safety
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
106 mov pc, lr
107
108/* ================================= CACHE ================================ */
109
110/*
111 * cpu_sa110_dcache_clean_area(addr,sz)
112 *
113 * Clean the specified entry of any caches such that the MMU
114 * translation fetches will obtain correct data.
115 *
116 * addr: cache-unaligned virtual address
117 */
118 .align 5
119ENTRY(cpu_sa110_dcache_clean_area)
1201: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
121 add r0, r0, #DCACHELINESIZE
122 subs r1, r1, #DCACHELINESIZE
123 bhi 1b
124 mov pc, lr
125
126/* =============================== PageTable ============================== */
127
128/*
129 * cpu_sa110_switch_mm(pgd)
130 *
131 * Set the translation base pointer to be as described by pgd.
132 *
133 * pgd: new page tables
134 */
135 .align 5
136ENTRY(cpu_sa110_switch_mm)
137#ifdef CONFIG_MMU
138 str lr, [sp, #-4]!
139 bl v4wb_flush_kern_cache_all @ clears IP
140 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
142 ldr pc, [sp], #4
143#else
144 mov pc, lr
145#endif
146
147/*
148 * cpu_sa110_set_pte_ext(ptep, pte, ext)
149 *
150 * Set a PTE and flush it out
151 */
152 .align 5
153ENTRY(cpu_sa110_set_pte_ext)
154#ifdef CONFIG_MMU
155 armv3_set_pte_ext wc_disable=0
156 mov r0, r0
157 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
158 mcr p15, 0, r0, c7, c10, 4 @ drain WB
159#endif
160 mov pc, lr
161
162 .type __sa110_setup, #function
163__sa110_setup:
164 mov r10, #0
165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
166 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
167#ifdef CONFIG_MMU
168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
169#endif
170
171 adr r5, sa110_crval
172 ldmia r5, {r5, r6}
173 mrc p15, 0, r0, c1, c0 @ get control register v4
174 bic r0, r0, r5
175 orr r0, r0, r6
176 mov pc, lr
177 .size __sa110_setup, . - __sa110_setup
178
179 /*
180 * R
181 * .RVI ZFRS BLDP WCAM
182 * ..01 0001 ..11 1101
183 *
184 */
185 .type sa110_crval, #object
186sa110_crval:
187 crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
188
189 __INITDATA
190
191 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
192 define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
193
194 .section ".rodata"
195
196 string cpu_arch_name, "armv4"
197 string cpu_elf_name, "v4"
198 string cpu_sa110_name, "StrongARM-110"
199
200 .align
201
202 .section ".proc.info.init", #alloc, #execinstr
203
204 .type __sa110_proc_info,#object
205__sa110_proc_info:
206 .long 0x4401a100
207 .long 0xfffffff0
208 .long PMD_TYPE_SECT | \
209 PMD_SECT_BUFFERABLE | \
210 PMD_SECT_CACHEABLE | \
211 PMD_SECT_AP_WRITE | \
212 PMD_SECT_AP_READ
213 .long PMD_TYPE_SECT | \
214 PMD_SECT_AP_WRITE | \
215 PMD_SECT_AP_READ
216 b __sa110_setup
217 .long cpu_arch_name
218 .long cpu_elf_name
219 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
220 .long cpu_sa110_name
221 .long sa110_processor_functions
222 .long v4wb_tlb_fns
223 .long v4wb_user_fns
224 .long v4wb_cache_fns
225 .size __sa110_proc_info, . - __sa110_proc_info