1/*
  2 * Copyright 2013 Armadeus Systems - <support@armadeus.com>
  3 *
  4 * The code contained herein is licensed under the GNU General Public
  5 * License. You may obtain a copy of the GNU General Public License
  6 * Version 2 or later at the following locations:
  7 *
  8 * http://www.opensource.org/licenses/gpl-license.html
  9 * http://www.gnu.org/copyleft/gpl.html
 10 */
 11
 12/* APF27Dev is a docking board for the APF27 SOM */
 13#include "imx27-apf27.dts"
 14
 15/ {
 16	model = "Armadeus Systems APF27Dev docking/development board";
 17	compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27";
 18
 19	display: display {
 20		model = "Chimei-LW700AT9003";
 21		native-mode = <&timing0>;
 22		bits-per-pixel = <16>;  /* non-standard but required */
 23		fsl,pcr = <0xfae80083>;	/* non-standard but required */
 24		display-timings {
 25			timing0: 800x480 {
 26				clock-frequency = <33000033>;
 27				hactive = <800>;
 28				vactive = <480>;
 29				hback-porch = <96>;
 30				hfront-porch = <96>;
 31				vback-porch = <20>;
 32				vfront-porch = <21>;
 33				hsync-len = <64>;
 34				vsync-len = <4>;
 35			};
 36		};
 37	};
 38
 39	gpio-keys {
 40		compatible = "gpio-keys";
 41		pinctrl-names = "default";
 42		pinctrl-0 = <&pinctrl_gpio_keys>;
 43
 44		user-key {
 45			label = "user";
 46			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 47			linux,code = <276>; /* BTN_EXTRA */
 48		};
 49	};
 50
 51	leds {
 52		compatible = "gpio-leds";
 53		pinctrl-names = "default";
 54		pinctrl-0 = <&pinctrl_gpio_leds>;
 55
 56		user {
 57			label = "Heartbeat";
 58			gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
 59			linux,default-trigger = "heartbeat";
 60		};
 61	};
 62};
 63
 64&cspi1 {
 65	fsl,spi-num-chipselects = <1>;
 66	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 67	pinctrl-names = "default";
 68	pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
 69	status = "okay";
 70};
 71
 72&cspi2 {
 73	fsl,spi-num-chipselects = <3>;
 74	cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>,
 75		   <&gpio4 27 GPIO_ACTIVE_LOW>,
 76		   <&gpio2 17 GPIO_ACTIVE_LOW>;
 77	pinctrl-names = "default";
 78	pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>;
 79	status = "okay";
 80};
 81
 82&fb {
 83	display = <&display>;
 84	fsl,dmacr = <0x00020010>;
 85	pinctrl-names = "default";
 86	pinctrl-0 = <&pinctrl_imxfb1>;
 87	status = "okay";
 88};
 89
 90&i2c1 {
 91	clock-frequency = <400000>;
 92	pinctrl-names = "default";
 93	pinctrl-0 = <&pinctrl_i2c1>;
 94	status = "okay";
 95
 96	rtc@68 {
 97		compatible = "dallas,ds1374";
 98		reg = <0x68>;
 99	};
100};
101
102&i2c2 {
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_i2c2>;
105	status = "okay";
106};
107
108&iomuxc {
109	imx27-apf27dev {
110		pinctrl_cspi1: cspi1grp {
111			fsl,pins = <
112				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
113				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
114				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
115			>;
116		};
117
118		pinctrl_cspi1_cs: cspi1csgrp {
119			fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
120		};
121
122		pinctrl_cspi2: cspi2grp {
123			fsl,pins = <
124				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
125				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
126				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
127			>;
128		};
129
130		pinctrl_cspi2_cs: cspi2csgrp {
131			fsl,pins = <
132				MX27_PAD_CSI_D5__GPIO2_17 0x0
133				MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
134				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
135			>;
136		};
137
138		pinctrl_gpio_leds: gpioledsgrp {
139			fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
140		};
141
142		pinctrl_gpio_keys: gpiokeysgrp {
143			fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
144		};
145
146		pinctrl_imxfb1: imxfbgrp {
147			fsl,pins = <
148				MX27_PAD_CLS__CLS 0x0
149				MX27_PAD_CONTRAST__CONTRAST 0x0
150				MX27_PAD_LD0__LD0 0x0
151				MX27_PAD_LD1__LD1 0x0
152				MX27_PAD_LD2__LD2 0x0
153				MX27_PAD_LD3__LD3 0x0
154				MX27_PAD_LD4__LD4 0x0
155				MX27_PAD_LD5__LD5 0x0
156				MX27_PAD_LD6__LD6 0x0
157				MX27_PAD_LD7__LD7 0x0
158				MX27_PAD_LD8__LD8 0x0
159				MX27_PAD_LD9__LD9 0x0
160				MX27_PAD_LD10__LD10 0x0
161				MX27_PAD_LD11__LD11 0x0
162				MX27_PAD_LD12__LD12 0x0
163				MX27_PAD_LD13__LD13 0x0
164				MX27_PAD_LD14__LD14 0x0
165				MX27_PAD_LD15__LD15 0x0
166				MX27_PAD_LD16__LD16 0x0
167				MX27_PAD_LD17__LD17 0x0
168				MX27_PAD_LSCLK__LSCLK 0x0
169				MX27_PAD_OE_ACD__OE_ACD 0x0
170				MX27_PAD_PS__PS 0x0
171				MX27_PAD_REV__REV 0x0
172				MX27_PAD_SPL_SPR__SPL_SPR 0x0
173				MX27_PAD_HSYNC__HSYNC 0x0
174				MX27_PAD_VSYNC__VSYNC 0x0
175			>;
176		};
177
178		pinctrl_i2c1: i2c1grp {
179			fsl,pins = <
180				MX27_PAD_I2C_DATA__I2C_DATA 0x0
181				MX27_PAD_I2C_CLK__I2C_CLK 0x0
182			>;
183		};
184
185		pinctrl_i2c2: i2c2grp {
186			fsl,pins = <
187				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
188				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
189			>;
190		};
191
192		pinctrl_pwm: pwmgrp {
193			fsl,pins = <
194				MX27_PAD_PWMO__PWMO 0x0
195			>;
196		};
197
198		pinctrl_sdhc2: sdhc2grp {
199			fsl,pins = <
200				MX27_PAD_SD2_CLK__SD2_CLK 0x0
201				MX27_PAD_SD2_CMD__SD2_CMD 0x0
202				MX27_PAD_SD2_D0__SD2_D0 0x0
203				MX27_PAD_SD2_D1__SD2_D1 0x0
204				MX27_PAD_SD2_D2__SD2_D2 0x0
205				MX27_PAD_SD2_D3__SD2_D3 0x0
206			>;
207		};
208
209		pinctrl_sdhc2_cd: sdhc2cdgrp {
210			fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
211		};
212	};
213};
214
215&sdhci2 {
216	bus-width = <4>;
217	cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
218	pinctrl-names = "default";
219	pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>;
220	status = "okay";
221};
222
223&pwm {
224	pinctrl-names = "default";
225	pinctrl-0 = <&pinctrl_pwm>;
226};