Loading...
Note: File does not exist in v6.13.7.
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1176000 1160000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55 };
56 cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a15";
59 reg = <1>;
60 };
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
69 };
70
71 gic: interrupt-controller@48211000 {
72 compatible = "arm,cortex-a15-gic";
73 interrupt-controller;
74 #interrupt-cells = <3>;
75 reg = <0x48211000 0x1000>,
76 <0x48212000 0x1000>,
77 <0x48214000 0x2000>,
78 <0x48216000 0x2000>;
79 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
80 };
81
82 /*
83 * The soc node represents the soc top level view. It is used for IPs
84 * that are not memory mapped in the MPU view or for the MPU itself.
85 */
86 soc {
87 compatible = "ti,omap-infra";
88 mpu {
89 compatible = "ti,omap5-mpu";
90 ti,hwmods = "mpu";
91 };
92 };
93
94 /*
95 * XXX: Use a flat representation of the SOC interconnect.
96 * The real OMAP interconnect network is quite complex.
97 * Since it will not bring real advantage to represent that in DT for
98 * the moment, just use a fake OCP bus entry to represent the whole bus
99 * hierarchy.
100 */
101 ocp {
102 compatible = "ti,omap4-l3-noc", "simple-bus";
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges;
106 ti,hwmods = "l3_main_1", "l3_main_2";
107 reg = <0x44000000 0x2000>,
108 <0x44800000 0x3000>;
109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
111
112 prm: prm@4ae06000 {
113 compatible = "ti,dra7-prm";
114 reg = <0x4ae06000 0x3000>;
115
116 prm_clocks: clocks {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 };
120
121 prm_clockdomains: clockdomains {
122 };
123 };
124
125 cm_core_aon: cm_core_aon@4a005000 {
126 compatible = "ti,dra7-cm-core-aon";
127 reg = <0x4a005000 0x2000>;
128
129 cm_core_aon_clocks: clocks {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 };
133
134 cm_core_aon_clockdomains: clockdomains {
135 };
136 };
137
138 cm_core: cm_core@4a008000 {
139 compatible = "ti,dra7-cm-core";
140 reg = <0x4a008000 0x3000>;
141
142 cm_core_clocks: clocks {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 };
146
147 cm_core_clockdomains: clockdomains {
148 };
149 };
150
151 counter32k: counter@4ae04000 {
152 compatible = "ti,omap-counter32k";
153 reg = <0x4ae04000 0x40>;
154 ti,hwmods = "counter_32k";
155 };
156
157 dra7_ctrl_general: tisyscon@4a002e00 {
158 compatible = "syscon";
159 reg = <0x4a002e00 0x7c>;
160 };
161
162 pbias_regulator: pbias_regulator {
163 compatible = "ti,pbias-omap";
164 reg = <0 0x4>;
165 syscon = <&dra7_ctrl_general>;
166 pbias_mmc_reg: pbias_mmc_omap5 {
167 regulator-name = "pbias_mmc_omap5";
168 regulator-min-microvolt = <1800000>;
169 regulator-max-microvolt = <3000000>;
170 };
171 };
172
173 dra7_pmx_core: pinmux@4a003400 {
174 compatible = "pinctrl-single";
175 reg = <0x4a003400 0x0464>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 pinctrl-single,register-width = <32>;
179 pinctrl-single,function-mask = <0x3fffffff>;
180 };
181
182 sdma: dma-controller@4a056000 {
183 compatible = "ti,omap4430-sdma";
184 reg = <0x4a056000 0x1000>;
185 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
189 #dma-cells = <1>;
190 #dma-channels = <32>;
191 #dma-requests = <127>;
192 };
193
194 gpio1: gpio@4ae10000 {
195 compatible = "ti,omap4-gpio";
196 reg = <0x4ae10000 0x200>;
197 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
198 ti,hwmods = "gpio1";
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <1>;
203 };
204
205 gpio2: gpio@48055000 {
206 compatible = "ti,omap4-gpio";
207 reg = <0x48055000 0x200>;
208 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
209 ti,hwmods = "gpio2";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <1>;
214 };
215
216 gpio3: gpio@48057000 {
217 compatible = "ti,omap4-gpio";
218 reg = <0x48057000 0x200>;
219 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
220 ti,hwmods = "gpio3";
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <1>;
225 };
226
227 gpio4: gpio@48059000 {
228 compatible = "ti,omap4-gpio";
229 reg = <0x48059000 0x200>;
230 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
231 ti,hwmods = "gpio4";
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
235 #interrupt-cells = <1>;
236 };
237
238 gpio5: gpio@4805b000 {
239 compatible = "ti,omap4-gpio";
240 reg = <0x4805b000 0x200>;
241 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
242 ti,hwmods = "gpio5";
243 gpio-controller;
244 #gpio-cells = <2>;
245 interrupt-controller;
246 #interrupt-cells = <1>;
247 };
248
249 gpio6: gpio@4805d000 {
250 compatible = "ti,omap4-gpio";
251 reg = <0x4805d000 0x200>;
252 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
253 ti,hwmods = "gpio6";
254 gpio-controller;
255 #gpio-cells = <2>;
256 interrupt-controller;
257 #interrupt-cells = <1>;
258 };
259
260 gpio7: gpio@48051000 {
261 compatible = "ti,omap4-gpio";
262 reg = <0x48051000 0x200>;
263 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
264 ti,hwmods = "gpio7";
265 gpio-controller;
266 #gpio-cells = <2>;
267 interrupt-controller;
268 #interrupt-cells = <1>;
269 };
270
271 gpio8: gpio@48053000 {
272 compatible = "ti,omap4-gpio";
273 reg = <0x48053000 0x200>;
274 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
275 ti,hwmods = "gpio8";
276 gpio-controller;
277 #gpio-cells = <2>;
278 interrupt-controller;
279 #interrupt-cells = <1>;
280 };
281
282 uart1: serial@4806a000 {
283 compatible = "ti,omap4-uart";
284 reg = <0x4806a000 0x100>;
285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
286 ti,hwmods = "uart1";
287 clock-frequency = <48000000>;
288 status = "disabled";
289 };
290
291 uart2: serial@4806c000 {
292 compatible = "ti,omap4-uart";
293 reg = <0x4806c000 0x100>;
294 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
295 ti,hwmods = "uart2";
296 clock-frequency = <48000000>;
297 status = "disabled";
298 };
299
300 uart3: serial@48020000 {
301 compatible = "ti,omap4-uart";
302 reg = <0x48020000 0x100>;
303 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "uart3";
305 clock-frequency = <48000000>;
306 status = "disabled";
307 };
308
309 uart4: serial@4806e000 {
310 compatible = "ti,omap4-uart";
311 reg = <0x4806e000 0x100>;
312 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
313 ti,hwmods = "uart4";
314 clock-frequency = <48000000>;
315 status = "disabled";
316 };
317
318 uart5: serial@48066000 {
319 compatible = "ti,omap4-uart";
320 reg = <0x48066000 0x100>;
321 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
322 ti,hwmods = "uart5";
323 clock-frequency = <48000000>;
324 status = "disabled";
325 };
326
327 uart6: serial@48068000 {
328 compatible = "ti,omap4-uart";
329 reg = <0x48068000 0x100>;
330 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
331 ti,hwmods = "uart6";
332 clock-frequency = <48000000>;
333 status = "disabled";
334 };
335
336 uart7: serial@48420000 {
337 compatible = "ti,omap4-uart";
338 reg = <0x48420000 0x100>;
339 ti,hwmods = "uart7";
340 clock-frequency = <48000000>;
341 status = "disabled";
342 };
343
344 uart8: serial@48422000 {
345 compatible = "ti,omap4-uart";
346 reg = <0x48422000 0x100>;
347 ti,hwmods = "uart8";
348 clock-frequency = <48000000>;
349 status = "disabled";
350 };
351
352 uart9: serial@48424000 {
353 compatible = "ti,omap4-uart";
354 reg = <0x48424000 0x100>;
355 ti,hwmods = "uart9";
356 clock-frequency = <48000000>;
357 status = "disabled";
358 };
359
360 uart10: serial@4ae2b000 {
361 compatible = "ti,omap4-uart";
362 reg = <0x4ae2b000 0x100>;
363 ti,hwmods = "uart10";
364 clock-frequency = <48000000>;
365 status = "disabled";
366 };
367
368 timer1: timer@4ae18000 {
369 compatible = "ti,omap5430-timer";
370 reg = <0x4ae18000 0x80>;
371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
372 ti,hwmods = "timer1";
373 ti,timer-alwon;
374 };
375
376 timer2: timer@48032000 {
377 compatible = "ti,omap5430-timer";
378 reg = <0x48032000 0x80>;
379 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
380 ti,hwmods = "timer2";
381 };
382
383 timer3: timer@48034000 {
384 compatible = "ti,omap5430-timer";
385 reg = <0x48034000 0x80>;
386 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
387 ti,hwmods = "timer3";
388 };
389
390 timer4: timer@48036000 {
391 compatible = "ti,omap5430-timer";
392 reg = <0x48036000 0x80>;
393 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
394 ti,hwmods = "timer4";
395 };
396
397 timer5: timer@48820000 {
398 compatible = "ti,omap5430-timer";
399 reg = <0x48820000 0x80>;
400 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
401 ti,hwmods = "timer5";
402 ti,timer-dsp;
403 };
404
405 timer6: timer@48822000 {
406 compatible = "ti,omap5430-timer";
407 reg = <0x48822000 0x80>;
408 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
409 ti,hwmods = "timer6";
410 ti,timer-dsp;
411 ti,timer-pwm;
412 };
413
414 timer7: timer@48824000 {
415 compatible = "ti,omap5430-timer";
416 reg = <0x48824000 0x80>;
417 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
418 ti,hwmods = "timer7";
419 ti,timer-dsp;
420 };
421
422 timer8: timer@48826000 {
423 compatible = "ti,omap5430-timer";
424 reg = <0x48826000 0x80>;
425 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
426 ti,hwmods = "timer8";
427 ti,timer-dsp;
428 ti,timer-pwm;
429 };
430
431 timer9: timer@4803e000 {
432 compatible = "ti,omap5430-timer";
433 reg = <0x4803e000 0x80>;
434 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
435 ti,hwmods = "timer9";
436 };
437
438 timer10: timer@48086000 {
439 compatible = "ti,omap5430-timer";
440 reg = <0x48086000 0x80>;
441 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
442 ti,hwmods = "timer10";
443 };
444
445 timer11: timer@48088000 {
446 compatible = "ti,omap5430-timer";
447 reg = <0x48088000 0x80>;
448 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
449 ti,hwmods = "timer11";
450 ti,timer-pwm;
451 };
452
453 timer13: timer@48828000 {
454 compatible = "ti,omap5430-timer";
455 reg = <0x48828000 0x80>;
456 ti,hwmods = "timer13";
457 status = "disabled";
458 };
459
460 timer14: timer@4882a000 {
461 compatible = "ti,omap5430-timer";
462 reg = <0x4882a000 0x80>;
463 ti,hwmods = "timer14";
464 status = "disabled";
465 };
466
467 timer15: timer@4882c000 {
468 compatible = "ti,omap5430-timer";
469 reg = <0x4882c000 0x80>;
470 ti,hwmods = "timer15";
471 status = "disabled";
472 };
473
474 timer16: timer@4882e000 {
475 compatible = "ti,omap5430-timer";
476 reg = <0x4882e000 0x80>;
477 ti,hwmods = "timer16";
478 status = "disabled";
479 };
480
481 wdt2: wdt@4ae14000 {
482 compatible = "ti,omap4-wdt";
483 reg = <0x4ae14000 0x80>;
484 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
485 ti,hwmods = "wd_timer2";
486 };
487
488 hwspinlock: spinlock@4a0f6000 {
489 compatible = "ti,omap4-hwspinlock";
490 reg = <0x4a0f6000 0x1000>;
491 ti,hwmods = "spinlock";
492 #hwlock-cells = <1>;
493 };
494
495 dmm@4e000000 {
496 compatible = "ti,omap5-dmm";
497 reg = <0x4e000000 0x800>;
498 interrupts = <0 113 0x4>;
499 ti,hwmods = "dmm";
500 };
501
502 i2c1: i2c@48070000 {
503 compatible = "ti,omap4-i2c";
504 reg = <0x48070000 0x100>;
505 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 ti,hwmods = "i2c1";
509 status = "disabled";
510 };
511
512 i2c2: i2c@48072000 {
513 compatible = "ti,omap4-i2c";
514 reg = <0x48072000 0x100>;
515 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 ti,hwmods = "i2c2";
519 status = "disabled";
520 };
521
522 i2c3: i2c@48060000 {
523 compatible = "ti,omap4-i2c";
524 reg = <0x48060000 0x100>;
525 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 ti,hwmods = "i2c3";
529 status = "disabled";
530 };
531
532 i2c4: i2c@4807a000 {
533 compatible = "ti,omap4-i2c";
534 reg = <0x4807a000 0x100>;
535 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 ti,hwmods = "i2c4";
539 status = "disabled";
540 };
541
542 i2c5: i2c@4807c000 {
543 compatible = "ti,omap4-i2c";
544 reg = <0x4807c000 0x100>;
545 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 ti,hwmods = "i2c5";
549 status = "disabled";
550 };
551
552 mmc1: mmc@4809c000 {
553 compatible = "ti,omap4-hsmmc";
554 reg = <0x4809c000 0x400>;
555 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
556 ti,hwmods = "mmc1";
557 ti,dual-volt;
558 ti,needs-special-reset;
559 dmas = <&sdma 61>, <&sdma 62>;
560 dma-names = "tx", "rx";
561 status = "disabled";
562 pbias-supply = <&pbias_mmc_reg>;
563 };
564
565 mmc2: mmc@480b4000 {
566 compatible = "ti,omap4-hsmmc";
567 reg = <0x480b4000 0x400>;
568 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
569 ti,hwmods = "mmc2";
570 ti,needs-special-reset;
571 dmas = <&sdma 47>, <&sdma 48>;
572 dma-names = "tx", "rx";
573 status = "disabled";
574 };
575
576 mmc3: mmc@480ad000 {
577 compatible = "ti,omap4-hsmmc";
578 reg = <0x480ad000 0x400>;
579 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
580 ti,hwmods = "mmc3";
581 ti,needs-special-reset;
582 dmas = <&sdma 77>, <&sdma 78>;
583 dma-names = "tx", "rx";
584 status = "disabled";
585 };
586
587 mmc4: mmc@480d1000 {
588 compatible = "ti,omap4-hsmmc";
589 reg = <0x480d1000 0x400>;
590 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
591 ti,hwmods = "mmc4";
592 ti,needs-special-reset;
593 dmas = <&sdma 57>, <&sdma 58>;
594 dma-names = "tx", "rx";
595 status = "disabled";
596 };
597
598 abb_mpu: regulator-abb-mpu {
599 compatible = "ti,abb-v3";
600 regulator-name = "abb_mpu";
601 #address-cells = <0>;
602 #size-cells = <0>;
603 clocks = <&sys_clkin1>;
604 ti,settling-time = <50>;
605 ti,clock-cycles = <16>;
606
607 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
608 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
609 <0x4ae0c158 0x4>;
610 reg-names = "setup-address", "control-address",
611 "int-address", "efuse-address",
612 "ldo-address";
613 ti,tranxdone-status-mask = <0x80>;
614 /* LDOVBBMPU_FBB_MUX_CTRL */
615 ti,ldovbb-override-mask = <0x400>;
616 /* LDOVBBMPU_FBB_VSET_OUT */
617 ti,ldovbb-vset-mask = <0x1F>;
618
619 /*
620 * NOTE: only FBB mode used but actual vset will
621 * determine final biasing
622 */
623 ti,abb_info = <
624 /*uV ABB efuse rbb_m fbb_m vset_m*/
625 1060000 0 0x0 0 0x02000000 0x01F00000
626 1160000 0 0x4 0 0x02000000 0x01F00000
627 1210000 0 0x8 0 0x02000000 0x01F00000
628 >;
629 };
630
631 abb_ivahd: regulator-abb-ivahd {
632 compatible = "ti,abb-v3";
633 regulator-name = "abb_ivahd";
634 #address-cells = <0>;
635 #size-cells = <0>;
636 clocks = <&sys_clkin1>;
637 ti,settling-time = <50>;
638 ti,clock-cycles = <16>;
639
640 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
641 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
642 <0x4a002470 0x4>;
643 reg-names = "setup-address", "control-address",
644 "int-address", "efuse-address",
645 "ldo-address";
646 ti,tranxdone-status-mask = <0x40000000>;
647 /* LDOVBBIVA_FBB_MUX_CTRL */
648 ti,ldovbb-override-mask = <0x400>;
649 /* LDOVBBIVA_FBB_VSET_OUT */
650 ti,ldovbb-vset-mask = <0x1F>;
651
652 /*
653 * NOTE: only FBB mode used but actual vset will
654 * determine final biasing
655 */
656 ti,abb_info = <
657 /*uV ABB efuse rbb_m fbb_m vset_m*/
658 1055000 0 0x0 0 0x02000000 0x01F00000
659 1150000 0 0x4 0 0x02000000 0x01F00000
660 1250000 0 0x8 0 0x02000000 0x01F00000
661 >;
662 };
663
664 abb_dspeve: regulator-abb-dspeve {
665 compatible = "ti,abb-v3";
666 regulator-name = "abb_dspeve";
667 #address-cells = <0>;
668 #size-cells = <0>;
669 clocks = <&sys_clkin1>;
670 ti,settling-time = <50>;
671 ti,clock-cycles = <16>;
672
673 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
674 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
675 <0x4a00246c 0x4>;
676 reg-names = "setup-address", "control-address",
677 "int-address", "efuse-address",
678 "ldo-address";
679 ti,tranxdone-status-mask = <0x20000000>;
680 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
681 ti,ldovbb-override-mask = <0x400>;
682 /* LDOVBBDSPEVE_FBB_VSET_OUT */
683 ti,ldovbb-vset-mask = <0x1F>;
684
685 /*
686 * NOTE: only FBB mode used but actual vset will
687 * determine final biasing
688 */
689 ti,abb_info = <
690 /*uV ABB efuse rbb_m fbb_m vset_m*/
691 1055000 0 0x0 0 0x02000000 0x01F00000
692 1150000 0 0x4 0 0x02000000 0x01F00000
693 1250000 0 0x8 0 0x02000000 0x01F00000
694 >;
695 };
696
697 abb_gpu: regulator-abb-gpu {
698 compatible = "ti,abb-v3";
699 regulator-name = "abb_gpu";
700 #address-cells = <0>;
701 #size-cells = <0>;
702 clocks = <&sys_clkin1>;
703 ti,settling-time = <50>;
704 ti,clock-cycles = <16>;
705
706 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
707 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
708 <0x4ae0c154 0x4>;
709 reg-names = "setup-address", "control-address",
710 "int-address", "efuse-address",
711 "ldo-address";
712 ti,tranxdone-status-mask = <0x10000000>;
713 /* LDOVBBGPU_FBB_MUX_CTRL */
714 ti,ldovbb-override-mask = <0x400>;
715 /* LDOVBBGPU_FBB_VSET_OUT */
716 ti,ldovbb-vset-mask = <0x1F>;
717
718 /*
719 * NOTE: only FBB mode used but actual vset will
720 * determine final biasing
721 */
722 ti,abb_info = <
723 /*uV ABB efuse rbb_m fbb_m vset_m*/
724 1090000 0 0x0 0 0x02000000 0x01F00000
725 1210000 0 0x4 0 0x02000000 0x01F00000
726 1280000 0 0x8 0 0x02000000 0x01F00000
727 >;
728 };
729
730 mcspi1: spi@48098000 {
731 compatible = "ti,omap4-mcspi";
732 reg = <0x48098000 0x200>;
733 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
734 #address-cells = <1>;
735 #size-cells = <0>;
736 ti,hwmods = "mcspi1";
737 ti,spi-num-cs = <4>;
738 dmas = <&sdma 35>,
739 <&sdma 36>,
740 <&sdma 37>,
741 <&sdma 38>,
742 <&sdma 39>,
743 <&sdma 40>,
744 <&sdma 41>,
745 <&sdma 42>;
746 dma-names = "tx0", "rx0", "tx1", "rx1",
747 "tx2", "rx2", "tx3", "rx3";
748 status = "disabled";
749 };
750
751 mcspi2: spi@4809a000 {
752 compatible = "ti,omap4-mcspi";
753 reg = <0x4809a000 0x200>;
754 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>;
756 #size-cells = <0>;
757 ti,hwmods = "mcspi2";
758 ti,spi-num-cs = <2>;
759 dmas = <&sdma 43>,
760 <&sdma 44>,
761 <&sdma 45>,
762 <&sdma 46>;
763 dma-names = "tx0", "rx0", "tx1", "rx1";
764 status = "disabled";
765 };
766
767 mcspi3: spi@480b8000 {
768 compatible = "ti,omap4-mcspi";
769 reg = <0x480b8000 0x200>;
770 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
771 #address-cells = <1>;
772 #size-cells = <0>;
773 ti,hwmods = "mcspi3";
774 ti,spi-num-cs = <2>;
775 dmas = <&sdma 15>, <&sdma 16>;
776 dma-names = "tx0", "rx0";
777 status = "disabled";
778 };
779
780 mcspi4: spi@480ba000 {
781 compatible = "ti,omap4-mcspi";
782 reg = <0x480ba000 0x200>;
783 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
784 #address-cells = <1>;
785 #size-cells = <0>;
786 ti,hwmods = "mcspi4";
787 ti,spi-num-cs = <1>;
788 dmas = <&sdma 70>, <&sdma 71>;
789 dma-names = "tx0", "rx0";
790 status = "disabled";
791 };
792 };
793};
794
795/include/ "dra7xx-clocks.dtsi"