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1/*
2 * imx-ssi.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 *
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
25 * rate.
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
31 *
32 */
33
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/dma-mapping.h>
38#include <linux/init.h>
39#include <linux/interrupt.h>
40#include <linux/module.h>
41#include <linux/platform_device.h>
42#include <linux/slab.h>
43
44#include <sound/core.h>
45#include <sound/initval.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49
50#include <mach/ssi.h>
51#include <mach/hardware.h>
52
53#include "imx-ssi.h"
54
55#define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
56
57/*
58 * SSI Network Mode or TDM slots configuration.
59 * Should only be called when port is inactive (i.e. SSIEN = 0).
60 */
61static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
62 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
63{
64 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
65 u32 sccr;
66
67 sccr = readl(ssi->base + SSI_STCCR);
68 sccr &= ~SSI_STCCR_DC_MASK;
69 sccr |= SSI_STCCR_DC(slots - 1);
70 writel(sccr, ssi->base + SSI_STCCR);
71
72 sccr = readl(ssi->base + SSI_SRCCR);
73 sccr &= ~SSI_STCCR_DC_MASK;
74 sccr |= SSI_STCCR_DC(slots - 1);
75 writel(sccr, ssi->base + SSI_SRCCR);
76
77 writel(tx_mask, ssi->base + SSI_STMSK);
78 writel(rx_mask, ssi->base + SSI_SRMSK);
79
80 return 0;
81}
82
83/*
84 * SSI DAI format configuration.
85 * Should only be called when port is inactive (i.e. SSIEN = 0).
86 */
87static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
88{
89 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
90 u32 strcr = 0, scr;
91
92 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
93
94 /* DAI mode */
95 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
96 case SND_SOC_DAIFMT_I2S:
97 /* data on rising edge of bclk, frame low 1clk before data */
98 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
99 scr |= SSI_SCR_NET;
100 if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
101 scr &= ~SSI_I2S_MODE_MASK;
102 scr |= SSI_SCR_I2S_MODE_SLAVE;
103 }
104 break;
105 case SND_SOC_DAIFMT_LEFT_J:
106 /* data on rising edge of bclk, frame high with data */
107 strcr |= SSI_STCR_TXBIT0;
108 break;
109 case SND_SOC_DAIFMT_DSP_B:
110 /* data on rising edge of bclk, frame high with data */
111 strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0;
112 break;
113 case SND_SOC_DAIFMT_DSP_A:
114 /* data on rising edge of bclk, frame high 1clk before data */
115 strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
116 break;
117 }
118
119 /* DAI clock inversion */
120 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
121 case SND_SOC_DAIFMT_IB_IF:
122 strcr |= SSI_STCR_TFSI;
123 strcr &= ~SSI_STCR_TSCKP;
124 break;
125 case SND_SOC_DAIFMT_IB_NF:
126 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
127 break;
128 case SND_SOC_DAIFMT_NB_IF:
129 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
130 break;
131 case SND_SOC_DAIFMT_NB_NF:
132 strcr &= ~SSI_STCR_TFSI;
133 strcr |= SSI_STCR_TSCKP;
134 break;
135 }
136
137 /* DAI clock master masks */
138 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
139 case SND_SOC_DAIFMT_CBM_CFM:
140 break;
141 default:
142 /* Master mode not implemented, needs handling of clocks. */
143 return -EINVAL;
144 }
145
146 strcr |= SSI_STCR_TFEN0;
147
148 if (ssi->flags & IMX_SSI_NET)
149 scr |= SSI_SCR_NET;
150 if (ssi->flags & IMX_SSI_SYN)
151 scr |= SSI_SCR_SYN;
152
153 writel(strcr, ssi->base + SSI_STCR);
154 writel(strcr, ssi->base + SSI_SRCR);
155 writel(scr, ssi->base + SSI_SCR);
156
157 return 0;
158}
159
160/*
161 * SSI system clock configuration.
162 * Should only be called when port is inactive (i.e. SSIEN = 0).
163 */
164static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
165 int clk_id, unsigned int freq, int dir)
166{
167 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
168 u32 scr;
169
170 scr = readl(ssi->base + SSI_SCR);
171
172 switch (clk_id) {
173 case IMX_SSP_SYS_CLK:
174 if (dir == SND_SOC_CLOCK_OUT)
175 scr |= SSI_SCR_SYS_CLK_EN;
176 else
177 scr &= ~SSI_SCR_SYS_CLK_EN;
178 break;
179 default:
180 return -EINVAL;
181 }
182
183 writel(scr, ssi->base + SSI_SCR);
184
185 return 0;
186}
187
188/*
189 * SSI Clock dividers
190 * Should only be called when port is inactive (i.e. SSIEN = 0).
191 */
192static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
193 int div_id, int div)
194{
195 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
196 u32 stccr, srccr;
197
198 stccr = readl(ssi->base + SSI_STCCR);
199 srccr = readl(ssi->base + SSI_SRCCR);
200
201 switch (div_id) {
202 case IMX_SSI_TX_DIV_2:
203 stccr &= ~SSI_STCCR_DIV2;
204 stccr |= div;
205 break;
206 case IMX_SSI_TX_DIV_PSR:
207 stccr &= ~SSI_STCCR_PSR;
208 stccr |= div;
209 break;
210 case IMX_SSI_TX_DIV_PM:
211 stccr &= ~0xff;
212 stccr |= SSI_STCCR_PM(div);
213 break;
214 case IMX_SSI_RX_DIV_2:
215 stccr &= ~SSI_STCCR_DIV2;
216 stccr |= div;
217 break;
218 case IMX_SSI_RX_DIV_PSR:
219 stccr &= ~SSI_STCCR_PSR;
220 stccr |= div;
221 break;
222 case IMX_SSI_RX_DIV_PM:
223 stccr &= ~0xff;
224 stccr |= SSI_STCCR_PM(div);
225 break;
226 default:
227 return -EINVAL;
228 }
229
230 writel(stccr, ssi->base + SSI_STCCR);
231 writel(srccr, ssi->base + SSI_SRCCR);
232
233 return 0;
234}
235
236/*
237 * Should only be called when port is inactive (i.e. SSIEN = 0),
238 * although can be called multiple times by upper layers.
239 */
240static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
241 struct snd_pcm_hw_params *params,
242 struct snd_soc_dai *cpu_dai)
243{
244 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
245 struct imx_pcm_dma_params *dma_data;
246 u32 reg, sccr;
247
248 /* Tx/Rx config */
249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
250 reg = SSI_STCCR;
251 dma_data = &ssi->dma_params_tx;
252 } else {
253 reg = SSI_SRCCR;
254 dma_data = &ssi->dma_params_rx;
255 }
256
257 if (ssi->flags & IMX_SSI_SYN)
258 reg = SSI_STCCR;
259
260 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
261
262 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
263
264 /* DAI data (word) size */
265 switch (params_format(params)) {
266 case SNDRV_PCM_FORMAT_S16_LE:
267 sccr |= SSI_SRCCR_WL(16);
268 break;
269 case SNDRV_PCM_FORMAT_S20_3LE:
270 sccr |= SSI_SRCCR_WL(20);
271 break;
272 case SNDRV_PCM_FORMAT_S24_LE:
273 sccr |= SSI_SRCCR_WL(24);
274 break;
275 }
276
277 writel(sccr, ssi->base + reg);
278
279 return 0;
280}
281
282static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
283 struct snd_soc_dai *dai)
284{
285 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
286 unsigned int sier_bits, sier;
287 unsigned int scr;
288
289 scr = readl(ssi->base + SSI_SCR);
290 sier = readl(ssi->base + SSI_SIER);
291
292 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
293 if (ssi->flags & IMX_SSI_DMA)
294 sier_bits = SSI_SIER_TDMAE;
295 else
296 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
297 } else {
298 if (ssi->flags & IMX_SSI_DMA)
299 sier_bits = SSI_SIER_RDMAE;
300 else
301 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
302 }
303
304 switch (cmd) {
305 case SNDRV_PCM_TRIGGER_START:
306 case SNDRV_PCM_TRIGGER_RESUME:
307 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
308 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
309 scr |= SSI_SCR_TE;
310 else
311 scr |= SSI_SCR_RE;
312 sier |= sier_bits;
313
314 if (++ssi->enabled == 1)
315 scr |= SSI_SCR_SSIEN;
316
317 break;
318
319 case SNDRV_PCM_TRIGGER_STOP:
320 case SNDRV_PCM_TRIGGER_SUSPEND:
321 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
323 scr &= ~SSI_SCR_TE;
324 else
325 scr &= ~SSI_SCR_RE;
326 sier &= ~sier_bits;
327
328 if (--ssi->enabled == 0)
329 scr &= ~SSI_SCR_SSIEN;
330
331 break;
332 default:
333 return -EINVAL;
334 }
335
336 if (!(ssi->flags & IMX_SSI_USE_AC97))
337 /* rx/tx are always enabled to access ac97 registers */
338 writel(scr, ssi->base + SSI_SCR);
339
340 writel(sier, ssi->base + SSI_SIER);
341
342 return 0;
343}
344
345static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
346 .hw_params = imx_ssi_hw_params,
347 .set_fmt = imx_ssi_set_dai_fmt,
348 .set_clkdiv = imx_ssi_set_dai_clkdiv,
349 .set_sysclk = imx_ssi_set_dai_sysclk,
350 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
351 .trigger = imx_ssi_trigger,
352};
353
354int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
355 struct vm_area_struct *vma)
356{
357 struct snd_pcm_runtime *runtime = substream->runtime;
358 int ret;
359
360 ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
361 runtime->dma_addr, runtime->dma_bytes);
362
363 pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
364 runtime->dma_area,
365 runtime->dma_addr,
366 runtime->dma_bytes);
367 return ret;
368}
369EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
370
371static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
372{
373 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
374 struct snd_dma_buffer *buf = &substream->dma_buffer;
375 size_t size = IMX_SSI_DMABUF_SIZE;
376
377 buf->dev.type = SNDRV_DMA_TYPE_DEV;
378 buf->dev.dev = pcm->card->dev;
379 buf->private_data = NULL;
380 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
381 &buf->addr, GFP_KERNEL);
382 if (!buf->area)
383 return -ENOMEM;
384 buf->bytes = size;
385
386 return 0;
387}
388
389static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
390
391int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
392{
393 struct snd_card *card = rtd->card->snd_card;
394 struct snd_soc_dai *dai = rtd->cpu_dai;
395 struct snd_pcm *pcm = rtd->pcm;
396 int ret = 0;
397
398 if (!card->dev->dma_mask)
399 card->dev->dma_mask = &imx_pcm_dmamask;
400 if (!card->dev->coherent_dma_mask)
401 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
402 if (dai->driver->playback.channels_min) {
403 ret = imx_pcm_preallocate_dma_buffer(pcm,
404 SNDRV_PCM_STREAM_PLAYBACK);
405 if (ret)
406 goto out;
407 }
408
409 if (dai->driver->capture.channels_min) {
410 ret = imx_pcm_preallocate_dma_buffer(pcm,
411 SNDRV_PCM_STREAM_CAPTURE);
412 if (ret)
413 goto out;
414 }
415
416out:
417 return ret;
418}
419EXPORT_SYMBOL_GPL(imx_pcm_new);
420
421void imx_pcm_free(struct snd_pcm *pcm)
422{
423 struct snd_pcm_substream *substream;
424 struct snd_dma_buffer *buf;
425 int stream;
426
427 for (stream = 0; stream < 2; stream++) {
428 substream = pcm->streams[stream].substream;
429 if (!substream)
430 continue;
431
432 buf = &substream->dma_buffer;
433 if (!buf->area)
434 continue;
435
436 dma_free_writecombine(pcm->card->dev, buf->bytes,
437 buf->area, buf->addr);
438 buf->area = NULL;
439 }
440}
441EXPORT_SYMBOL_GPL(imx_pcm_free);
442
443static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
444{
445 struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
446 uint32_t val;
447
448 snd_soc_dai_set_drvdata(dai, ssi);
449
450 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
451 SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
452 writel(val, ssi->base + SSI_SFCSR);
453
454 return 0;
455}
456
457static struct snd_soc_dai_driver imx_ssi_dai = {
458 .probe = imx_ssi_dai_probe,
459 .playback = {
460 .channels_min = 1,
461 .channels_max = 2,
462 .rates = SNDRV_PCM_RATE_8000_96000,
463 .formats = SNDRV_PCM_FMTBIT_S16_LE,
464 },
465 .capture = {
466 .channels_min = 1,
467 .channels_max = 2,
468 .rates = SNDRV_PCM_RATE_8000_96000,
469 .formats = SNDRV_PCM_FMTBIT_S16_LE,
470 },
471 .ops = &imx_ssi_pcm_dai_ops,
472};
473
474static struct snd_soc_dai_driver imx_ac97_dai = {
475 .probe = imx_ssi_dai_probe,
476 .ac97_control = 1,
477 .playback = {
478 .stream_name = "AC97 Playback",
479 .channels_min = 2,
480 .channels_max = 2,
481 .rates = SNDRV_PCM_RATE_48000,
482 .formats = SNDRV_PCM_FMTBIT_S16_LE,
483 },
484 .capture = {
485 .stream_name = "AC97 Capture",
486 .channels_min = 2,
487 .channels_max = 2,
488 .rates = SNDRV_PCM_RATE_48000,
489 .formats = SNDRV_PCM_FMTBIT_S16_LE,
490 },
491 .ops = &imx_ssi_pcm_dai_ops,
492};
493
494static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
495{
496 void __iomem *base = imx_ssi->base;
497
498 writel(0x0, base + SSI_SCR);
499 writel(0x0, base + SSI_STCR);
500 writel(0x0, base + SSI_SRCR);
501
502 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
503
504 writel(SSI_SFCSR_RFWM0(8) |
505 SSI_SFCSR_TFWM0(8) |
506 SSI_SFCSR_RFWM1(8) |
507 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
508
509 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
510 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
511
512 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
513 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
514
515 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
516 SSI_SCR_TE | SSI_SCR_RE,
517 base + SSI_SCR);
518
519 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
520 writel(0xff, base + SSI_SACCDIS);
521 writel(0x300, base + SSI_SACCEN);
522}
523
524static struct imx_ssi *ac97_ssi;
525
526static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
527 unsigned short val)
528{
529 struct imx_ssi *imx_ssi = ac97_ssi;
530 void __iomem *base = imx_ssi->base;
531 unsigned int lreg;
532 unsigned int lval;
533
534 if (reg > 0x7f)
535 return;
536
537 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
538
539 lreg = reg << 12;
540 writel(lreg, base + SSI_SACADD);
541
542 lval = val << 4;
543 writel(lval , base + SSI_SACDAT);
544
545 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
546 udelay(100);
547}
548
549static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
550 unsigned short reg)
551{
552 struct imx_ssi *imx_ssi = ac97_ssi;
553 void __iomem *base = imx_ssi->base;
554
555 unsigned short val = -1;
556 unsigned int lreg;
557
558 lreg = (reg & 0x7f) << 12 ;
559 writel(lreg, base + SSI_SACADD);
560 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
561
562 udelay(100);
563
564 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
565
566 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
567
568 return val;
569}
570
571static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
572{
573 struct imx_ssi *imx_ssi = ac97_ssi;
574
575 if (imx_ssi->ac97_reset)
576 imx_ssi->ac97_reset(ac97);
577}
578
579static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
580{
581 struct imx_ssi *imx_ssi = ac97_ssi;
582
583 if (imx_ssi->ac97_warm_reset)
584 imx_ssi->ac97_warm_reset(ac97);
585}
586
587struct snd_ac97_bus_ops soc_ac97_ops = {
588 .read = imx_ssi_ac97_read,
589 .write = imx_ssi_ac97_write,
590 .reset = imx_ssi_ac97_reset,
591 .warm_reset = imx_ssi_ac97_warm_reset
592};
593EXPORT_SYMBOL_GPL(soc_ac97_ops);
594
595static int imx_ssi_probe(struct platform_device *pdev)
596{
597 struct resource *res;
598 struct imx_ssi *ssi;
599 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
600 int ret = 0;
601 struct snd_soc_dai_driver *dai;
602
603 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
604 if (!ssi)
605 return -ENOMEM;
606 dev_set_drvdata(&pdev->dev, ssi);
607
608 if (pdata) {
609 ssi->ac97_reset = pdata->ac97_reset;
610 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
611 ssi->flags = pdata->flags;
612 }
613
614 ssi->irq = platform_get_irq(pdev, 0);
615
616 ssi->clk = clk_get(&pdev->dev, NULL);
617 if (IS_ERR(ssi->clk)) {
618 ret = PTR_ERR(ssi->clk);
619 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
620 ret);
621 goto failed_clk;
622 }
623 clk_enable(ssi->clk);
624
625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 if (!res) {
627 ret = -ENODEV;
628 goto failed_get_resource;
629 }
630
631 if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
632 dev_err(&pdev->dev, "request_mem_region failed\n");
633 ret = -EBUSY;
634 goto failed_get_resource;
635 }
636
637 ssi->base = ioremap(res->start, resource_size(res));
638 if (!ssi->base) {
639 dev_err(&pdev->dev, "ioremap failed\n");
640 ret = -ENODEV;
641 goto failed_ioremap;
642 }
643
644 if (ssi->flags & IMX_SSI_USE_AC97) {
645 if (ac97_ssi) {
646 ret = -EBUSY;
647 goto failed_ac97;
648 }
649 ac97_ssi = ssi;
650 setup_channel_to_ac97(ssi);
651 dai = &imx_ac97_dai;
652 } else
653 dai = &imx_ssi_dai;
654
655 writel(0x0, ssi->base + SSI_SIER);
656
657 ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
658 ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
659
660 ssi->dma_params_tx.burstsize = 4;
661 ssi->dma_params_rx.burstsize = 4;
662
663 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
664 if (res)
665 ssi->dma_params_tx.dma = res->start;
666
667 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
668 if (res)
669 ssi->dma_params_rx.dma = res->start;
670
671 platform_set_drvdata(pdev, ssi);
672
673 ret = snd_soc_register_dai(&pdev->dev, dai);
674 if (ret) {
675 dev_err(&pdev->dev, "register DAI failed\n");
676 goto failed_register;
677 }
678
679 ssi->soc_platform_pdev_fiq = platform_device_alloc("imx-fiq-pcm-audio", pdev->id);
680 if (!ssi->soc_platform_pdev_fiq) {
681 ret = -ENOMEM;
682 goto failed_pdev_fiq_alloc;
683 }
684
685 platform_set_drvdata(ssi->soc_platform_pdev_fiq, ssi);
686 ret = platform_device_add(ssi->soc_platform_pdev_fiq);
687 if (ret) {
688 dev_err(&pdev->dev, "failed to add platform device\n");
689 goto failed_pdev_fiq_add;
690 }
691
692 ssi->soc_platform_pdev = platform_device_alloc("imx-pcm-audio", pdev->id);
693 if (!ssi->soc_platform_pdev) {
694 ret = -ENOMEM;
695 goto failed_pdev_alloc;
696 }
697
698 platform_set_drvdata(ssi->soc_platform_pdev, ssi);
699 ret = platform_device_add(ssi->soc_platform_pdev);
700 if (ret) {
701 dev_err(&pdev->dev, "failed to add platform device\n");
702 goto failed_pdev_add;
703 }
704
705 return 0;
706
707failed_pdev_add:
708 platform_device_put(ssi->soc_platform_pdev);
709failed_pdev_alloc:
710 platform_device_del(ssi->soc_platform_pdev_fiq);
711failed_pdev_fiq_add:
712 platform_device_put(ssi->soc_platform_pdev_fiq);
713failed_pdev_fiq_alloc:
714 snd_soc_unregister_dai(&pdev->dev);
715failed_register:
716failed_ac97:
717 iounmap(ssi->base);
718failed_ioremap:
719 release_mem_region(res->start, resource_size(res));
720failed_get_resource:
721 clk_disable(ssi->clk);
722 clk_put(ssi->clk);
723failed_clk:
724 kfree(ssi);
725
726 return ret;
727}
728
729static int __devexit imx_ssi_remove(struct platform_device *pdev)
730{
731 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
732 struct imx_ssi *ssi = platform_get_drvdata(pdev);
733
734 platform_device_unregister(ssi->soc_platform_pdev);
735 platform_device_unregister(ssi->soc_platform_pdev_fiq);
736
737 snd_soc_unregister_dai(&pdev->dev);
738
739 if (ssi->flags & IMX_SSI_USE_AC97)
740 ac97_ssi = NULL;
741
742 iounmap(ssi->base);
743 release_mem_region(res->start, resource_size(res));
744 clk_disable(ssi->clk);
745 clk_put(ssi->clk);
746 kfree(ssi);
747
748 return 0;
749}
750
751static struct platform_driver imx_ssi_driver = {
752 .probe = imx_ssi_probe,
753 .remove = __devexit_p(imx_ssi_remove),
754
755 .driver = {
756 .name = "imx-ssi",
757 .owner = THIS_MODULE,
758 },
759};
760
761static int __init imx_ssi_init(void)
762{
763 return platform_driver_register(&imx_ssi_driver);
764}
765
766static void __exit imx_ssi_exit(void)
767{
768 platform_driver_unregister(&imx_ssi_driver);
769}
770
771module_init(imx_ssi_init);
772module_exit(imx_ssi_exit);
773
774/* Module information */
775MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
776MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
777MODULE_LICENSE("GPL");
778MODULE_ALIAS("platform:imx-ssi");