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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * nau8822.h -- NAU8822 ALSA SoC Audio driver
4 *
5 * Copyright 2017 Nuvoton Technology Crop.
6 *
7 * Author: David Lin <ctlin0@nuvoton.com>
8 * Co-author: John Hsu <kchsu0@nuvoton.com>
9 * Co-author: Seven Li <wtli@nuvoton.com>
10 */
11
12#ifndef __NAU8822_H__
13#define __NAU8822_H__
14
15#define NAU8822_REG_RESET 0x00
16#define NAU8822_REG_POWER_MANAGEMENT_1 0x01
17#define NAU8822_REG_POWER_MANAGEMENT_2 0x02
18#define NAU8822_REG_POWER_MANAGEMENT_3 0x03
19#define NAU8822_REG_AUDIO_INTERFACE 0x04
20#define NAU8822_REG_COMPANDING_CONTROL 0x05
21#define NAU8822_REG_CLOCKING 0x06
22#define NAU8822_REG_ADDITIONAL_CONTROL 0x07
23#define NAU8822_REG_GPIO_CONTROL 0x08
24#define NAU8822_REG_JACK_DETECT_CONTROL_1 0x09
25#define NAU8822_REG_DAC_CONTROL 0x0A
26#define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B
27#define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME 0x0C
28#define NAU8822_REG_JACK_DETECT_CONTROL_2 0x0D
29#define NAU8822_REG_ADC_CONTROL 0x0E
30#define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F
31#define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME 0x10
32#define NAU8822_REG_EQ1 0x12
33#define NAU8822_REG_EQ2 0x13
34#define NAU8822_REG_EQ3 0x14
35#define NAU8822_REG_EQ4 0x15
36#define NAU8822_REG_EQ5 0x16
37#define NAU8822_REG_DAC_LIMITER_1 0x18
38#define NAU8822_REG_DAC_LIMITER_2 0x19
39#define NAU8822_REG_NOTCH_FILTER_1 0x1B
40#define NAU8822_REG_NOTCH_FILTER_2 0x1C
41#define NAU8822_REG_NOTCH_FILTER_3 0x1D
42#define NAU8822_REG_NOTCH_FILTER_4 0x1E
43#define NAU8822_REG_ALC_CONTROL_1 0x20
44#define NAU8822_REG_ALC_CONTROL_2 0x21
45#define NAU8822_REG_ALC_CONTROL_3 0x22
46#define NAU8822_REG_NOISE_GATE 0x23
47#define NAU8822_REG_PLL_N 0x24
48#define NAU8822_REG_PLL_K1 0x25
49#define NAU8822_REG_PLL_K2 0x26
50#define NAU8822_REG_PLL_K3 0x27
51#define NAU8822_REG_3D_CONTROL 0x29
52#define NAU8822_REG_RIGHT_SPEAKER_CONTROL 0x2B
53#define NAU8822_REG_INPUT_CONTROL 0x2C
54#define NAU8822_REG_LEFT_INP_PGA_CONTROL 0x2D
55#define NAU8822_REG_RIGHT_INP_PGA_CONTROL 0x2E
56#define NAU8822_REG_LEFT_ADC_BOOST_CONTROL 0x2F
57#define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x30
58#define NAU8822_REG_OUTPUT_CONTROL 0x31
59#define NAU8822_REG_LEFT_MIXER_CONTROL 0x32
60#define NAU8822_REG_RIGHT_MIXER_CONTROL 0x33
61#define NAU8822_REG_LHP_VOLUME 0x34
62#define NAU8822_REG_RHP_VOLUME 0x35
63#define NAU8822_REG_LSPKOUT_VOLUME 0x36
64#define NAU8822_REG_RSPKOUT_VOLUME 0x37
65#define NAU8822_REG_AUX2_MIXER 0x38
66#define NAU8822_REG_AUX1_MIXER 0x39
67#define NAU8822_REG_POWER_MANAGEMENT_4 0x3A
68#define NAU8822_REG_LEFT_TIME_SLOT 0x3B
69#define NAU8822_REG_MISC 0x3C
70#define NAU8822_REG_RIGHT_TIME_SLOT 0x3D
71#define NAU8822_REG_DEVICE_REVISION 0x3E
72#define NAU8822_REG_DEVICE_ID 0x3F
73#define NAU8822_REG_DAC_DITHER 0x41
74#define NAU8822_REG_ALC_ENHANCE_1 0x46
75#define NAU8822_REG_ALC_ENHANCE_2 0x47
76#define NAU8822_REG_192KHZ_SAMPLING 0x48
77#define NAU8822_REG_MISC_CONTROL 0x49
78#define NAU8822_REG_INPUT_TIEOFF 0x4A
79#define NAU8822_REG_POWER_REDUCTION 0x4B
80#define NAU8822_REG_AGC_PEAK2PEAK 0x4C
81#define NAU8822_REG_AGC_PEAK_DETECT 0x4D
82#define NAU8822_REG_AUTOMUTE_CONTROL 0x4E
83#define NAU8822_REG_OUTPUT_TIEOFF 0x4F
84#define NAU8822_REG_MAX_REGISTER NAU8822_REG_OUTPUT_TIEOFF
85
86/* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
87#define NAU8822_REFIMP_MASK 0x3
88#define NAU8822_REFIMP_80K 0x1
89#define NAU8822_REFIMP_300K 0x2
90#define NAU8822_REFIMP_3K 0x3
91#define NAU8822_IOBUF_EN (0x1 << 2)
92#define NAU8822_ABIAS_EN (0x1 << 3)
93#define NAU8822_PLL_EN_MASK (0x1 << 5)
94#define NAU8822_PLL_ON (0x1 << 5)
95#define NAU8822_PLL_OFF (0x0 << 5)
96
97/* NAU8822_REG_AUDIO_INTERFACE (0x4) */
98#define NAU8822_AIFMT_MASK (0x3 << 3)
99#define NAU8822_WLEN_MASK (0x3 << 5)
100#define NAU8822_WLEN_20 (0x1 << 5)
101#define NAU8822_WLEN_24 (0x2 << 5)
102#define NAU8822_WLEN_32 (0x3 << 5)
103#define NAU8822_LRP_MASK (0x1 << 7)
104#define NAU8822_BCLKP_MASK (0x1 << 8)
105
106/* NAU8822_REG_COMPANDING_CONTROL (0x5) */
107#define NAU8822_ADDAP_SFT 0
108#define NAU8822_ADCCM_SFT 1
109#define NAU8822_DACCM_SFT 3
110
111/* NAU8822_REG_CLOCKING (0x6) */
112#define NAU8822_CLKIOEN_MASK 0x1
113#define NAU8822_CLK_MASTER 0x1
114#define NAU8822_CLK_SLAVE 0x0
115#define NAU8822_MCLKSEL_SFT 5
116#define NAU8822_MCLKSEL_MASK (0x7 << 5)
117#define NAU8822_BCLKSEL_SFT 2
118#define NAU8822_BCLKSEL_MASK (0x7 << 2)
119#define NAU8822_BCLKDIV_1 (0x0 << 2)
120#define NAU8822_BCLKDIV_2 (0x1 << 2)
121#define NAU8822_BCLKDIV_4 (0x2 << 2)
122#define NAU8822_BCLKDIV_8 (0x3 << 2)
123#define NAU8822_BCLKDIV_16 (0x4 << 2)
124#define NAU8822_CLKM_MASK (0x1 << 8)
125#define NAU8822_CLKM_MCLK (0x0 << 8)
126#define NAU8822_CLKM_PLL (0x1 << 8)
127
128/* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */
129#define NAU8822_SMPLR_SFT 1
130#define NAU8822_SMPLR_MASK (0x7 << 1)
131#define NAU8822_SMPLR_48K (0x0 << 1)
132#define NAU8822_SMPLR_32K (0x1 << 1)
133#define NAU8822_SMPLR_24K (0x2 << 1)
134#define NAU8822_SMPLR_16K (0x3 << 1)
135#define NAU8822_SMPLR_12K (0x4 << 1)
136#define NAU8822_SMPLR_8K (0x5 << 1)
137
138/* NAU8822_REG_EQ1 (0x12) */
139#define NAU8822_EQ1GC_SFT 0
140#define NAU8822_EQ1CF_SFT 5
141#define NAU8822_EQM_SFT 8
142
143/* NAU8822_REG_EQ2 (0x13) */
144#define NAU8822_EQ2GC_SFT 0
145#define NAU8822_EQ2CF_SFT 5
146#define NAU8822_EQ2BW_SFT 8
147
148/* NAU8822_REG_EQ3 (0x14) */
149#define NAU8822_EQ3GC_SFT 0
150#define NAU8822_EQ3CF_SFT 5
151#define NAU8822_EQ3BW_SFT 8
152
153/* NAU8822_REG_EQ4 (0x15) */
154#define NAU8822_EQ4GC_SFT 0
155#define NAU8822_EQ4CF_SFT 5
156#define NAU8822_EQ4BW_SFT 8
157
158/* NAU8822_REG_EQ5 (0x16) */
159#define NAU8822_EQ5GC_SFT 0
160#define NAU8822_EQ5CF_SFT 5
161
162/* NAU8822_REG_ALC_CONTROL_1 (0x20) */
163#define NAU8822_ALCMINGAIN_SFT 0
164#define NAU8822_ALCMXGAIN_SFT 3
165#define NAU8822_ALCEN_SFT 7
166
167/* NAU8822_REG_ALC_CONTROL_2 (0x21) */
168#define NAU8822_ALCSL_SFT 0
169#define NAU8822_ALCHT_SFT 4
170
171/* NAU8822_REG_ALC_CONTROL_3 (0x22) */
172#define NAU8822_ALCATK_SFT 0
173#define NAU8822_ALCDCY_SFT 4
174#define NAU8822_ALCM_SFT 8
175
176/* NAU8822_REG_PLL_N (0x24) */
177#define NAU8822_PLLMCLK_DIV2 (0x1 << 4)
178#define NAU8822_PLLN_MASK 0xF
179
180#define NAU8822_PLLK1_SFT 18
181#define NAU8822_PLLK1_MASK 0x3F
182
183/* NAU8822_REG_PLL_K2 (0x26) */
184#define NAU8822_PLLK2_SFT 9
185#define NAU8822_PLLK2_MASK 0x1FF
186
187/* NAU8822_REG_PLL_K3 (0x27) */
188#define NAU8822_PLLK3_MASK 0x1FF
189
190/* NAU8822_REG_RIGHT_SPEAKER_CONTROL (0x2B) */
191#define NAU8822_RMIXMUT 0x20
192#define NAU8822_RSUBBYP 0x10
193
194#define NAU8822_RAUXRSUBG_SFT 1
195#define NAU8822_RAUXRSUBG_MASK 0x0E
196
197#define NAU8822_RAUXSMUT 0x01
198
199/* System Clock Source */
200enum {
201 NAU8822_CLK_MCLK,
202 NAU8822_CLK_PLL,
203};
204
205struct nau8822_pll {
206 int pre_factor;
207 int mclk_scaler;
208 int pll_frac;
209 int pll_int;
210 int freq_in;
211 int freq_out;
212};
213
214/* Codec Private Data */
215struct nau8822 {
216 struct device *dev;
217 struct regmap *regmap;
218 struct clk *mclk;
219 struct nau8822_pll pll;
220 int sysclk;
221 int div_id;
222};
223
224#endif /* __NAU8822_H__ */