1// SPDX-License-Identifier: GPL-2.0-only
  2//
  3// aw88081.h  --  AW88081 ALSA SoC Audio driver
  4//
  5// Copyright (c) 2024 awinic Technology CO., LTD
  6//
  7// Author: Weidong Wang <wangweidong.a@awinic.com>
  8//
  9
 10#ifndef __AW88081_H__
 11#define __AW88081_H__
 12
 13#define AW88081_ID_REG			(0x00)
 14#define AW88081_SYSST_REG		(0x01)
 15#define AW88081_SYSINT_REG		(0x02)
 16#define AW88081_SYSINTM_REG		(0x03)
 17#define AW88081_SYSCTRL_REG		(0x04)
 18#define AW88081_SYSCTRL2_REG		(0x05)
 19#define AW88081_I2SCTRL1_REG		(0x06)
 20#define AW88081_I2SCTRL2_REG		(0x07)
 21#define AW88081_I2SCTRL3_REG		(0x08)
 22#define AW88081_DACCFG1_REG		(0x09)
 23#define AW88081_DACCFG2_REG		(0x0A)
 24#define AW88081_DACCFG3_REG		(0x0B)
 25#define AW88081_DACCFG4_REG		(0x0C)
 26#define AW88081_DACCFG5_REG		(0x0D)
 27#define AW88081_DACCFG6_REG		(0x0E)
 28#define AW88081_DACCFG7_REG		(0x11)
 29#define AW88081_PWMCTRL1_REG		(0x13)
 30#define AW88081_PWMCTRL2_REG		(0x14)
 31#define AW88081_PWMCTRL3_REG		(0x15)
 32#define AW88081_PWMCTRL4_REG		(0x16)
 33#define AW88081_I2SCFG1_REG		(0x17)
 34#define AW88081_DBGCTRL_REG		(0x18)
 35#define AW88081_PDMCTRL_REG		(0x19)
 36#define AW88081_DACST_REG		(0x20)
 37#define AW88081_PATTERNST_REG		(0x21)
 38#define AW88081_I2SINT_REG		(0x26)
 39#define AW88081_I2SCAPCNT_REG		(0x27)
 40#define AW88081_ANASTA1_REG		(0x28)
 41#define AW88081_ANASTA2_REG		(0x29)
 42#define AW88081_ANASTA3_REG		(0x2A)
 43#define AW88081_VBAT_REG		(0x21)
 44#define AW88081_TEMP_REG		(0x22)
 45#define AW88081_PVDD_REG		(0x23)
 46#define AW88081_ISNDAT_REG		(0x24)
 47#define AW88081_VSNDAT_REG		(0x25)
 48#define AW88081_DSMCFG1_REG		(0x30)
 49#define AW88081_DSMCFG2_REG		(0x31)
 50#define AW88081_DSMCFG3_REG		(0x32)
 51#define AW88081_DSMCFG4_REG		(0x33)
 52#define AW88081_DSMCFG5_REG		(0x34)
 53#define AW88081_DSMCFG6_REG		(0x35)
 54#define AW88081_DSMCFG7_REG		(0x36)
 55#define AW88081_DSMCFG8_REG		(0x37)
 56#define AW88081_TESTIN_REG		(0x38)
 57#define AW88081_TESTOUT_REG		(0x39)
 58#define AW88081_BOPCTRL1_REG		(0x40)
 59#define AW88081_BOPCTRL2_REG		(0x41)
 60#define AW88081_BOPCTRL3_REG		(0x42)
 61#define AW88081_BOPSTA_REG		(0x43)
 62#define AW88081_PLLCTRL1_REG		(0x54)
 63#define AW88081_PLLCTRL2_REG		(0x55)
 64#define AW88081_PLLCTRL3_REG		(0x56)
 65#define AW88081_CDACTRL1_REG		(0x57)
 66#define AW88081_CDACTRL2_REG		(0x58)
 67#define AW88081_CDACTRL3_REG		(0x59)
 68#define AW88081_DITHERCFG1_REG		(0x5A)
 69#define AW88081_DITHERCFG2_REG		(0x5B)
 70#define AW88081_DITHERCFG3_REG		(0x5C)
 71#define AW88081_TM_REG			(0x6E)
 72#define AW88081_TM2_REG		(0x6F)
 73#define AW88081_TESTCTRL1_REG		(0x70)
 74#define AW88081_TESTCTRL2_REG		(0x71)
 75
 76#define AW88081_REG_MAX		(0x72)
 77
 78#define AW88081_UVLS_START_BIT		(14)
 79#define AW88081_UVLS_UVLO		(1)
 80#define AW88081_UVLS_UVLO_VALUE	\
 81	(AW88081_UVLS_UVLO << AW88081_UVLS_START_BIT)
 82
 83#define AW88081_SWS_START_BIT		(8)
 84#define AW88081_SWS_SWITCHING		(1)
 85#define AW88081_SWS_SWITCHING_VALUE	\
 86	(AW88081_SWS_SWITCHING << AW88081_SWS_START_BIT)
 87
 88#define AW88081_NOCLKS_START_BIT	(5)
 89#define AW88081_NOCLKS_NO_CLOCK	(1)
 90#define AW88081_NOCLKS_NO_CLOCK_VALUE	\
 91	(AW88081_NOCLKS_NO_CLOCK << AW88081_NOCLKS_START_BIT)
 92
 93#define AW88081_CLKS_START_BIT		(4)
 94#define AW88081_CLKS_STABLE		(1)
 95#define AW88081_CLKS_STABLE_VALUE	\
 96	(AW88081_CLKS_STABLE << AW88081_CLKS_START_BIT)
 97
 98#define AW88081_OCDS_START_BIT		(3)
 99#define AW88081_OCDS_OC		(1)
100#define AW88081_OCDS_OC_VALUE		\
101	(AW88081_OCDS_OC << AW88081_OCDS_START_BIT)
102
103#define AW88081_OTHS_START_BIT		(1)
104#define AW88081_OTHS_OT		(1)
105#define AW88081_OTHS_OT_VALUE		\
106	(AW88081_OTHS_OT << AW88081_OTHS_START_BIT)
107
108#define AW88081_PLLS_START_BIT		(0)
109#define AW88081_PLLS_LOCKED		(1)
110#define AW88081_PLLS_LOCKED_VALUE	\
111	(AW88081_PLLS_LOCKED << AW88081_PLLS_START_BIT)
112
113#define AW88081_BIT_PLL_CHECK \
114		(AW88081_CLKS_STABLE_VALUE | \
115		AW88081_PLLS_LOCKED_VALUE)
116
117#define AW88081_BIT_SYSST_CHECK_MASK \
118		(~(AW88081_UVLS_UVLO_VALUE | \
119		AW88081_SWS_SWITCHING_VALUE | \
120		AW88081_NOCLKS_NO_CLOCK_VALUE | \
121		AW88081_CLKS_STABLE_VALUE | \
122		AW88081_OCDS_OC_VALUE | \
123		AW88081_OTHS_OT_VALUE | \
124		AW88081_PLLS_LOCKED_VALUE))
125
126#define AW88081_NO_SWS_SYSST_CHECK \
127		(AW88081_CLKS_STABLE_VALUE | \
128		AW88081_PLLS_LOCKED_VALUE)
129
130#define AW88081_SWS_SYSST_CHECK \
131	(AW88081_SWS_SWITCHING_VALUE | \
132	AW88081_CLKS_STABLE_VALUE | \
133	AW88081_PLLS_LOCKED_VALUE)
134
135#define AW88081_ULS_HMUTE_START_BIT	(14)
136#define AW88081_ULS_HMUTE_BITS_LEN	(1)
137#define AW88081_ULS_HMUTE_MASK		\
138	(~(((1<<AW88081_ULS_HMUTE_BITS_LEN)-1) << AW88081_ULS_HMUTE_START_BIT))
139
140#define AW88081_ULS_HMUTE_DISABLE	(0)
141#define AW88081_ULS_HMUTE_DISABLE_VALUE	\
142	(AW88081_ULS_HMUTE_DISABLE << AW88081_ULS_HMUTE_START_BIT)
143
144#define AW88081_ULS_HMUTE_ENABLE	(1)
145#define AW88081_ULS_HMUTE_ENABLE_VALUE	\
146	(AW88081_ULS_HMUTE_ENABLE << AW88081_ULS_HMUTE_START_BIT)
147
148#define AW88081_HMUTE_START_BIT	(8)
149#define AW88081_HMUTE_BITS_LEN		(1)
150#define AW88081_HMUTE_MASK		\
151	(~(((1<<AW88081_HMUTE_BITS_LEN)-1) << AW88081_HMUTE_START_BIT))
152
153#define AW88081_HMUTE_DISABLE		(0)
154#define AW88081_HMUTE_DISABLE_VALUE	\
155	(AW88081_HMUTE_DISABLE << AW88081_HMUTE_START_BIT)
156
157#define AW88081_HMUTE_ENABLE		(1)
158#define AW88081_HMUTE_ENABLE_VALUE	\
159	(AW88081_HMUTE_ENABLE << AW88081_HMUTE_START_BIT)
160
161#define AW88081_EN_PA_START_BIT	(1)
162#define AW88081_EN_PA_BITS_LEN		(1)
163#define AW88081_EN_PA_MASK		\
164	(~(((1<<AW88081_EN_PA_BITS_LEN)-1) << AW88081_EN_PA_START_BIT))
165
166#define AW88081_EN_PA_WORKING		(1)
167#define AW88081_EN_PA_WORKING_VALUE	\
168	(AW88081_EN_PA_WORKING << AW88081_EN_PA_START_BIT)
169
170#define AW88081_EN_PA_POWER_DOWN	(0)
171#define AW88081_EN_PA_POWER_DOWN_VALUE	\
172	(AW88081_EN_PA_POWER_DOWN << AW88081_EN_PA_START_BIT)
173
174#define AW88081_PWDN_START_BIT		(0)
175#define AW88081_PWDN_BITS_LEN		(1)
176#define AW88081_PWDN_MASK		\
177	(~(((1<<AW88081_PWDN_BITS_LEN)-1) << AW88081_PWDN_START_BIT))
178
179#define AW88081_PWDN_WORKING		(0)
180#define AW88081_PWDN_WORKING_VALUE	\
181	(AW88081_PWDN_WORKING << AW88081_PWDN_START_BIT)
182
183#define AW88081_PWDN_POWER_DOWN	(1)
184#define AW88081_PWDN_POWER_DOWN_VALUE	\
185	(AW88081_PWDN_POWER_DOWN << AW88081_PWDN_START_BIT)
186
187#define AW88081_VOL_START_BIT		(0)
188#define AW88081_VOL_BITS_LEN		(10)
189#define AW88081_VOL_MASK		\
190	(~(((1<<AW88081_VOL_BITS_LEN)-1) << AW88081_VOL_START_BIT))
191
192#define AW88081_VOLUME_STEP_DB		(64)
193#define AW88081_MUTE_VOL		(1023)
194
195#define AW88081_I2STXEN_START_BIT	(6)
196#define AW88081_I2STXEN_BITS_LEN	(1)
197#define AW88081_I2STXEN_MASK		\
198	(~(((1<<AW88081_I2STXEN_BITS_LEN)-1) << AW88081_I2STXEN_START_BIT))
199
200#define AW88081_I2STXEN_DISABLE	(0)
201#define AW88081_I2STXEN_DISABLE_VALUE	\
202	(AW88081_I2STXEN_DISABLE << AW88081_I2STXEN_START_BIT)
203
204#define AW88081_I2STXEN_ENABLE		(1)
205#define AW88081_I2STXEN_ENABLE_VALUE	\
206	(AW88081_I2STXEN_ENABLE << AW88081_I2STXEN_START_BIT)
207
208#define AW88081_NOISE_GATE_EN_START_BIT	(13)
209#define AW88081_NOISE_GATE_EN_BITS_LEN	(1)
210#define AW88081_NOISE_GATE_EN_MASK	\
211		(~(((1<<AW88081_NOISE_GATE_EN_BITS_LEN)-1) << AW88081_NOISE_GATE_EN_START_BIT))
212
213#define AW88081_NOISE_GATE_EN_DISABLE	(0)
214#define AW88081_NOISE_GATE_EN_DISABLE_VALUE	\
215		(AW88081_NOISE_GATE_EN_DISABLE << AW88081_NOISE_GATE_EN_START_BIT)
216
217#define AW88081_NOISE_GATE_EN_ENABLE	(1)
218#define AW88081_NOISE_GATE_EN_ENABLE_VALUE	\
219		(AW88081_NOISE_GATE_EN_ENABLE << AW88081_NOISE_GATE_EN_START_BIT)
220
221#define AW88081_CCO_MUX_START_BIT	(13)
222#define AW88081_CCO_MUX_BITS_LEN	(1)
223#define AW88081_CCO_MUX_MASK		\
224	(~(((1<<AW88081_CCO_MUX_BITS_LEN)-1) << AW88081_CCO_MUX_START_BIT))
225
226#define AW88081_CCO_MUX_DIVIDED	(0)
227#define AW88081_CCO_MUX_DIVIDED_VALUE	\
228	(AW88081_CCO_MUX_DIVIDED << AW88081_CCO_MUX_START_BIT)
229
230#define AW88081_CCO_MUX_BYPASS		(1)
231#define AW88081_CCO_MUX_BYPASS_VALUE	\
232	(AW88081_CCO_MUX_BYPASS << AW88081_CCO_MUX_START_BIT)
233
234#define AW88081_START_RETRIES		(5)
235#define AW88081_START_WORK_DELAY_MS	(0)
236
237#define AW88081_I2C_NAME		"aw88081"
238#define AW88081_CHIP_ID		0x2116
239
240#define AW88081_RATES (SNDRV_PCM_RATE_8000_48000 | \
241			SNDRV_PCM_RATE_96000)
242#define AW88081_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
243			SNDRV_PCM_FMTBIT_S24_LE | \
244			SNDRV_PCM_FMTBIT_S32_LE)
245
246#define FADE_TIME_MAX			100000
247
248#define AW88081_DEV_DEFAULT_CH		(0)
249#define AW88081_ACF_FILE		"aw88081_acf.bin"
250#define AW88081_DEV_SYSST_CHECK_MAX	(10)
251#define AW88081_SOFT_RESET_VALUE	(0x55aa)
252
253#define AW88081_INIT_PROFILE		(0)
254
255#define AW88081_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \
256{ \
257	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
258	.name = xname, \
259	.info = profile_info, \
260	.get = profile_get, \
261	.put = profile_set, \
262}
263
264enum {
265	AW88081_SYNC_START = 0,
266	AW88081_ASYNC_START,
267};
268
269enum {
270	AW88081_500_US = 500,
271	AW88081_1000_US = 1000,
272	AW88081_2000_US = 2000,
273	AW88081_5000_US = 5000,
274};
275
276enum {
277	AW88081_DEV_PW_OFF = 0,
278	AW88081_DEV_PW_ON,
279};
280
281enum {
282	AW88081_DEV_FW_FAILED = 0,
283	AW88081_DEV_FW_OK,
284};
285
286#endif