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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence CDNSP DRD Driver.
4 *
5 * Copyright (C) 2020 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 *
9 * Code based on Linux XHCI driver.
10 * Origin: Copyright (C) 2008 Intel Corp.
11 */
12#ifndef __LINUX_CDNSP_GADGET_H
13#define __LINUX_CDNSP_GADGET_H
14
15#include <linux/io-64-nonatomic-lo-hi.h>
16#include <linux/usb/gadget.h>
17#include <linux/irq.h>
18
19/* Max number slots - only 1 is allowed. */
20#define CDNSP_DEV_MAX_SLOTS 1
21
22#define CDNSP_EP0_SETUP_SIZE 512
23
24/* One control and 15 for in and 15 for out endpoints. */
25#define CDNSP_ENDPOINTS_NUM 31
26
27/* Best Effort Service Latency. */
28#define CDNSP_DEFAULT_BESL 0
29
30/* Device Controller command default timeout value in us */
31#define CDNSP_CMD_TIMEOUT (15 * 1000)
32
33/* Up to 16 ms to halt an device controller */
34#define CDNSP_MAX_HALT_USEC (16 * 1000)
35
36#define CDNSP_CTX_SIZE 2112
37
38/*
39 * Controller register interface.
40 */
41
42/**
43 * struct cdnsp_cap_regs - CDNSP Registers.
44 * @hc_capbase: Length of the capabilities register and controller
45 * version number
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
52 * @hcc_params2: HCCPARAMS2 Capability Parameters 2,
53 */
54struct cdnsp_cap_regs {
55 __le32 hc_capbase;
56 __le32 hcs_params1;
57 __le32 hcs_params2;
58 __le32 hcs_params3;
59 __le32 hcc_params;
60 __le32 db_off;
61 __le32 run_regs_off;
62 __le32 hcc_params2;
63 /* Reserved up to (CAPLENGTH - 0x1C) */
64};
65
66/* hc_capbase bitmasks. */
67/* bits 7:0 - how long is the Capabilities register. */
68#define HC_LENGTH(p) (((p) >> 00) & GENMASK(7, 0))
69/* bits 31:16 */
70#define HC_VERSION(p) (((p) >> 16) & GENMASK(15, 1))
71
72/* HCSPARAMS1 - hcs_params1 - bitmasks */
73/* bits 0:7, Max Device Endpoints */
74#define HCS_ENDPOINTS_MASK GENMASK(7, 0)
75#define HCS_ENDPOINTS(p) (((p) & HCS_ENDPOINTS_MASK) >> 0)
76
77/* HCCPARAMS offset from PCI base address */
78#define HCC_PARAMS_OFFSET 0x10
79
80/* HCCPARAMS - hcc_params - bitmasks */
81/* 1: device controller can use 64-bit address pointers. */
82#define HCC_64BIT_ADDR(p) ((p) & BIT(0))
83/* 1: device controller uses 64-byte Device Context structures. */
84#define HCC_64BYTE_CONTEXT(p) ((p) & BIT(2))
85/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15. */
86#define HCC_MAX_PSA(p) ((((p) >> 12) & 0xf) + 1)
87/* Extended Capabilities pointer from PCI base. */
88#define HCC_EXT_CAPS(p) (((p) & GENMASK(31, 16)) >> 16)
89
90#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
91
92/* db_off bitmask - bits 0:1 reserved. */
93#define DBOFF_MASK GENMASK(31, 2)
94
95/* run_regs_off bitmask - bits 0:4 reserved. */
96#define RTSOFF_MASK GENMASK(31, 5)
97
98/**
99 * struct cdnsp_op_regs - Device Controller Operational Registers.
100 * @command: USBCMD - Controller command register.
101 * @status: USBSTS - Controller status register.
102 * @page_size: This indicates the page size that the device controller supports.
103 * If bit n is set, the controller supports a page size of 2^(n+12),
104 * up to a 128MB page size. 4K is the minimum page size.
105 * @dnctrl: DNCTRL - Device notification control register.
106 * @cmd_ring: CRP - 64-bit Command Ring Pointer.
107 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer.
108 * @config_reg: CONFIG - Configure Register
109 * @port_reg_base: PORTSCn - base address for Port Status and Control
110 * Each port has a Port Status and Control register,
111 * followed by a Port Power Management Status and Control
112 * register, a Port Link Info register, and a reserved
113 * register.
114 */
115struct cdnsp_op_regs {
116 __le32 command;
117 __le32 status;
118 __le32 page_size;
119 __le32 reserved1;
120 __le32 reserved2;
121 __le32 dnctrl;
122 __le64 cmd_ring;
123 /* rsvd: offset 0x20-2F. */
124 __le32 reserved3[4];
125 __le64 dcbaa_ptr;
126 __le32 config_reg;
127 /* rsvd: offset 0x3C-3FF. */
128 __le32 reserved4[241];
129 /* port 1 registers, which serve as a base address for other ports. */
130 __le32 port_reg_base;
131};
132
133/* Number of registers per port. */
134#define NUM_PORT_REGS 4
135
136/**
137 * struct cdnsp_port_regs - Port Registers.
138 * @portsc: PORTSC - Port Status and Control Register.
139 * @portpmsc: PORTPMSC - Port Power Managements Status and Control Register.
140 * @portli: PORTLI - Port Link Info register.
141 */
142struct cdnsp_port_regs {
143 __le32 portsc;
144 __le32 portpmsc;
145 __le32 portli;
146 __le32 reserved;
147};
148
149/*
150 * These bits are Read Only (RO) and should be saved and written to the
151 * registers: 0 (connect status) and 10:13 (port speed).
152 * These bits are also sticky - meaning they're in the AUX well and they aren't
153 * changed by a hot and warm.
154 */
155#define CDNSP_PORT_RO (PORT_CONNECT | DEV_SPEED_MASK)
156
157/*
158 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
159 * bits 5:8 (link state), 25:26 ("wake on" enable state)
160 */
161#define CDNSP_PORT_RWS (PORT_PLS_MASK | PORT_WKCONN_E | PORT_WKDISC_E)
162
163/*
164 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
165 * bits 1 (port enable/disable), 17 ( connect changed),
166 * 21 (port reset changed) , 22 (Port Link State Change),
167 */
168#define CDNSP_PORT_RW1CS (PORT_PED | PORT_CSC | PORT_RC | PORT_PLC)
169
170/* USBCMD - USB command - bitmasks. */
171/* Run/Stop, controller execution - do not write unless controller is halted.*/
172#define CMD_R_S BIT(0)
173/*
174 * Reset device controller - resets internal controller state machine and all
175 * registers (except PCI config regs).
176 */
177#define CMD_RESET BIT(1)
178/* Event Interrupt Enable - a '1' allows interrupts from the controller. */
179#define CMD_INTE BIT(2)
180/*
181 * Device System Error Interrupt Enable - get out-of-band signal for
182 * controller errors.
183 */
184#define CMD_DSEIE BIT(3)
185/* device controller save/restore state. */
186#define CMD_CSS BIT(8)
187#define CMD_CRS BIT(9)
188/*
189 * Enable Wrap Event - '1' means device controller generates an event
190 * when MFINDEX wraps.
191 */
192#define CMD_EWE BIT(10)
193/* 1: device enabled */
194#define CMD_DEVEN BIT(17)
195/* bits 18:31 are reserved (and should be preserved on writes). */
196
197/* Command register values to disable interrupts. */
198#define CDNSP_IRQS (CMD_INTE | CMD_DSEIE | CMD_EWE)
199
200/* USBSTS - USB status - bitmasks */
201/* controller not running - set to 1 when run/stop bit is cleared. */
202#define STS_HALT BIT(0)
203/*
204 * serious error, e.g. PCI parity error. The controller will clear
205 * the run/stop bit.
206 */
207#define STS_FATAL BIT(2)
208/* event interrupt - clear this prior to clearing any IP flags in IR set.*/
209#define STS_EINT BIT(3)
210/* port change detect */
211#define STS_PCD BIT(4)
212/* save state status - '1' means device controller is saving state. */
213#define STS_SSS BIT(8)
214/* restore state status - '1' means controllers is restoring state. */
215#define STS_RSS BIT(9)
216/* 1: save or restore error */
217#define STS_SRE BIT(10)
218/* 1: device Not Ready to accept doorbell or op reg writes after reset. */
219#define STS_CNR BIT(11)
220/* 1: internal Device Controller Error.*/
221#define STS_HCE BIT(12)
222
223/* CRCR - Command Ring Control Register - cmd_ring bitmasks. */
224/* bit 0 is the command ring cycle state. */
225#define CMD_RING_CS BIT(0)
226/* stop ring immediately - abort the currently executing command. */
227#define CMD_RING_ABORT BIT(2)
228/*
229 * Command Ring Busy.
230 * Set when Doorbell register is written with DB for command and cleared when
231 * the controller reached end of CR.
232 */
233#define CMD_RING_BUSY(p) ((p) & BIT(4))
234/* 1: command ring is running */
235#define CMD_RING_RUNNING BIT(3)
236/* Command Ring pointer - bit mask for the lower 32 bits. */
237#define CMD_RING_RSVD_BITS GENMASK(5, 0)
238
239/* CONFIG - Configure Register - config_reg bitmasks. */
240/* bits 0:7 - maximum number of device slots enabled. */
241#define MAX_DEVS GENMASK(7, 0)
242/* bit 8: U3 Entry Enabled, assert PLC when controller enters U3. */
243#define CONFIG_U3E BIT(8)
244
245/* PORTSC - Port Status and Control Register - port_reg_base bitmasks */
246/* 1: device connected. */
247#define PORT_CONNECT BIT(0)
248/* 1: port enabled. */
249#define PORT_PED BIT(1)
250/* 1: port reset signaling asserted. */
251#define PORT_RESET BIT(4)
252/*
253 * Port Link State - bits 5:8
254 * A read gives the current link PM state of the port,
255 * a write with Link State Write Strobe sets the link state.
256 */
257#define PORT_PLS_MASK GENMASK(8, 5)
258#define XDEV_U0 (0x0 << 5)
259#define XDEV_U1 (0x1 << 5)
260#define XDEV_U2 (0x2 << 5)
261#define XDEV_U3 (0x3 << 5)
262#define XDEV_DISABLED (0x4 << 5)
263#define XDEV_RXDETECT (0x5 << 5)
264#define XDEV_INACTIVE (0x6 << 5)
265#define XDEV_POLLING (0x7 << 5)
266#define XDEV_RECOVERY (0x8 << 5)
267#define XDEV_HOT_RESET (0x9 << 5)
268#define XDEV_COMP_MODE (0xa << 5)
269#define XDEV_TEST_MODE (0xb << 5)
270#define XDEV_RESUME (0xf << 5)
271/* 1: port has power. */
272#define PORT_POWER BIT(9)
273/*
274 * bits 10:13 indicate device speed:
275 * 0 - undefined speed - port hasn't be initialized by a reset yet
276 * 1 - full speed
277 * 2 - Reserved (Low Speed not supported
278 * 3 - high speed
279 * 4 - super speed
280 * 5 - super speed
281 * 6-15 reserved
282 */
283#define DEV_SPEED_MASK GENMASK(13, 10)
284#define XDEV_FS (0x1 << 10)
285#define XDEV_HS (0x3 << 10)
286#define XDEV_SS (0x4 << 10)
287#define XDEV_SSP (0x5 << 10)
288#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0 << 10))
289#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
290#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
291#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
292#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
293#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
294#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
295/* Port Link State Write Strobe - set this when changing link state */
296#define PORT_LINK_STROBE BIT(16)
297/* 1: connect status change */
298#define PORT_CSC BIT(17)
299/* 1: warm reset for a USB 3.0 device is done. */
300#define PORT_WRC BIT(19)
301/* 1: reset change - 1 to 0 transition of PORT_RESET */
302#define PORT_RC BIT(21)
303/*
304 * port link status change - set on some port link state transitions:
305 * Transition Reason
306 * ----------------------------------------------------------------------------
307 * - U3 to Resume Wakeup signaling from a device
308 * - Resume to Recovery to U0 USB 3.0 device resume
309 * - Resume to U0 USB 2.0 device resume
310 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
311 * - U3 to U0 Software resume of USB 2.0 device complete
312 * - U2 to U0 L1 resume of USB 2.1 device complete
313 * - U0 to U0 L1 entry rejection by USB 2.1 device
314 * - U0 to disabled L1 entry error with USB 2.1 device
315 * - Any state to inactive Error on USB 3.0 port
316 */
317#define PORT_PLC BIT(22)
318/* Port configure error change - port failed to configure its link partner. */
319#define PORT_CEC BIT(23)
320/* Wake on connect (enable). */
321#define PORT_WKCONN_E BIT(25)
322/* Wake on disconnect (enable). */
323#define PORT_WKDISC_E BIT(26)
324/* Indicates if Warm Reset is being received. */
325#define PORT_WR BIT(31)
326
327#define PORT_CHANGE_BITS (PORT_CSC | PORT_WRC | PORT_RC | PORT_PLC | PORT_CEC)
328
329/* PORTPMSCUSB3 - Port Power Management Status and Control - bitmasks. */
330/* Enables U1 entry. */
331#define PORT_U1_TIMEOUT_MASK GENMASK(7, 0)
332#define PORT_U1_TIMEOUT(p) ((p) & PORT_U1_TIMEOUT_MASK)
333/* Enables U2 entry .*/
334#define PORT_U2_TIMEOUT_MASK GENMASK(14, 8)
335#define PORT_U2_TIMEOUT(p) (((p) << 8) & PORT_U2_TIMEOUT_MASK)
336
337/* PORTPMSCUSB2 - Port Power Management Status and Control - bitmasks. */
338#define PORT_L1S_MASK GENMASK(2, 0)
339#define PORT_L1S(p) ((p) & PORT_L1S_MASK)
340#define PORT_L1S_ACK PORT_L1S(1)
341#define PORT_L1S_NYET PORT_L1S(2)
342#define PORT_L1S_STALL PORT_L1S(3)
343#define PORT_L1S_TIMEOUT PORT_L1S(4)
344/* Remote Wake Enable. */
345#define PORT_RWE BIT(3)
346/* Best Effort Service Latency (BESL). */
347#define PORT_BESL(p) (((p) << 4) & GENMASK(7, 4))
348/* Hardware LPM Enable (HLE). */
349#define PORT_HLE BIT(16)
350/* Received Best Effort Service Latency (BESL). */
351#define PORT_RRBESL(p) (((p) & GENMASK(20, 17)) >> 17)
352/* Port Test Control. */
353#define PORT_TEST_MODE_MASK GENMASK(31, 28)
354#define PORT_TEST_MODE(p) (((p) << 28) & PORT_TEST_MODE_MASK)
355
356/**
357 * struct cdnsp_intr_reg - Interrupt Register Set.
358 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
359 * interrupts and check for pending interrupts.
360 * @irq_control: IMOD - Interrupt Moderation Register.
361 * Used to throttle interrupts.
362 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
363 * @erst_base: ERST base address.
364 * @erst_dequeue: Event ring dequeue pointer.
365 *
366 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
367 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
368 * multiple segments of the same size. The controller places events on the ring
369 * and "updates the Cycle bit in the TRBs to indicate to software the current
370 * position of the Enqueue Pointer." The driver processes those events and
371 * updates the dequeue pointer.
372 */
373struct cdnsp_intr_reg {
374 __le32 irq_pending;
375 __le32 irq_control;
376 __le32 erst_size;
377 __le32 rsvd;
378 __le64 erst_base;
379 __le64 erst_dequeue;
380};
381
382/* IMAN - Interrupt Management Register - irq_pending bitmasks l. */
383#define IMAN_IE BIT(1)
384#define IMAN_IP BIT(0)
385/* bits 2:31 need to be preserved */
386#define IMAN_IE_SET(p) ((p) | IMAN_IE)
387#define IMAN_IE_CLEAR(p) ((p) & ~IMAN_IE)
388
389/* IMOD - Interrupter Moderation Register - irq_control bitmasks. */
390/*
391 * Minimum interval between interrupts (in 250ns intervals). The interval
392 * between interrupts will be longer if there are no events on the event ring.
393 * Default is 4000 (1 ms).
394 */
395#define IMOD_INTERVAL_MASK GENMASK(15, 0)
396/* Counter used to count down the time to the next interrupt - HW use only */
397#define IMOD_COUNTER_MASK GENMASK(31, 16)
398#define IMOD_DEFAULT_INTERVAL 0
399
400/* erst_size bitmasks. */
401/* Preserve bits 16:31 of erst_size. */
402#define ERST_SIZE_MASK GENMASK(31, 16)
403
404/* erst_dequeue bitmasks. */
405/*
406 * Dequeue ERST Segment Index (DESI) - Segment number (or alias)
407 * where the current dequeue pointer lies. This is an optional HW hint.
408 */
409#define ERST_DESI_MASK GENMASK(2, 0)
410/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced. */
411#define ERST_EHB BIT(3)
412#define ERST_PTR_MASK GENMASK(3, 0)
413
414/**
415 * struct cdnsp_run_regs
416 * @microframe_index: MFINDEX - current microframe number.
417 * @ir_set: Array of Interrupter registers.
418 *
419 * Device Controller Runtime Registers:
420 * "Software should read and write these registers using only Dword (32 bit)
421 * or larger accesses"
422 */
423struct cdnsp_run_regs {
424 __le32 microframe_index;
425 __le32 rsvd[7];
426 struct cdnsp_intr_reg ir_set[128];
427};
428
429/**
430 * USB2.0 Port Peripheral Configuration Registers.
431 * @ext_cap: Header register for Extended Capability.
432 * @port_reg1: Timer Configuration Register.
433 * @port_reg2: Timer Configuration Register.
434 * @port_reg3: Timer Configuration Register.
435 * @port_reg4: Timer Configuration Register.
436 * @port_reg5: Timer Configuration Register.
437 * @port_reg6: Chicken bits for USB20PPP.
438 */
439struct cdnsp_20port_cap {
440 __le32 ext_cap;
441 __le32 port_reg1;
442 __le32 port_reg2;
443 __le32 port_reg3;
444 __le32 port_reg4;
445 __le32 port_reg5;
446 __le32 port_reg6;
447};
448
449/* Extended capability register fields */
450#define EXT_CAPS_ID(p) (((p) >> 0) & GENMASK(7, 0))
451#define EXT_CAPS_NEXT(p) (((p) >> 8) & GENMASK(7, 0))
452/* Extended capability IDs - ID 0 reserved */
453#define EXT_CAPS_PROTOCOL 2
454
455/* USB 2.0 Port Peripheral Configuration Extended Capability */
456#define EXT_CAP_CFG_DEV_20PORT_CAP_ID 0xC1
457/*
458 * Setting this bit to '1' enables automatic wakeup from L1 state on transfer
459 * TRB prepared when USBSSP operates in USB2.0 mode.
460 */
461#define PORT_REG6_L1_L0_HW_EN BIT(1)
462/*
463 * Setting this bit to '1' forces Full Speed when USBSSP operates in USB2.0
464 * mode (disables High Speed).
465 */
466#define PORT_REG6_FORCE_FS BIT(0)
467
468/**
469 * USB3.x Port Peripheral Configuration Registers.
470 * @ext_cap: Header register for Extended Capability.
471 * @mode_addr: Miscellaneous 3xPORT operation mode configuration register.
472 * @mode_2: 3x Port Control Register 2.
473 */
474struct cdnsp_3xport_cap {
475 __le32 ext_cap;
476 __le32 mode_addr;
477 __le32 reserved[52];
478 __le32 mode_2;
479};
480
481/* Extended Capability Header for 3XPort Configuration Registers. */
482#define D_XEC_CFG_3XPORT_CAP 0xC0
483#define CFG_3XPORT_SSP_SUPPORT BIT(31)
484#define CFG_3XPORT_U1_PIPE_CLK_GATE_EN BIT(0)
485
486/* Revision Extended Capability ID */
487#define RTL_REV_CAP 0xC4
488#define RTL_REV_CAP_RX_BUFF_CMD_SIZE BITMASK(31, 24)
489#define RTL_REV_CAP_RX_BUFF_SIZE BITMASK(15, 0)
490#define RTL_REV_CAP_TX_BUFF_CMD_SIZE BITMASK(31, 24)
491#define RTL_REV_CAP_TX_BUFF_SIZE BITMASK(15, 0)
492
493#define CDNSP_VER_1 0x00000000
494#define CDNSP_VER_2 0x10000000
495
496#define CDNSP_IF_EP_EXIST(pdev, ep_num, dir) \
497 (readl(&(pdev)->rev_cap->ep_supported) & \
498 (BIT(ep_num) << ((dir) ? 0 : 16)))
499
500/**
501 * struct cdnsp_rev_cap - controller capabilities.
502 * @ext_cap: Header for RTL Revision Extended Capability.
503 * @rtl_revision: RTL revision.
504 * @rx_buff_size: Rx buffer sizes.
505 * @tx_buff_size: Tx buffer sizes.
506 * @ep_supported: Supported endpoints.
507 * @ctrl_revision: Controller revision ID.
508 */
509struct cdnsp_rev_cap {
510 __le32 ext_cap;
511 __le32 rtl_revision;
512 __le32 rx_buff_size;
513 __le32 tx_buff_size;
514 __le32 ep_supported;
515 __le32 ctrl_revision;
516};
517
518/* USB2.0 Port Peripheral Configuration Registers. */
519#define D_XEC_PRE_REGS_CAP 0xC8
520#define REG_CHICKEN_BITS_2_OFFSET 0x48
521#define CHICKEN_XDMA_2_TP_CACHE_DIS BIT(28)
522
523/* XBUF Extended Capability ID. */
524#define XBUF_CAP_ID 0xCB
525#define XBUF_RX_TAG_MASK_0_OFFSET 0x1C
526#define XBUF_RX_TAG_MASK_1_OFFSET 0x24
527#define XBUF_TX_CMD_OFFSET 0x2C
528
529/**
530 * struct cdnsp_doorbell_array.
531 * @cmd_db: Command ring doorbell register.
532 * @ep_db: Endpoint ring doorbell register.
533 * Bits 0 - 7: Endpoint target.
534 * Bits 8 - 15: RsvdZ.
535 * Bits 16 - 31: Stream ID.
536 */
537struct cdnsp_doorbell_array {
538 __le32 cmd_db;
539 __le32 ep_db;
540};
541
542#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
543#define DB_VALUE_EP0_OUT(ep, stream) ((ep) & 0xff)
544#define DB_VALUE_CMD 0x00000000
545
546/**
547 * struct cdnsp_container_ctx.
548 * @type: Type of context. Used to calculated offsets to contained contexts.
549 * @size: Size of the context data.
550 * @ctx_size: context data structure size - 64 or 32 bits.
551 * @dma: dma address of the bytes.
552 * @bytes: The raw context data given to HW.
553 *
554 * Represents either a Device or Input context. Holds a pointer to the raw
555 * memory used for the context (bytes) and dma address of it (dma).
556 */
557struct cdnsp_container_ctx {
558 unsigned int type;
559#define CDNSP_CTX_TYPE_DEVICE 0x1
560#define CDNSP_CTX_TYPE_INPUT 0x2
561 int size;
562 int ctx_size;
563 dma_addr_t dma;
564 u8 *bytes;
565};
566
567/**
568 * struct cdnsp_slot_ctx
569 * @dev_info: Device speed, and last valid endpoint.
570 * @dev_port: Device port number that is needed to access the USB device.
571 * @int_target: Interrupter target number.
572 * @dev_state: Slot state and device address.
573 *
574 * Slot Context - This assumes the controller uses 32-byte context
575 * structures. If the controller uses 64-byte contexts, there is an additional
576 * 32 bytes reserved at the end of the slot context for controller internal use.
577 */
578struct cdnsp_slot_ctx {
579 __le32 dev_info;
580 __le32 dev_port;
581 __le32 int_target;
582 __le32 dev_state;
583 /* offset 0x10 to 0x1f reserved for controller internal use. */
584 __le32 reserved[4];
585};
586
587/* Bits 20:23 in the Slot Context are the speed for the device. */
588#define SLOT_SPEED_FS (XDEV_FS << 10)
589#define SLOT_SPEED_HS (XDEV_HS << 10)
590#define SLOT_SPEED_SS (XDEV_SS << 10)
591#define SLOT_SPEED_SSP (XDEV_SSP << 10)
592
593/* dev_info bitmasks. */
594/* Device speed - values defined by PORTSC Device Speed field - 20:23. */
595#define DEV_SPEED GENMASK(23, 20)
596#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
597/* Index of the last valid endpoint context in this device context - 27:31. */
598#define LAST_CTX_MASK ((unsigned int)GENMASK(31, 27))
599#define LAST_CTX(p) ((p) << 27)
600#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
601#define SLOT_FLAG BIT(0)
602#define EP0_FLAG BIT(1)
603
604/* dev_port bitmasks */
605/* Device port number that is needed to access the USB device. */
606#define DEV_PORT(p) (((p) & 0xff) << 16)
607
608/* dev_state bitmasks */
609/* USB device address - assigned by the controller. */
610#define DEV_ADDR_MASK GENMASK(7, 0)
611/* Slot state */
612#define SLOT_STATE GENMASK(31, 27)
613#define GET_SLOT_STATE(p) (((p) & SLOT_STATE) >> 27)
614
615#define SLOT_STATE_DISABLED 0
616#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
617#define SLOT_STATE_DEFAULT 1
618#define SLOT_STATE_ADDRESSED 2
619#define SLOT_STATE_CONFIGURED 3
620
621/**
622 * struct cdnsp_ep_ctx.
623 * @ep_info: Endpoint state, streams, mult, and interval information.
624 * @ep_info2: Information on endpoint type, max packet size, max burst size,
625 * error count, and whether the controller will force an event for
626 * all transactions.
627 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
628 * defines one stream, this points to the endpoint transfer ring.
629 * Otherwise, it points to a stream context array, which has a
630 * ring pointer for each flow.
631 * @tx_info: Average TRB lengths for the endpoint ring and
632 * max payload within an Endpoint Service Interval Time (ESIT).
633 *
634 * Endpoint Context - This assumes the controller uses 32-byte context
635 * structures. If the controller uses 64-byte contexts, there is an additional
636 * 32 bytes reserved at the end of the endpoint context for controller internal
637 * use.
638 */
639struct cdnsp_ep_ctx {
640 __le32 ep_info;
641 __le32 ep_info2;
642 __le64 deq;
643 __le32 tx_info;
644 /* offset 0x14 - 0x1f reserved for controller internal use. */
645 __le32 reserved[3];
646};
647
648/* ep_info bitmasks. */
649/*
650 * Endpoint State - bits 0:2:
651 * 0 - disabled
652 * 1 - running
653 * 2 - halted due to halt condition
654 * 3 - stopped
655 * 4 - TRB error
656 * 5-7 - reserved
657 */
658#define EP_STATE_MASK GENMASK(3, 0)
659#define EP_STATE_DISABLED 0
660#define EP_STATE_RUNNING 1
661#define EP_STATE_HALTED 2
662#define EP_STATE_STOPPED 3
663#define EP_STATE_ERROR 4
664#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
665
666/* Mult - Max number of burst within an interval, in EP companion desc. */
667#define EP_MULT(p) (((p) << 8) & GENMASK(9, 8))
668#define CTX_TO_EP_MULT(p) (((p) & GENMASK(9, 8)) >> 8)
669/* bits 10:14 are Max Primary Streams. */
670/* bit 15 is Linear Stream Array. */
671/* Interval - period between requests to an endpoint - 125u increments. */
672#define EP_INTERVAL(p) (((p) << 16) & GENMASK(23, 16))
673#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) & GENMASK(23, 16)) >> 16))
674#define CTX_TO_EP_INTERVAL(p) (((p) & GENMASK(23, 16)) >> 16)
675#define EP_MAXPSTREAMS_MASK GENMASK(14, 10)
676#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
677#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
678/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
679#define EP_HAS_LSA BIT(15)
680
681/* ep_info2 bitmasks */
682#define ERROR_COUNT(p) (((p) & 0x3) << 1)
683#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
684#define EP_TYPE(p) ((p) << 3)
685#define ISOC_OUT_EP 1
686#define BULK_OUT_EP 2
687#define INT_OUT_EP 3
688#define CTRL_EP 4
689#define ISOC_IN_EP 5
690#define BULK_IN_EP 6
691#define INT_IN_EP 7
692/* bit 6 reserved. */
693/* bit 7 is Device Initiate Disable - for disabling stream selection. */
694#define MAX_BURST(p) (((p) << 8) & GENMASK(15, 8))
695#define CTX_TO_MAX_BURST(p) (((p) & GENMASK(15, 8)) >> 8)
696#define MAX_PACKET(p) (((p) << 16) & GENMASK(31, 16))
697#define MAX_PACKET_MASK GENMASK(31, 16)
698#define MAX_PACKET_DECODED(p) (((p) & GENMASK(31, 16)) >> 16)
699
700/* tx_info bitmasks. */
701#define EP_AVG_TRB_LENGTH(p) ((p) & GENMASK(15, 0))
702#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) << 16) & GENMASK(31, 16))
703#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) & GENMASK(23, 16)) >> 16) << 24)
704#define CTX_TO_MAX_ESIT_PAYLOAD_LO(p) (((p) & GENMASK(31, 16)) >> 16)
705#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) & GENMASK(31, 24)) >> 24)
706
707/* deq bitmasks. */
708#define EP_CTX_CYCLE_MASK BIT(0)
709#define CTX_DEQ_MASK (~0xfL)
710
711/**
712 * struct cdnsp_input_control_context
713 * Input control context;
714 *
715 * @drop_context: Set the bit of the endpoint context you want to disable.
716 * @add_context: Set the bit of the endpoint context you want to enable.
717 */
718struct cdnsp_input_control_ctx {
719 __le32 drop_flags;
720 __le32 add_flags;
721 __le32 rsvd2[6];
722};
723
724/**
725 * Represents everything that is needed to issue a command on the command ring.
726 *
727 * @in_ctx: Pointer to input context structure.
728 * @status: Command Completion Code for last command.
729 * @command_trb: Pointer to command TRB.
730 */
731struct cdnsp_command {
732 /* Input context for changing device state. */
733 struct cdnsp_container_ctx *in_ctx;
734 u32 status;
735 union cdnsp_trb *command_trb;
736};
737
738/**
739 * Stream context structure.
740 *
741 * @stream_ring: 64-bit stream ring address, cycle state, and stream type.
742 * @reserved: offset 0x14 - 0x1f reserved for controller internal use.
743 */
744struct cdnsp_stream_ctx {
745 __le64 stream_ring;
746 __le32 reserved[2];
747};
748
749/* Stream Context Types - bits 3:1 of stream ctx deq ptr. */
750#define SCT_FOR_CTX(p) (((p) << 1) & GENMASK(3, 1))
751/* Secondary stream array type, dequeue pointer is to a transfer ring. */
752#define SCT_SEC_TR 0
753/* Primary stream array type, dequeue pointer is to a transfer ring. */
754#define SCT_PRI_TR 1
755
756/**
757 * struct cdnsp_stream_info: Representing everything that is needed to
758 * supports stream capable endpoints.
759 * @stream_rings: Array of pointers containing Transfer rings for all
760 * supported streams.
761 * @num_streams: Number of streams, including stream 0.
762 * @stream_ctx_array: The stream context array may be bigger than the number
763 * of streams the driver asked for.
764 * @num_stream_ctxs: Number of streams.
765 * @ctx_array_dma: Dma address of Context Stream Array.
766 * @trb_address_map: For mapping physical TRB addresses to segments in
767 * stream rings.
768 * @td_count: Number of TDs associated with endpoint.
769 * @first_prime_det: First PRIME packet detected.
770 * @drbls_count: Number of allowed doorbells.
771 */
772struct cdnsp_stream_info {
773 struct cdnsp_ring **stream_rings;
774 unsigned int num_streams;
775 struct cdnsp_stream_ctx *stream_ctx_array;
776 unsigned int num_stream_ctxs;
777 dma_addr_t ctx_array_dma;
778 struct radix_tree_root trb_address_map;
779 int td_count;
780 u8 first_prime_det;
781#define STREAM_DRBL_FIFO_DEPTH 2
782 u8 drbls_count;
783};
784
785#define STREAM_LOG_STREAMS 4
786#define STREAM_NUM_STREAMS BIT(STREAM_LOG_STREAMS)
787
788#if STREAM_LOG_STREAMS > 16 && STREAM_LOG_STREAMS < 1
789#error "Not suupported stream value"
790#endif
791
792/**
793 * struct cdnsp_ep - extended device side representation of USB endpoint.
794 * @endpoint: usb endpoint
795 * @pending_req_list: List of requests queuing on transfer ring.
796 * @pdev: Device associated with this endpoint.
797 * @number: Endpoint number (1 - 15).
798 * idx: The device context index (DCI).
799 * interval: Interval between packets used for ISOC endpoint.
800 * @name: A human readable name e.g. ep1out.
801 * @direction: Endpoint direction.
802 * @buffering: Number of on-chip buffers related to endpoint.
803 * @buffering_period; Number of on-chip buffers related to periodic endpoint.
804 * @in_ctx: Pointer to input endpoint context structure.
805 * @out_ctx: Pointer to output endpoint context structure.
806 * @ring: Pointer to transfer ring.
807 * @stream_info: Hold stream information.
808 * @ep_state: Current state of endpoint.
809 * @skip: Sometimes the controller can not process isochronous endpoint ring
810 * quickly enough, and it will miss some isoc tds on the ring and
811 * generate Missed Service Error Event.
812 * Set skip flag when receive a Missed Service Error Event and
813 * process the missed tds on the endpoint ring.
814 * @wa1_nop_trb: hold pointer to NOP trb.
815 */
816struct cdnsp_ep {
817 struct usb_ep endpoint;
818 struct list_head pending_list;
819 struct cdnsp_device *pdev;
820 u8 number;
821 u8 idx;
822 u32 interval;
823 char name[20];
824 u8 direction;
825 u8 buffering;
826 u8 buffering_period;
827 struct cdnsp_ep_ctx *in_ctx;
828 struct cdnsp_ep_ctx *out_ctx;
829 struct cdnsp_ring *ring;
830 struct cdnsp_stream_info stream_info;
831 unsigned int ep_state;
832#define EP_ENABLED BIT(0)
833#define EP_DIS_IN_RROGRESS BIT(1)
834#define EP_HALTED BIT(2)
835#define EP_STOPPED BIT(3)
836#define EP_WEDGE BIT(4)
837#define EP0_HALTED_STATUS BIT(5)
838#define EP_HAS_STREAMS BIT(6)
839#define EP_UNCONFIGURED BIT(7)
840
841 bool skip;
842 union cdnsp_trb *wa1_nop_trb;
843
844};
845
846/**
847 * struct cdnsp_device_context_array
848 * @dev_context_ptr: Array of 64-bit DMA addresses for device contexts.
849 * @dma: DMA address for device contexts structure.
850 */
851struct cdnsp_device_context_array {
852 __le64 dev_context_ptrs[CDNSP_DEV_MAX_SLOTS + 1];
853 dma_addr_t dma;
854};
855
856/**
857 * struct cdnsp_transfer_event.
858 * @buffer: 64-bit buffer address, or immediate data.
859 * @transfer_len: Data length transferred.
860 * @flags: Field is interpreted differently based on the type of TRB.
861 */
862struct cdnsp_transfer_event {
863 __le64 buffer;
864 __le32 transfer_len;
865 __le32 flags;
866};
867
868/* Invalidate event after disabling endpoint. */
869#define TRB_EVENT_INVALIDATE 8
870
871/* Transfer event TRB length bit mask. */
872/* bits 0:23 */
873#define EVENT_TRB_LEN(p) ((p) & GENMASK(23, 0))
874/* Completion Code - only applicable for some types of TRBs */
875#define COMP_CODE_MASK (0xff << 24)
876#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
877#define COMP_INVALID 0
878#define COMP_SUCCESS 1
879#define COMP_DATA_BUFFER_ERROR 2
880#define COMP_BABBLE_DETECTED_ERROR 3
881#define COMP_TRB_ERROR 5
882#define COMP_RESOURCE_ERROR 7
883#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
884#define COMP_INVALID_STREAM_TYPE_ERROR 10
885#define COMP_SLOT_NOT_ENABLED_ERROR 11
886#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
887#define COMP_SHORT_PACKET 13
888#define COMP_RING_UNDERRUN 14
889#define COMP_RING_OVERRUN 15
890#define COMP_VF_EVENT_RING_FULL_ERROR 16
891#define COMP_PARAMETER_ERROR 17
892#define COMP_CONTEXT_STATE_ERROR 19
893#define COMP_EVENT_RING_FULL_ERROR 21
894#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
895#define COMP_MISSED_SERVICE_ERROR 23
896#define COMP_COMMAND_RING_STOPPED 24
897#define COMP_COMMAND_ABORTED 25
898#define COMP_STOPPED 26
899#define COMP_STOPPED_LENGTH_INVALID 27
900#define COMP_STOPPED_SHORT_PACKET 28
901#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
902#define COMP_ISOCH_BUFFER_OVERRUN 31
903#define COMP_EVENT_LOST_ERROR 32
904#define COMP_UNDEFINED_ERROR 33
905#define COMP_INVALID_STREAM_ID_ERROR 34
906
907/*Transfer Event NRDY bit fields */
908#define TRB_TO_DEV_STREAM(p) ((p) & GENMASK(16, 0))
909#define TRB_TO_HOST_STREAM(p) ((p) & GENMASK(16, 0))
910#define STREAM_PRIME_ACK 0xFFFE
911#define STREAM_REJECTED 0xFFFF
912
913/** Transfer Event bit fields **/
914#define TRB_TO_EP_ID(p) (((p) & GENMASK(20, 16)) >> 16)
915
916/**
917 * struct cdnsp_link_trb
918 * @segment_ptr: 64-bit segment pointer.
919 * @intr_target: Interrupter target.
920 * @control: Flags.
921 */
922struct cdnsp_link_trb {
923 __le64 segment_ptr;
924 __le32 intr_target;
925 __le32 control;
926};
927
928/* control bitfields */
929#define LINK_TOGGLE BIT(1)
930
931/**
932 * struct cdnsp_event_cmd - Command completion event TRB.
933 * cmd_trb: Pointer to command TRB, or the value passed by the event data trb
934 * status: Command completion parameters and error code.
935 * flags: Flags.
936 */
937struct cdnsp_event_cmd {
938 __le64 cmd_trb;
939 __le32 status;
940 __le32 flags;
941};
942
943/* flags bitmasks */
944
945/* Address device - disable SetAddress. */
946#define TRB_BSR BIT(9)
947
948/* Configure Endpoint - Deconfigure. */
949#define TRB_DC BIT(9)
950
951/* Force Header */
952#define TRB_FH_TO_PACKET_TYPE(p) ((p) & GENMASK(4, 0))
953#define TRB_FH_TR_PACKET 0x4
954#define TRB_FH_TO_DEVICE_ADDRESS(p) (((p) << 25) & GENMASK(31, 25))
955#define TRB_FH_TR_PACKET_DEV_NOT 0x6
956#define TRB_FH_TO_NOT_TYPE(p) (((p) << 4) & GENMASK(7, 4))
957#define TRB_FH_TR_PACKET_FUNCTION_WAKE 0x1
958#define TRB_FH_TO_INTERFACE(p) (((p) << 8) & GENMASK(15, 8))
959
960enum cdnsp_setup_dev {
961 SETUP_CONTEXT_ONLY,
962 SETUP_CONTEXT_ADDRESS,
963};
964
965/* bits 24:31 are the slot ID. */
966#define TRB_TO_SLOT_ID(p) (((p) & GENMASK(31, 24)) >> 24)
967#define SLOT_ID_FOR_TRB(p) (((p) << 24) & GENMASK(31, 24))
968
969/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB. */
970#define TRB_TO_EP_INDEX(p) (((p) >> 16) & 0x1f)
971
972#define EP_ID_FOR_TRB(p) ((((p) + 1) << 16) & GENMASK(20, 16))
973
974#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
975#define TRB_TO_SUSPEND_PORT(p) (((p) >> 23) & 0x1)
976#define LAST_EP_INDEX 30
977
978/* Set TR Dequeue Pointer command TRB fields. */
979#define TRB_TO_STREAM_ID(p) ((((p) & GENMASK(31, 16)) >> 16))
980#define STREAM_ID_FOR_TRB(p) ((((p)) << 16) & GENMASK(31, 16))
981#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
982
983/* Link TRB specific fields. */
984#define TRB_TC BIT(1)
985
986/* Port Status Change Event TRB fields. */
987/* Port ID - bits 31:24. */
988#define GET_PORT_ID(p) (((p) & GENMASK(31, 24)) >> 24)
989#define SET_PORT_ID(p) (((p) << 24) & GENMASK(31, 24))
990#define EVENT_DATA BIT(2)
991
992/* Normal TRB fields. */
993/* transfer_len bitmasks - bits 0:16. */
994#define TRB_LEN(p) ((p) & GENMASK(16, 0))
995/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31). */
996#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
997#define GET_TD_SIZE(p) (((p) & GENMASK(21, 17)) >> 17)
998/*
999 * Controller uses the TD_SIZE field for TBC if Extended TBC
1000 * is enabled (ETE).
1001 */
1002#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1003/* Interrupter Target - which MSI-X vector to target the completion event at. */
1004#define TRB_INTR_TARGET(p) (((p) << 22) & GENMASK(31, 22))
1005#define GET_INTR_TARGET(p) (((p) & GENMASK(31, 22)) >> 22)
1006/*
1007 * Total burst count field, Rsvdz on controller with Extended TBC
1008 * enabled (ETE).
1009 */
1010#define TRB_TBC(p) (((p) & 0x3) << 7)
1011#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1012
1013/* Cycle bit - indicates TRB ownership by driver or driver.*/
1014#define TRB_CYCLE BIT(0)
1015/*
1016 * Force next event data TRB to be evaluated before task switch.
1017 * Used to pass OS data back after a TD completes.
1018 */
1019#define TRB_ENT BIT(1)
1020/* Interrupt on short packet. */
1021#define TRB_ISP BIT(2)
1022/* Set PCIe no snoop attribute. */
1023#define TRB_NO_SNOOP BIT(3)
1024/* Chain multiple TRBs into a TD. */
1025#define TRB_CHAIN BIT(4)
1026/* Interrupt on completion. */
1027#define TRB_IOC BIT(5)
1028/* The buffer pointer contains immediate data. */
1029#define TRB_IDT BIT(6)
1030/* 0 - NRDY during data stage, 1 - NRDY during status stage (only control). */
1031#define TRB_STAT BIT(7)
1032/* Block Event Interrupt. */
1033#define TRB_BEI BIT(9)
1034
1035/* Control transfer TRB specific fields. */
1036#define TRB_DIR_IN BIT(16)
1037
1038/* TRB bit mask in Data Stage TRB */
1039#define TRB_SETUPID_BITMASK GENMASK(9, 8)
1040#define TRB_SETUPID(p) ((p) << 8)
1041#define TRB_SETUPID_TO_TYPE(p) (((p) & TRB_SETUPID_BITMASK) >> 8)
1042
1043#define TRB_SETUP_SPEEDID_USB3 0x1
1044#define TRB_SETUP_SPEEDID_USB2 0x0
1045#define TRB_SETUP_SPEEDID(p) ((p) & (1 << 7))
1046
1047#define TRB_SETUPSTAT_ACK 0x1
1048#define TRB_SETUPSTAT_STALL 0x0
1049#define TRB_SETUPSTAT(p) ((p) << 6)
1050
1051/* Isochronous TRB specific fields */
1052#define TRB_SIA BIT(31)
1053#define TRB_FRAME_ID(p) (((p) << 20) & GENMASK(30, 20))
1054
1055struct cdnsp_generic_trb {
1056 __le32 field[4];
1057};
1058
1059union cdnsp_trb {
1060 struct cdnsp_link_trb link;
1061 struct cdnsp_transfer_event trans_event;
1062 struct cdnsp_event_cmd event_cmd;
1063 struct cdnsp_generic_trb generic;
1064};
1065
1066/* TRB bit mask. */
1067#define TRB_TYPE_BITMASK GENMASK(15, 10)
1068#define TRB_TYPE(p) ((p) << 10)
1069#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1070
1071/* TRB type IDs. */
1072/* bulk, interrupt, isoc scatter/gather, and control data stage. */
1073#define TRB_NORMAL 1
1074/* Setup Stage for control transfers. */
1075#define TRB_SETUP 2
1076/* Data Stage for control transfers. */
1077#define TRB_DATA 3
1078/* Status Stage for control transfers. */
1079#define TRB_STATUS 4
1080/* ISOC transfers. */
1081#define TRB_ISOC 5
1082/* TRB for linking ring segments. */
1083#define TRB_LINK 6
1084#define TRB_EVENT_DATA 7
1085/* Transfer Ring No-op (not for the command ring). */
1086#define TRB_TR_NOOP 8
1087
1088/* Command TRBs */
1089/* Enable Slot Command. */
1090#define TRB_ENABLE_SLOT 9
1091/* Disable Slot Command. */
1092#define TRB_DISABLE_SLOT 10
1093/* Address Device Command. */
1094#define TRB_ADDR_DEV 11
1095/* Configure Endpoint Command. */
1096#define TRB_CONFIG_EP 12
1097/* Evaluate Context Command. */
1098#define TRB_EVAL_CONTEXT 13
1099/* Reset Endpoint Command. */
1100#define TRB_RESET_EP 14
1101/* Stop Transfer Ring Command. */
1102#define TRB_STOP_RING 15
1103/* Set Transfer Ring Dequeue Pointer Command. */
1104#define TRB_SET_DEQ 16
1105/* Reset Device Command. */
1106#define TRB_RESET_DEV 17
1107/* Force Event Command (opt). */
1108#define TRB_FORCE_EVENT 18
1109/* Force Header Command - generate a transaction or link management packet. */
1110#define TRB_FORCE_HEADER 22
1111/* No-op Command - not for transfer rings. */
1112#define TRB_CMD_NOOP 23
1113/* TRB IDs 24-31 reserved. */
1114
1115/* Event TRBS. */
1116/* Transfer Event. */
1117#define TRB_TRANSFER 32
1118/* Command Completion Event. */
1119#define TRB_COMPLETION 33
1120/* Port Status Change Event. */
1121#define TRB_PORT_STATUS 34
1122/* Device Controller Event. */
1123#define TRB_HC_EVENT 37
1124/* MFINDEX Wrap Event - microframe counter wrapped. */
1125#define TRB_MFINDEX_WRAP 39
1126/* TRB IDs 40-47 reserved. */
1127/* Endpoint Not Ready Event. */
1128#define TRB_ENDPOINT_NRDY 48
1129/* TRB IDs 49-53 reserved. */
1130/* Halt Endpoint Command. */
1131#define TRB_HALT_ENDPOINT 54
1132/* Doorbell Overflow Event. */
1133#define TRB_DRB_OVERFLOW 57
1134
1135#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1136#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1137 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1138#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1139 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1140
1141/*
1142 * TRBS_PER_SEGMENT must be a multiple of 4.
1143 * The command ring is 64-byte aligned, so it must also be greater than 16.
1144 */
1145#define TRBS_PER_SEGMENT 256
1146#define TRBS_PER_EVENT_SEGMENT 256
1147#define TRBS_PER_EV_DEQ_UPDATE 100
1148#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT * 16)
1149#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1150/* TRB buffer pointers can't cross 64KB boundaries. */
1151#define TRB_MAX_BUFF_SHIFT 16
1152#define TRB_MAX_BUFF_SIZE BIT(TRB_MAX_BUFF_SHIFT)
1153/* How much data is left before the 64KB boundary? */
1154#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1155 ((addr) & (TRB_MAX_BUFF_SIZE - 1)))
1156
1157/**
1158 * struct cdnsp_segment - segment related data.
1159 * @trbs: Array of Transfer Request Blocks.
1160 * @next: Pointer to the next segment.
1161 * @dma: DMA address of current segment.
1162 * @bounce_dma: Bounce buffer DMA address .
1163 * @bounce_buf: Bounce buffer virtual address.
1164 * bounce_offs: Bounce buffer offset.
1165 * bounce_len: Bounce buffer length.
1166 */
1167struct cdnsp_segment {
1168 union cdnsp_trb *trbs;
1169 struct cdnsp_segment *next;
1170 dma_addr_t dma;
1171 /* Max packet sized bounce buffer for td-fragmant alignment */
1172 dma_addr_t bounce_dma;
1173 void *bounce_buf;
1174 unsigned int bounce_offs;
1175 unsigned int bounce_len;
1176};
1177
1178/**
1179 * struct cdnsp_td - Transfer Descriptor object.
1180 * @td_list: Used for binding TD with ep_ring->td_list.
1181 * @preq: Request associated with this TD
1182 * @start_seg: Segment containing the first_trb in TD.
1183 * @first_trb: First TRB for this TD.
1184 * @last_trb: Last TRB related with TD.
1185 * @bounce_seg: Bounce segment for this TD.
1186 * @request_length_set: actual_length of the request has already been set.
1187 * @drbl - TD has been added to HW scheduler - only for stream capable
1188 * endpoints.
1189 */
1190struct cdnsp_td {
1191 struct list_head td_list;
1192 struct cdnsp_request *preq;
1193 struct cdnsp_segment *start_seg;
1194 union cdnsp_trb *first_trb;
1195 union cdnsp_trb *last_trb;
1196 struct cdnsp_segment *bounce_seg;
1197 bool request_length_set;
1198 bool drbl;
1199};
1200
1201/**
1202 * struct cdnsp_dequeue_state - New dequeue pointer for Transfer Ring.
1203 * @new_deq_seg: New dequeue segment.
1204 * @new_deq_ptr: New dequeue pointer.
1205 * @new_cycle_state: New cycle state.
1206 * @stream_id: stream id for which new dequeue pointer has been selected.
1207 */
1208struct cdnsp_dequeue_state {
1209 struct cdnsp_segment *new_deq_seg;
1210 union cdnsp_trb *new_deq_ptr;
1211 int new_cycle_state;
1212 unsigned int stream_id;
1213};
1214
1215enum cdnsp_ring_type {
1216 TYPE_CTRL = 0,
1217 TYPE_ISOC,
1218 TYPE_BULK,
1219 TYPE_INTR,
1220 TYPE_STREAM,
1221 TYPE_COMMAND,
1222 TYPE_EVENT,
1223};
1224
1225/**
1226 * struct cdnsp_ring - information describing transfer, command or event ring.
1227 * @first_seg: First segment on transfer ring.
1228 * @last_seg: Last segment on transfer ring.
1229 * @enqueue: SW enqueue pointer address.
1230 * @enq_seg: SW enqueue segment address.
1231 * @dequeue: SW dequeue pointer address.
1232 * @deq_seg: SW dequeue segment address.
1233 * @td_list: transfer descriptor list associated with this ring.
1234 * @cycle_state: Current cycle bit. Write the cycle state into the TRB cycle
1235 * field to give ownership of the TRB to the device controller
1236 * (if we are the producer) or to check if we own the TRB
1237 * (if we are the consumer).
1238 * @stream_id: Stream id
1239 * @stream_active: Stream is active - PRIME packet has been detected.
1240 * @stream_rejected: This ring has been rejected by host.
1241 * @num_tds: Number of TDs associated with ring.
1242 * @num_segs: Number of segments.
1243 * @num_trbs_free: Number of free TRBs on the ring.
1244 * @bounce_buf_len: Length of bounce buffer.
1245 * @type: Ring type - event, transfer, or command ring.
1246 * @last_td_was_short - TD is short TD.
1247 * @trb_address_map: For mapping physical TRB addresses to segments in
1248 * stream rings.
1249 */
1250struct cdnsp_ring {
1251 struct cdnsp_segment *first_seg;
1252 struct cdnsp_segment *last_seg;
1253 union cdnsp_trb *enqueue;
1254 struct cdnsp_segment *enq_seg;
1255 union cdnsp_trb *dequeue;
1256 struct cdnsp_segment *deq_seg;
1257 struct list_head td_list;
1258 u32 cycle_state;
1259 unsigned int stream_id;
1260 unsigned int stream_active;
1261 unsigned int stream_rejected;
1262 int num_tds;
1263 unsigned int num_segs;
1264 unsigned int num_trbs_free;
1265 unsigned int bounce_buf_len;
1266 enum cdnsp_ring_type type;
1267 bool last_td_was_short;
1268 struct radix_tree_root *trb_address_map;
1269};
1270
1271/**
1272 * struct cdnsp_erst_entry - even ring segment table entry object.
1273 * @seg_addr: 64-bit event ring segment address.
1274 * seg_size: Number of TRBs in segment.;
1275 */
1276struct cdnsp_erst_entry {
1277 __le64 seg_addr;
1278 __le32 seg_size;
1279 /* Set to zero */
1280 __le32 rsvd;
1281};
1282
1283/**
1284 * struct cdnsp_erst - even ring segment table for event ring.
1285 * @entries: Array of event ring segments
1286 * @num_entries: Number of segments in entries array.
1287 * @erst_dma_addr: DMA address for entries array.
1288 */
1289struct cdnsp_erst {
1290 struct cdnsp_erst_entry *entries;
1291 unsigned int num_entries;
1292 dma_addr_t erst_dma_addr;
1293};
1294
1295/**
1296 * struct cdnsp_request - extended device side representation of usb_request
1297 * object .
1298 * @td: Transfer descriptor associated with this request.
1299 * @request: Generic usb_request object describing single I/O request.
1300 * @list: Used to adding request to endpoint pending_list.
1301 * @pep: Extended representation of usb_ep object
1302 * @epnum: Endpoint number associated with usb request.
1303 * @direction: Endpoint direction for usb request.
1304 */
1305struct cdnsp_request {
1306 struct cdnsp_td td;
1307 struct usb_request request;
1308 struct list_head list;
1309 struct cdnsp_ep *pep;
1310 u8 epnum;
1311 unsigned direction:1;
1312};
1313
1314#define ERST_NUM_SEGS 1
1315
1316/* Stages used during enumeration process.*/
1317enum cdnsp_ep0_stage {
1318 CDNSP_SETUP_STAGE,
1319 CDNSP_DATA_STAGE,
1320 CDNSP_STATUS_STAGE,
1321};
1322
1323/**
1324 * struct cdnsp_port - holds information about detected ports.
1325 * @port_num: Port number.
1326 * @exist: Indicate if port exist.
1327 * maj_rev: Major revision.
1328 * min_rev: Minor revision.
1329 */
1330struct cdnsp_port {
1331 struct cdnsp_port_regs __iomem *regs;
1332 u8 port_num;
1333 u8 exist;
1334 u8 maj_rev;
1335 u8 min_rev;
1336};
1337
1338#define CDNSP_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
1339#define CDNSP_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
1340#define CDNSP_EXT_PORT_OFF(x) ((x) & 0xff)
1341#define CDNSP_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
1342
1343/**
1344 * struct cdnsp_device - represent USB device.
1345 * @dev: Pointer to device structure associated whit this controller.
1346 * @gadget: Device side representation of the peripheral controller.
1347 * @gadget_driver: Pointer to the gadget driver.
1348 * @irq: IRQ line number used by device side.
1349 * @regs:IO device memory.
1350 * @cap_regs: Capability registers.
1351 * @op_regs: Operational registers.
1352 * @run_regs: Runtime registers.
1353 * @dba: Device base address register.
1354 * @ir_set: Current interrupter register set.
1355 * @port20_regs: Port 2.0 Peripheral Configuration Registers.
1356 * @port3x_regs: USB3.x Port Peripheral Configuration Registers.
1357 * @rev_cap: Controller Capabilities Registers.
1358 * @hcs_params1: Cached register copies of read-only HCSPARAMS1
1359 * @hcc_params: Cached register copies of read-only HCCPARAMS1
1360 * @setup: Temporary buffer for setup packet.
1361 * @ep0_preq: Internal allocated request used during enumeration.
1362 * @ep0_stage: ep0 stage during enumeration process.
1363 * @three_stage_setup: Three state or two state setup.
1364 * @ep0_expect_in: Data IN expected for control transfer.
1365 * @setup_id: Setup identifier.
1366 * @setup_speed - Speed detected for current SETUP packet.
1367 * @setup_buf: Buffer for SETUP packet.
1368 * @device_address: Current device address.
1369 * @may_wakeup: remote wakeup enabled/disabled.
1370 * @lock: Lock used in interrupt thread context.
1371 * @hci_version: device controller version.
1372 * @dcbaa: Device context base address array.
1373 * @cmd_ring: Command ring.
1374 * @cmd: Represent all what is needed to issue command on Command Ring.
1375 * @event_ring: Event ring.
1376 * @erst: Event Ring Segment table
1377 * @slot_id: Current Slot ID. Should be 0 or 1.
1378 * @out_ctx: Output context.
1379 * @in_ctx: Input context.
1380 * @eps: array of endpoints object associated with device.
1381 * @usb2_hw_lpm_capable: hardware lpm is enabled;
1382 * @u1_allowed: Allow device transition to U1 state.
1383 * @u2_allowed: Allow device transition to U2 state
1384 * @device_pool: DMA pool for allocating input and output context.
1385 * @segment_pool: DMA pool for allocating new segments.
1386 * @cdnsp_state: Current state of controller.
1387 * @link_state: Current link state.
1388 * @usb2_port - Port USB 2.0.
1389 * @usb3_port - Port USB 3.0.
1390 * @active_port - Current selected Port.
1391 * @test_mode: selected Test Mode.
1392 */
1393struct cdnsp_device {
1394 struct device *dev;
1395 struct usb_gadget gadget;
1396 struct usb_gadget_driver *gadget_driver;
1397 unsigned int irq;
1398 void __iomem *regs;
1399
1400 /* Registers map */
1401 struct cdnsp_cap_regs __iomem *cap_regs;
1402 struct cdnsp_op_regs __iomem *op_regs;
1403 struct cdnsp_run_regs __iomem *run_regs;
1404 struct cdnsp_doorbell_array __iomem *dba;
1405 struct cdnsp_intr_reg __iomem *ir_set;
1406 struct cdnsp_20port_cap __iomem *port20_regs;
1407 struct cdnsp_3xport_cap __iomem *port3x_regs;
1408 struct cdnsp_rev_cap __iomem *rev_cap;
1409
1410 /* Cached register copies of read-only CDNSP data */
1411 __u32 hcs_params1;
1412 __u32 hcs_params3;
1413 __u32 hcc_params;
1414 /* Lock used in interrupt thread context. */
1415 spinlock_t lock;
1416 struct usb_ctrlrequest setup;
1417 struct cdnsp_request ep0_preq;
1418 enum cdnsp_ep0_stage ep0_stage;
1419 u8 three_stage_setup;
1420 u8 ep0_expect_in;
1421 u8 setup_id;
1422 u8 setup_speed;
1423 void *setup_buf;
1424 u8 device_address;
1425 int may_wakeup;
1426 u16 hci_version;
1427
1428 /* data structures */
1429 struct cdnsp_device_context_array *dcbaa;
1430 struct cdnsp_ring *cmd_ring;
1431 struct cdnsp_command cmd;
1432 struct cdnsp_ring *event_ring;
1433 struct cdnsp_erst erst;
1434 int slot_id;
1435
1436 /*
1437 * Commands to the hardware are passed an "input context" that
1438 * tells the hardware what to change in its data structures.
1439 * The hardware will return changes in an "output context" that
1440 * software must allocate for the hardware. .
1441 */
1442 struct cdnsp_container_ctx out_ctx;
1443 struct cdnsp_container_ctx in_ctx;
1444 struct cdnsp_ep eps[CDNSP_ENDPOINTS_NUM];
1445 u8 usb2_hw_lpm_capable:1;
1446 u8 u1_allowed:1;
1447 u8 u2_allowed:1;
1448
1449 /* DMA pools */
1450 struct dma_pool *device_pool;
1451 struct dma_pool *segment_pool;
1452
1453#define CDNSP_STATE_HALTED BIT(1)
1454#define CDNSP_STATE_DYING BIT(2)
1455#define CDNSP_STATE_DISCONNECT_PENDING BIT(3)
1456#define CDNSP_WAKEUP_PENDING BIT(4)
1457 unsigned int cdnsp_state;
1458 unsigned int link_state;
1459
1460 struct cdnsp_port usb2_port;
1461 struct cdnsp_port usb3_port;
1462 struct cdnsp_port *active_port;
1463 u16 test_mode;
1464};
1465
1466/*
1467 * Registers should always be accessed with double word or quad word accesses.
1468 *
1469 * Registers with 64-bit address pointers should be written to with
1470 * dword accesses by writing the low dword first (ptr[0]), then the high dword
1471 * (ptr[1]) second. controller implementations that do not support 64-bit
1472 * address pointers will ignore the high dword, and write order is irrelevant.
1473 */
1474static inline u64 cdnsp_read_64(__le64 __iomem *regs)
1475{
1476 return lo_hi_readq(regs);
1477}
1478
1479static inline void cdnsp_write_64(const u64 val, __le64 __iomem *regs)
1480{
1481 lo_hi_writeq(val, regs);
1482}
1483
1484/* CDNSP memory management functions. */
1485void cdnsp_mem_cleanup(struct cdnsp_device *pdev);
1486int cdnsp_mem_init(struct cdnsp_device *pdev);
1487int cdnsp_setup_addressable_priv_dev(struct cdnsp_device *pdev);
1488void cdnsp_copy_ep0_dequeue_into_input_ctx(struct cdnsp_device *pdev);
1489void cdnsp_endpoint_zero(struct cdnsp_device *pdev, struct cdnsp_ep *ep);
1490int cdnsp_endpoint_init(struct cdnsp_device *pdev,
1491 struct cdnsp_ep *pep,
1492 gfp_t mem_flags);
1493int cdnsp_ring_expansion(struct cdnsp_device *pdev,
1494 struct cdnsp_ring *ring,
1495 unsigned int num_trbs, gfp_t flags);
1496struct cdnsp_ring *cdnsp_dma_to_transfer_ring(struct cdnsp_ep *ep, u64 address);
1497int cdnsp_alloc_stream_info(struct cdnsp_device *pdev,
1498 struct cdnsp_ep *pep,
1499 unsigned int num_stream_ctxs,
1500 unsigned int num_streams);
1501int cdnsp_alloc_streams(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1502void cdnsp_free_endpoint_rings(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1503
1504/* Device controller glue. */
1505int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id);
1506int cdnsp_halt(struct cdnsp_device *pdev);
1507void cdnsp_died(struct cdnsp_device *pdev);
1508int cdnsp_reset(struct cdnsp_device *pdev);
1509irqreturn_t cdnsp_irq_handler(int irq, void *priv);
1510int cdnsp_setup_device(struct cdnsp_device *pdev, enum cdnsp_setup_dev setup);
1511void cdnsp_set_usb2_hardware_lpm(struct cdnsp_device *usbsssp_data,
1512 struct usb_request *req, int enable);
1513irqreturn_t cdnsp_thread_irq_handler(int irq, void *data);
1514
1515/* Ring, segment, TRB, and TD functions. */
1516dma_addr_t cdnsp_trb_virt_to_dma(struct cdnsp_segment *seg,
1517 union cdnsp_trb *trb);
1518bool cdnsp_last_trb_on_seg(struct cdnsp_segment *seg, union cdnsp_trb *trb);
1519bool cdnsp_last_trb_on_ring(struct cdnsp_ring *ring,
1520 struct cdnsp_segment *seg,
1521 union cdnsp_trb *trb);
1522int cdnsp_wait_for_cmd_compl(struct cdnsp_device *pdev);
1523void cdnsp_update_erst_dequeue(struct cdnsp_device *pdev,
1524 union cdnsp_trb *event_ring_deq,
1525 u8 clear_ehb);
1526void cdnsp_initialize_ring_info(struct cdnsp_ring *ring);
1527void cdnsp_ring_cmd_db(struct cdnsp_device *pdev);
1528void cdnsp_queue_slot_control(struct cdnsp_device *pdev, u32 trb_type);
1529void cdnsp_queue_address_device(struct cdnsp_device *pdev,
1530 dma_addr_t in_ctx_ptr,
1531 enum cdnsp_setup_dev setup);
1532void cdnsp_queue_stop_endpoint(struct cdnsp_device *pdev,
1533 unsigned int ep_index);
1534int cdnsp_queue_ctrl_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq);
1535int cdnsp_queue_bulk_tx(struct cdnsp_device *pdev, struct cdnsp_request *preq);
1536int cdnsp_queue_isoc_tx(struct cdnsp_device *pdev,
1537 struct cdnsp_request *preq);
1538void cdnsp_queue_configure_endpoint(struct cdnsp_device *pdev,
1539 dma_addr_t in_ctx_ptr);
1540void cdnsp_queue_reset_ep(struct cdnsp_device *pdev, unsigned int ep_index);
1541void cdnsp_queue_halt_endpoint(struct cdnsp_device *pdev,
1542 unsigned int ep_index);
1543void cdnsp_force_header_wakeup(struct cdnsp_device *pdev, int intf_num);
1544void cdnsp_queue_reset_device(struct cdnsp_device *pdev);
1545void cdnsp_queue_new_dequeue_state(struct cdnsp_device *pdev,
1546 struct cdnsp_ep *pep,
1547 struct cdnsp_dequeue_state *deq_state);
1548void cdnsp_ring_doorbell_for_active_rings(struct cdnsp_device *pdev,
1549 struct cdnsp_ep *pep);
1550void cdnsp_inc_deq(struct cdnsp_device *pdev, struct cdnsp_ring *ring);
1551void cdnsp_set_link_state(struct cdnsp_device *pdev,
1552 __le32 __iomem *port_regs, u32 link_state);
1553u32 cdnsp_port_state_to_neutral(u32 state);
1554
1555/* CDNSP device controller contexts. */
1556int cdnsp_enable_slot(struct cdnsp_device *pdev);
1557int cdnsp_disable_slot(struct cdnsp_device *pdev);
1558struct cdnsp_input_control_ctx
1559 *cdnsp_get_input_control_ctx(struct cdnsp_container_ctx *ctx);
1560struct cdnsp_slot_ctx *cdnsp_get_slot_ctx(struct cdnsp_container_ctx *ctx);
1561struct cdnsp_ep_ctx *cdnsp_get_ep_ctx(struct cdnsp_container_ctx *ctx,
1562 unsigned int ep_index);
1563/* CDNSP gadget interface. */
1564void cdnsp_suspend_gadget(struct cdnsp_device *pdev);
1565void cdnsp_resume_gadget(struct cdnsp_device *pdev);
1566void cdnsp_disconnect_gadget(struct cdnsp_device *pdev);
1567void cdnsp_gadget_giveback(struct cdnsp_ep *pep, struct cdnsp_request *preq,
1568 int status);
1569int cdnsp_ep_enqueue(struct cdnsp_ep *pep, struct cdnsp_request *preq);
1570int cdnsp_ep_dequeue(struct cdnsp_ep *pep, struct cdnsp_request *preq);
1571unsigned int cdnsp_port_speed(unsigned int port_status);
1572void cdnsp_irq_reset(struct cdnsp_device *pdev);
1573int cdnsp_halt_endpoint(struct cdnsp_device *pdev,
1574 struct cdnsp_ep *pep, int value);
1575int cdnsp_cmd_stop_ep(struct cdnsp_device *pdev, struct cdnsp_ep *pep);
1576void cdnsp_setup_analyze(struct cdnsp_device *pdev);
1577int cdnsp_status_stage(struct cdnsp_device *pdev);
1578int cdnsp_reset_device(struct cdnsp_device *pdev);
1579
1580/**
1581 * next_request - gets the next request on the given list
1582 * @list: the request list to operate on
1583 *
1584 * Caller should take care of locking. This function return NULL or the first
1585 * request available on list.
1586 */
1587static inline struct cdnsp_request *next_request(struct list_head *list)
1588{
1589 return list_first_entry_or_null(list, struct cdnsp_request, list);
1590}
1591
1592#define to_cdnsp_ep(ep) (container_of(ep, struct cdnsp_ep, endpoint))
1593#define gadget_to_cdnsp(g) (container_of(g, struct cdnsp_device, gadget))
1594#define request_to_cdnsp_request(r) (container_of(r, struct cdnsp_request, \
1595 request))
1596#define to_cdnsp_request(r) (container_of(r, struct cdnsp_request, request))
1597int cdnsp_remove_request(struct cdnsp_device *pdev, struct cdnsp_request *preq,
1598 struct cdnsp_ep *pep);
1599
1600#endif /* __LINUX_CDNSP_GADGET_H */