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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Cirrus Logic EP93xx SPI controller.
4 *
5 * Copyright (C) 2010-2011 Mika Westerberg
6 *
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
8 *
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
10 *
11 * For more information about the SPI controller see documentation on Cirrus
12 * Logic web site:
13 * https://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
14 */
15
16#include <linux/io.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dma-direction.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/bitops.h>
25#include <linux/interrupt.h>
26#include <linux/module.h>
27#include <linux/property.h>
28#include <linux/platform_device.h>
29#include <linux/sched.h>
30#include <linux/scatterlist.h>
31#include <linux/spi/spi.h>
32
33#define SSPCR0 0x0000
34#define SSPCR0_SPO BIT(6)
35#define SSPCR0_SPH BIT(7)
36#define SSPCR0_SCR_SHIFT 8
37
38#define SSPCR1 0x0004
39#define SSPCR1_RIE BIT(0)
40#define SSPCR1_TIE BIT(1)
41#define SSPCR1_RORIE BIT(2)
42#define SSPCR1_LBM BIT(3)
43#define SSPCR1_SSE BIT(4)
44#define SSPCR1_MS BIT(5)
45#define SSPCR1_SOD BIT(6)
46
47#define SSPDR 0x0008
48
49#define SSPSR 0x000c
50#define SSPSR_TFE BIT(0)
51#define SSPSR_TNF BIT(1)
52#define SSPSR_RNE BIT(2)
53#define SSPSR_RFF BIT(3)
54#define SSPSR_BSY BIT(4)
55#define SSPCPSR 0x0010
56
57#define SSPIIR 0x0014
58#define SSPIIR_RIS BIT(0)
59#define SSPIIR_TIS BIT(1)
60#define SSPIIR_RORIS BIT(2)
61#define SSPICR SSPIIR
62
63/* timeout in milliseconds */
64#define SPI_TIMEOUT 5
65/* maximum depth of RX/TX FIFO */
66#define SPI_FIFO_SIZE 8
67
68/**
69 * struct ep93xx_spi - EP93xx SPI controller structure
70 * @clk: clock for the controller
71 * @mmio: pointer to ioremap()'d registers
72 * @sspdr_phys: physical address of the SSPDR register
73 * @tx: current byte in transfer to transmit
74 * @rx: current byte in transfer to receive
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
76 * frame decreases this level and sending one frame increases it.
77 * @dma_rx: RX DMA channel
78 * @dma_tx: TX DMA channel
79 * @rx_sgt: sg table for RX transfers
80 * @tx_sgt: sg table for TX transfers
81 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
82 * the client
83 */
84struct ep93xx_spi {
85 struct clk *clk;
86 void __iomem *mmio;
87 unsigned long sspdr_phys;
88 size_t tx;
89 size_t rx;
90 size_t fifo_level;
91 struct dma_chan *dma_rx;
92 struct dma_chan *dma_tx;
93 struct sg_table rx_sgt;
94 struct sg_table tx_sgt;
95 void *zeropage;
96};
97
98/* converts bits per word to CR0.DSS value */
99#define bits_per_word_to_dss(bpw) ((bpw) - 1)
100
101/**
102 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
103 * @host: SPI host
104 * @rate: desired SPI output clock rate
105 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
106 * @div_scr: pointer to return the scr divider
107 */
108static int ep93xx_spi_calc_divisors(struct spi_controller *host,
109 u32 rate, u8 *div_cpsr, u8 *div_scr)
110{
111 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
112 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
113 int cpsr, scr;
114
115 /*
116 * Make sure that max value is between values supported by the
117 * controller.
118 */
119 rate = clamp(rate, host->min_speed_hz, host->max_speed_hz);
120
121 /*
122 * Calculate divisors so that we can get speed according the
123 * following formula:
124 * rate = spi_clock_rate / (cpsr * (1 + scr))
125 *
126 * cpsr must be even number and starts from 2, scr can be any number
127 * between 0 and 255.
128 */
129 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
130 for (scr = 0; scr <= 255; scr++) {
131 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
132 *div_scr = (u8)scr;
133 *div_cpsr = (u8)cpsr;
134 return 0;
135 }
136 }
137 }
138
139 return -EINVAL;
140}
141
142static int ep93xx_spi_chip_setup(struct spi_controller *host,
143 struct spi_device *spi,
144 struct spi_transfer *xfer)
145{
146 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
147 u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
148 u8 div_cpsr = 0;
149 u8 div_scr = 0;
150 u16 cr0;
151 int err;
152
153 err = ep93xx_spi_calc_divisors(host, xfer->speed_hz,
154 &div_cpsr, &div_scr);
155 if (err)
156 return err;
157
158 cr0 = div_scr << SSPCR0_SCR_SHIFT;
159 if (spi->mode & SPI_CPOL)
160 cr0 |= SSPCR0_SPO;
161 if (spi->mode & SPI_CPHA)
162 cr0 |= SSPCR0_SPH;
163 cr0 |= dss;
164
165 dev_dbg(&host->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
166 spi->mode, div_cpsr, div_scr, dss);
167 dev_dbg(&host->dev, "setup: cr0 %#x\n", cr0);
168
169 writel(div_cpsr, espi->mmio + SSPCPSR);
170 writel(cr0, espi->mmio + SSPCR0);
171
172 return 0;
173}
174
175static void ep93xx_do_write(struct spi_controller *host)
176{
177 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
178 struct spi_transfer *xfer = host->cur_msg->state;
179 u32 val = 0;
180
181 if (xfer->bits_per_word > 8) {
182 if (xfer->tx_buf)
183 val = ((u16 *)xfer->tx_buf)[espi->tx];
184 espi->tx += 2;
185 } else {
186 if (xfer->tx_buf)
187 val = ((u8 *)xfer->tx_buf)[espi->tx];
188 espi->tx += 1;
189 }
190 writel(val, espi->mmio + SSPDR);
191}
192
193static void ep93xx_do_read(struct spi_controller *host)
194{
195 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
196 struct spi_transfer *xfer = host->cur_msg->state;
197 u32 val;
198
199 val = readl(espi->mmio + SSPDR);
200 if (xfer->bits_per_word > 8) {
201 if (xfer->rx_buf)
202 ((u16 *)xfer->rx_buf)[espi->rx] = val;
203 espi->rx += 2;
204 } else {
205 if (xfer->rx_buf)
206 ((u8 *)xfer->rx_buf)[espi->rx] = val;
207 espi->rx += 1;
208 }
209}
210
211/**
212 * ep93xx_spi_read_write() - perform next RX/TX transfer
213 * @host: SPI host
214 *
215 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
216 * called several times, the whole transfer will be completed. Returns
217 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
218 *
219 * When this function is finished, RX FIFO should be empty and TX FIFO should be
220 * full.
221 */
222static int ep93xx_spi_read_write(struct spi_controller *host)
223{
224 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
225 struct spi_transfer *xfer = host->cur_msg->state;
226
227 /* read as long as RX FIFO has frames in it */
228 while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
229 ep93xx_do_read(host);
230 espi->fifo_level--;
231 }
232
233 /* write as long as TX FIFO has room */
234 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
235 ep93xx_do_write(host);
236 espi->fifo_level++;
237 }
238
239 if (espi->rx == xfer->len)
240 return 0;
241
242 return -EINPROGRESS;
243}
244
245static enum dma_transfer_direction
246ep93xx_dma_data_to_trans_dir(enum dma_data_direction dir)
247{
248 switch (dir) {
249 case DMA_TO_DEVICE:
250 return DMA_MEM_TO_DEV;
251 case DMA_FROM_DEVICE:
252 return DMA_DEV_TO_MEM;
253 default:
254 return DMA_TRANS_NONE;
255 }
256}
257
258/**
259 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
260 * @host: SPI host
261 * @dir: DMA transfer direction
262 *
263 * Function configures the DMA, maps the buffer and prepares the DMA
264 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
265 * in case of failure.
266 */
267static struct dma_async_tx_descriptor *
268ep93xx_spi_dma_prepare(struct spi_controller *host,
269 enum dma_data_direction dir)
270{
271 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
272 struct spi_transfer *xfer = host->cur_msg->state;
273 struct dma_async_tx_descriptor *txd;
274 enum dma_slave_buswidth buswidth;
275 struct dma_slave_config conf;
276 struct scatterlist *sg;
277 struct sg_table *sgt;
278 struct dma_chan *chan;
279 const void *buf, *pbuf;
280 size_t len = xfer->len;
281 int i, ret, nents;
282
283 if (xfer->bits_per_word > 8)
284 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
285 else
286 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
287
288 memset(&conf, 0, sizeof(conf));
289 conf.direction = ep93xx_dma_data_to_trans_dir(dir);
290
291 if (dir == DMA_FROM_DEVICE) {
292 chan = espi->dma_rx;
293 buf = xfer->rx_buf;
294 sgt = &espi->rx_sgt;
295
296 conf.src_addr = espi->sspdr_phys;
297 conf.src_addr_width = buswidth;
298 } else {
299 chan = espi->dma_tx;
300 buf = xfer->tx_buf;
301 sgt = &espi->tx_sgt;
302
303 conf.dst_addr = espi->sspdr_phys;
304 conf.dst_addr_width = buswidth;
305 }
306
307 ret = dmaengine_slave_config(chan, &conf);
308 if (ret)
309 return ERR_PTR(ret);
310
311 /*
312 * We need to split the transfer into PAGE_SIZE'd chunks. This is
313 * because we are using @espi->zeropage to provide a zero RX buffer
314 * for the TX transfers and we have only allocated one page for that.
315 *
316 * For performance reasons we allocate a new sg_table only when
317 * needed. Otherwise we will re-use the current one. Eventually the
318 * last sg_table is released in ep93xx_spi_release_dma().
319 */
320
321 nents = DIV_ROUND_UP(len, PAGE_SIZE);
322 if (nents != sgt->nents) {
323 sg_free_table(sgt);
324
325 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
326 if (ret)
327 return ERR_PTR(ret);
328 }
329
330 pbuf = buf;
331 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
332 size_t bytes = min_t(size_t, len, PAGE_SIZE);
333
334 if (buf) {
335 sg_set_page(sg, virt_to_page(pbuf), bytes,
336 offset_in_page(pbuf));
337 } else {
338 sg_set_page(sg, virt_to_page(espi->zeropage),
339 bytes, 0);
340 }
341
342 pbuf += bytes;
343 len -= bytes;
344 }
345
346 if (WARN_ON(len)) {
347 dev_warn(&host->dev, "len = %zu expected 0!\n", len);
348 return ERR_PTR(-EINVAL);
349 }
350
351 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
352 if (!nents)
353 return ERR_PTR(-ENOMEM);
354
355 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction,
356 DMA_CTRL_ACK);
357 if (!txd) {
358 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
359 return ERR_PTR(-ENOMEM);
360 }
361 return txd;
362}
363
364/**
365 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
366 * @host: SPI host
367 * @dir: DMA transfer direction
368 *
369 * Function finishes with the DMA transfer. After this, the DMA buffer is
370 * unmapped.
371 */
372static void ep93xx_spi_dma_finish(struct spi_controller *host,
373 enum dma_data_direction dir)
374{
375 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
376 struct dma_chan *chan;
377 struct sg_table *sgt;
378
379 if (dir == DMA_FROM_DEVICE) {
380 chan = espi->dma_rx;
381 sgt = &espi->rx_sgt;
382 } else {
383 chan = espi->dma_tx;
384 sgt = &espi->tx_sgt;
385 }
386
387 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
388}
389
390static void ep93xx_spi_dma_callback(void *callback_param)
391{
392 struct spi_controller *host = callback_param;
393
394 ep93xx_spi_dma_finish(host, DMA_TO_DEVICE);
395 ep93xx_spi_dma_finish(host, DMA_FROM_DEVICE);
396
397 spi_finalize_current_transfer(host);
398}
399
400static int ep93xx_spi_dma_transfer(struct spi_controller *host)
401{
402 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
403 struct dma_async_tx_descriptor *rxd, *txd;
404
405 rxd = ep93xx_spi_dma_prepare(host, DMA_FROM_DEVICE);
406 if (IS_ERR(rxd)) {
407 dev_err(&host->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
408 return PTR_ERR(rxd);
409 }
410
411 txd = ep93xx_spi_dma_prepare(host, DMA_TO_DEVICE);
412 if (IS_ERR(txd)) {
413 ep93xx_spi_dma_finish(host, DMA_FROM_DEVICE);
414 dev_err(&host->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
415 return PTR_ERR(txd);
416 }
417
418 /* We are ready when RX is done */
419 rxd->callback = ep93xx_spi_dma_callback;
420 rxd->callback_param = host;
421
422 /* Now submit both descriptors and start DMA */
423 dmaengine_submit(rxd);
424 dmaengine_submit(txd);
425
426 dma_async_issue_pending(espi->dma_rx);
427 dma_async_issue_pending(espi->dma_tx);
428
429 /* signal that we need to wait for completion */
430 return 1;
431}
432
433static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
434{
435 struct spi_controller *host = dev_id;
436 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
437 u32 val;
438
439 /*
440 * If we got ROR (receive overrun) interrupt we know that something is
441 * wrong. Just abort the message.
442 */
443 if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
444 /* clear the overrun interrupt */
445 writel(0, espi->mmio + SSPICR);
446 dev_warn(&host->dev,
447 "receive overrun, aborting the message\n");
448 host->cur_msg->status = -EIO;
449 } else {
450 /*
451 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
452 * simply execute next data transfer.
453 */
454 if (ep93xx_spi_read_write(host)) {
455 /*
456 * In normal case, there still is some processing left
457 * for current transfer. Let's wait for the next
458 * interrupt then.
459 */
460 return IRQ_HANDLED;
461 }
462 }
463
464 /*
465 * Current transfer is finished, either with error or with success. In
466 * any case we disable interrupts and notify the worker to handle
467 * any post-processing of the message.
468 */
469 val = readl(espi->mmio + SSPCR1);
470 val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
471 writel(val, espi->mmio + SSPCR1);
472
473 spi_finalize_current_transfer(host);
474
475 return IRQ_HANDLED;
476}
477
478static int ep93xx_spi_transfer_one(struct spi_controller *host,
479 struct spi_device *spi,
480 struct spi_transfer *xfer)
481{
482 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
483 u32 val;
484 int ret;
485
486 ret = ep93xx_spi_chip_setup(host, spi, xfer);
487 if (ret) {
488 dev_err(&host->dev, "failed to setup chip for transfer\n");
489 return ret;
490 }
491
492 host->cur_msg->state = xfer;
493 espi->rx = 0;
494 espi->tx = 0;
495
496 /*
497 * There is no point of setting up DMA for the transfers which will
498 * fit into the FIFO and can be transferred with a single interrupt.
499 * So in these cases we will be using PIO and don't bother for DMA.
500 */
501 if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
502 return ep93xx_spi_dma_transfer(host);
503
504 /* Using PIO so prime the TX FIFO and enable interrupts */
505 ep93xx_spi_read_write(host);
506
507 val = readl(espi->mmio + SSPCR1);
508 val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
509 writel(val, espi->mmio + SSPCR1);
510
511 /* signal that we need to wait for completion */
512 return 1;
513}
514
515static int ep93xx_spi_prepare_message(struct spi_controller *host,
516 struct spi_message *msg)
517{
518 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
519 unsigned long timeout;
520
521 /*
522 * Just to be sure: flush any data from RX FIFO.
523 */
524 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
525 while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
526 if (time_after(jiffies, timeout)) {
527 dev_warn(&host->dev,
528 "timeout while flushing RX FIFO\n");
529 return -ETIMEDOUT;
530 }
531 readl(espi->mmio + SSPDR);
532 }
533
534 /*
535 * We explicitly handle FIFO level. This way we don't have to check TX
536 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
537 */
538 espi->fifo_level = 0;
539
540 return 0;
541}
542
543static int ep93xx_spi_prepare_hardware(struct spi_controller *host)
544{
545 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
546 u32 val;
547 int ret;
548
549 ret = clk_prepare_enable(espi->clk);
550 if (ret)
551 return ret;
552
553 val = readl(espi->mmio + SSPCR1);
554 val |= SSPCR1_SSE;
555 writel(val, espi->mmio + SSPCR1);
556
557 return 0;
558}
559
560static int ep93xx_spi_unprepare_hardware(struct spi_controller *host)
561{
562 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
563 u32 val;
564
565 val = readl(espi->mmio + SSPCR1);
566 val &= ~SSPCR1_SSE;
567 writel(val, espi->mmio + SSPCR1);
568
569 clk_disable_unprepare(espi->clk);
570
571 return 0;
572}
573
574static int ep93xx_spi_setup_dma(struct device *dev, struct ep93xx_spi *espi)
575{
576 int ret;
577
578 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
579 if (!espi->zeropage)
580 return -ENOMEM;
581
582 espi->dma_rx = dma_request_chan(dev, "rx");
583 if (IS_ERR(espi->dma_rx)) {
584 ret = dev_err_probe(dev, PTR_ERR(espi->dma_rx), "rx DMA setup failed");
585 goto fail_free_page;
586 }
587
588 espi->dma_tx = dma_request_chan(dev, "tx");
589 if (IS_ERR(espi->dma_tx)) {
590 ret = dev_err_probe(dev, PTR_ERR(espi->dma_tx), "tx DMA setup failed");
591 goto fail_release_rx;
592 }
593
594 return 0;
595
596fail_release_rx:
597 dma_release_channel(espi->dma_rx);
598 espi->dma_rx = NULL;
599fail_free_page:
600 free_page((unsigned long)espi->zeropage);
601
602 return ret;
603}
604
605static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
606{
607 if (espi->dma_rx) {
608 dma_release_channel(espi->dma_rx);
609 sg_free_table(&espi->rx_sgt);
610 }
611 if (espi->dma_tx) {
612 dma_release_channel(espi->dma_tx);
613 sg_free_table(&espi->tx_sgt);
614 }
615
616 if (espi->zeropage)
617 free_page((unsigned long)espi->zeropage);
618}
619
620static int ep93xx_spi_probe(struct platform_device *pdev)
621{
622 struct spi_controller *host;
623 struct ep93xx_spi *espi;
624 struct resource *res;
625 int irq;
626 int error;
627
628 irq = platform_get_irq(pdev, 0);
629 if (irq < 0)
630 return irq;
631
632 host = spi_alloc_host(&pdev->dev, sizeof(*espi));
633 if (!host)
634 return -ENOMEM;
635
636 host->use_gpio_descriptors = true;
637 host->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
638 host->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
639 host->prepare_message = ep93xx_spi_prepare_message;
640 host->transfer_one = ep93xx_spi_transfer_one;
641 host->bus_num = pdev->id;
642 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
643 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
644 /*
645 * The SPI core will count the number of GPIO descriptors to figure
646 * out the number of chip selects available on the platform.
647 */
648 host->num_chipselect = 0;
649
650 platform_set_drvdata(pdev, host);
651
652 espi = spi_controller_get_devdata(host);
653
654 espi->clk = devm_clk_get(&pdev->dev, NULL);
655 if (IS_ERR(espi->clk)) {
656 dev_err(&pdev->dev, "unable to get spi clock\n");
657 error = PTR_ERR(espi->clk);
658 goto fail_release_host;
659 }
660
661 /*
662 * Calculate maximum and minimum supported clock rates
663 * for the controller.
664 */
665 host->max_speed_hz = clk_get_rate(espi->clk) / 2;
666 host->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
667
668 espi->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
669 if (IS_ERR(espi->mmio)) {
670 error = PTR_ERR(espi->mmio);
671 goto fail_release_host;
672 }
673 espi->sspdr_phys = res->start + SSPDR;
674
675 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
676 0, "ep93xx-spi", host);
677 if (error) {
678 dev_err(&pdev->dev, "failed to request irq\n");
679 goto fail_release_host;
680 }
681
682 error = ep93xx_spi_setup_dma(&pdev->dev, espi);
683 if (error == -EPROBE_DEFER)
684 goto fail_release_host;
685
686 if (error)
687 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
688
689 /* make sure that the hardware is disabled */
690 writel(0, espi->mmio + SSPCR1);
691
692 device_set_node(&host->dev, dev_fwnode(&pdev->dev));
693 error = devm_spi_register_controller(&pdev->dev, host);
694 if (error) {
695 dev_err(&pdev->dev, "failed to register SPI host\n");
696 goto fail_free_dma;
697 }
698
699 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
700 (unsigned long)res->start, irq);
701
702 return 0;
703
704fail_free_dma:
705 ep93xx_spi_release_dma(espi);
706fail_release_host:
707 spi_controller_put(host);
708
709 return error;
710}
711
712static void ep93xx_spi_remove(struct platform_device *pdev)
713{
714 struct spi_controller *host = platform_get_drvdata(pdev);
715 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
716
717 ep93xx_spi_release_dma(espi);
718}
719
720static const struct of_device_id ep93xx_spi_of_ids[] = {
721 { .compatible = "cirrus,ep9301-spi" },
722 { /* sentinel */ }
723};
724MODULE_DEVICE_TABLE(of, ep93xx_spi_of_ids);
725
726static struct platform_driver ep93xx_spi_driver = {
727 .driver = {
728 .name = "ep93xx-spi",
729 .of_match_table = ep93xx_spi_of_ids,
730 },
731 .probe = ep93xx_spi_probe,
732 .remove = ep93xx_spi_remove,
733};
734module_platform_driver(ep93xx_spi_driver);
735
736MODULE_DESCRIPTION("EP93xx SPI Controller driver");
737MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
738MODULE_LICENSE("GPL");
739MODULE_ALIAS("platform:ep93xx-spi");
1/*
2 * Driver for Cirrus Logic EP93xx SPI controller.
3 *
4 * Copyright (C) 2010-2011 Mika Westerberg
5 *
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
7 *
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
9 *
10 * For more information about the SPI controller see documentation on Cirrus
11 * Logic web site:
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/dmaengine.h>
25#include <linux/bitops.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/workqueue.h>
29#include <linux/sched.h>
30#include <linux/scatterlist.h>
31#include <linux/spi/spi.h>
32
33#include <mach/dma.h>
34#include <mach/ep93xx_spi.h>
35
36#define SSPCR0 0x0000
37#define SSPCR0_MODE_SHIFT 6
38#define SSPCR0_SCR_SHIFT 8
39
40#define SSPCR1 0x0004
41#define SSPCR1_RIE BIT(0)
42#define SSPCR1_TIE BIT(1)
43#define SSPCR1_RORIE BIT(2)
44#define SSPCR1_LBM BIT(3)
45#define SSPCR1_SSE BIT(4)
46#define SSPCR1_MS BIT(5)
47#define SSPCR1_SOD BIT(6)
48
49#define SSPDR 0x0008
50
51#define SSPSR 0x000c
52#define SSPSR_TFE BIT(0)
53#define SSPSR_TNF BIT(1)
54#define SSPSR_RNE BIT(2)
55#define SSPSR_RFF BIT(3)
56#define SSPSR_BSY BIT(4)
57#define SSPCPSR 0x0010
58
59#define SSPIIR 0x0014
60#define SSPIIR_RIS BIT(0)
61#define SSPIIR_TIS BIT(1)
62#define SSPIIR_RORIS BIT(2)
63#define SSPICR SSPIIR
64
65/* timeout in milliseconds */
66#define SPI_TIMEOUT 5
67/* maximum depth of RX/TX FIFO */
68#define SPI_FIFO_SIZE 8
69
70/**
71 * struct ep93xx_spi - EP93xx SPI controller structure
72 * @lock: spinlock that protects concurrent accesses to fields @running,
73 * @current_msg and @msg_queue
74 * @pdev: pointer to platform device
75 * @clk: clock for the controller
76 * @regs_base: pointer to ioremap()'d registers
77 * @sspdr_phys: physical address of the SSPDR register
78 * @irq: IRQ number used by the driver
79 * @min_rate: minimum clock rate (in Hz) supported by the controller
80 * @max_rate: maximum clock rate (in Hz) supported by the controller
81 * @running: is the queue running
82 * @wq: workqueue used by the driver
83 * @msg_work: work that is queued for the driver
84 * @wait: wait here until given transfer is completed
85 * @msg_queue: queue for the messages
86 * @current_msg: message that is currently processed (or %NULL if none)
87 * @tx: current byte in transfer to transmit
88 * @rx: current byte in transfer to receive
89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
90 * frame decreases this level and sending one frame increases it.
91 * @dma_rx: RX DMA channel
92 * @dma_tx: TX DMA channel
93 * @dma_rx_data: RX parameters passed to the DMA engine
94 * @dma_tx_data: TX parameters passed to the DMA engine
95 * @rx_sgt: sg table for RX transfers
96 * @tx_sgt: sg table for TX transfers
97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
98 * the client
99 *
100 * This structure holds EP93xx SPI controller specific information. When
101 * @running is %true, driver accepts transfer requests from protocol drivers.
102 * @current_msg is used to hold pointer to the message that is currently
103 * processed. If @current_msg is %NULL, it means that no processing is going
104 * on.
105 *
106 * Most of the fields are only written once and they can be accessed without
107 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
108 * @running, and @msg_queue.
109 */
110struct ep93xx_spi {
111 spinlock_t lock;
112 const struct platform_device *pdev;
113 struct clk *clk;
114 void __iomem *regs_base;
115 unsigned long sspdr_phys;
116 int irq;
117 unsigned long min_rate;
118 unsigned long max_rate;
119 bool running;
120 struct workqueue_struct *wq;
121 struct work_struct msg_work;
122 struct completion wait;
123 struct list_head msg_queue;
124 struct spi_message *current_msg;
125 size_t tx;
126 size_t rx;
127 size_t fifo_level;
128 struct dma_chan *dma_rx;
129 struct dma_chan *dma_tx;
130 struct ep93xx_dma_data dma_rx_data;
131 struct ep93xx_dma_data dma_tx_data;
132 struct sg_table rx_sgt;
133 struct sg_table tx_sgt;
134 void *zeropage;
135};
136
137/**
138 * struct ep93xx_spi_chip - SPI device hardware settings
139 * @spi: back pointer to the SPI device
140 * @rate: max rate in hz this chip supports
141 * @div_cpsr: cpsr (pre-scaler) divider
142 * @div_scr: scr divider
143 * @dss: bits per word (4 - 16 bits)
144 * @ops: private chip operations
145 *
146 * This structure is used to store hardware register specific settings for each
147 * SPI device. Settings are written to hardware by function
148 * ep93xx_spi_chip_setup().
149 */
150struct ep93xx_spi_chip {
151 const struct spi_device *spi;
152 unsigned long rate;
153 u8 div_cpsr;
154 u8 div_scr;
155 u8 dss;
156 struct ep93xx_spi_chip_ops *ops;
157};
158
159/* converts bits per word to CR0.DSS value */
160#define bits_per_word_to_dss(bpw) ((bpw) - 1)
161
162static inline void
163ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value)
164{
165 __raw_writeb(value, espi->regs_base + reg);
166}
167
168static inline u8
169ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
170{
171 return __raw_readb(spi->regs_base + reg);
172}
173
174static inline void
175ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value)
176{
177 __raw_writew(value, espi->regs_base + reg);
178}
179
180static inline u16
181ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
182{
183 return __raw_readw(spi->regs_base + reg);
184}
185
186static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
187{
188 u8 regval;
189 int err;
190
191 err = clk_enable(espi->clk);
192 if (err)
193 return err;
194
195 regval = ep93xx_spi_read_u8(espi, SSPCR1);
196 regval |= SSPCR1_SSE;
197 ep93xx_spi_write_u8(espi, SSPCR1, regval);
198
199 return 0;
200}
201
202static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
203{
204 u8 regval;
205
206 regval = ep93xx_spi_read_u8(espi, SSPCR1);
207 regval &= ~SSPCR1_SSE;
208 ep93xx_spi_write_u8(espi, SSPCR1, regval);
209
210 clk_disable(espi->clk);
211}
212
213static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
214{
215 u8 regval;
216
217 regval = ep93xx_spi_read_u8(espi, SSPCR1);
218 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
219 ep93xx_spi_write_u8(espi, SSPCR1, regval);
220}
221
222static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
223{
224 u8 regval;
225
226 regval = ep93xx_spi_read_u8(espi, SSPCR1);
227 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
228 ep93xx_spi_write_u8(espi, SSPCR1, regval);
229}
230
231/**
232 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
233 * @espi: ep93xx SPI controller struct
234 * @chip: divisors are calculated for this chip
235 * @rate: desired SPI output clock rate
236 *
237 * Function calculates cpsr (clock pre-scaler) and scr divisors based on
238 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
239 * for some reason, divisors cannot be calculated nothing is stored and
240 * %-EINVAL is returned.
241 */
242static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
243 struct ep93xx_spi_chip *chip,
244 unsigned long rate)
245{
246 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
247 int cpsr, scr;
248
249 /*
250 * Make sure that max value is between values supported by the
251 * controller. Note that minimum value is already checked in
252 * ep93xx_spi_transfer().
253 */
254 rate = clamp(rate, espi->min_rate, espi->max_rate);
255
256 /*
257 * Calculate divisors so that we can get speed according the
258 * following formula:
259 * rate = spi_clock_rate / (cpsr * (1 + scr))
260 *
261 * cpsr must be even number and starts from 2, scr can be any number
262 * between 0 and 255.
263 */
264 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
265 for (scr = 0; scr <= 255; scr++) {
266 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
267 chip->div_scr = (u8)scr;
268 chip->div_cpsr = (u8)cpsr;
269 return 0;
270 }
271 }
272 }
273
274 return -EINVAL;
275}
276
277static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
278{
279 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
280 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
281
282 if (chip->ops && chip->ops->cs_control)
283 chip->ops->cs_control(spi, value);
284}
285
286/**
287 * ep93xx_spi_setup() - setup an SPI device
288 * @spi: SPI device to setup
289 *
290 * This function sets up SPI device mode, speed etc. Can be called multiple
291 * times for a single device. Returns %0 in case of success, negative error in
292 * case of failure. When this function returns success, the device is
293 * deselected.
294 */
295static int ep93xx_spi_setup(struct spi_device *spi)
296{
297 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
298 struct ep93xx_spi_chip *chip;
299
300 if (spi->bits_per_word < 4 || spi->bits_per_word > 16) {
301 dev_err(&espi->pdev->dev, "invalid bits per word %d\n",
302 spi->bits_per_word);
303 return -EINVAL;
304 }
305
306 chip = spi_get_ctldata(spi);
307 if (!chip) {
308 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
309 spi->modalias);
310
311 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
312 if (!chip)
313 return -ENOMEM;
314
315 chip->spi = spi;
316 chip->ops = spi->controller_data;
317
318 if (chip->ops && chip->ops->setup) {
319 int ret = chip->ops->setup(spi);
320 if (ret) {
321 kfree(chip);
322 return ret;
323 }
324 }
325
326 spi_set_ctldata(spi, chip);
327 }
328
329 if (spi->max_speed_hz != chip->rate) {
330 int err;
331
332 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz);
333 if (err != 0) {
334 spi_set_ctldata(spi, NULL);
335 kfree(chip);
336 return err;
337 }
338 chip->rate = spi->max_speed_hz;
339 }
340
341 chip->dss = bits_per_word_to_dss(spi->bits_per_word);
342
343 ep93xx_spi_cs_control(spi, false);
344 return 0;
345}
346
347/**
348 * ep93xx_spi_transfer() - queue message to be transferred
349 * @spi: target SPI device
350 * @msg: message to be transferred
351 *
352 * This function is called by SPI device drivers when they are going to transfer
353 * a new message. It simply puts the message in the queue and schedules
354 * workqueue to perform the actual transfer later on.
355 *
356 * Returns %0 on success and negative error in case of failure.
357 */
358static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
359{
360 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
361 struct spi_transfer *t;
362 unsigned long flags;
363
364 if (!msg || !msg->complete)
365 return -EINVAL;
366
367 /* first validate each transfer */
368 list_for_each_entry(t, &msg->transfers, transfer_list) {
369 if (t->bits_per_word) {
370 if (t->bits_per_word < 4 || t->bits_per_word > 16)
371 return -EINVAL;
372 }
373 if (t->speed_hz && t->speed_hz < espi->min_rate)
374 return -EINVAL;
375 }
376
377 /*
378 * Now that we own the message, let's initialize it so that it is
379 * suitable for us. We use @msg->status to signal whether there was
380 * error in transfer and @msg->state is used to hold pointer to the
381 * current transfer (or %NULL if no active current transfer).
382 */
383 msg->state = NULL;
384 msg->status = 0;
385 msg->actual_length = 0;
386
387 spin_lock_irqsave(&espi->lock, flags);
388 if (!espi->running) {
389 spin_unlock_irqrestore(&espi->lock, flags);
390 return -ESHUTDOWN;
391 }
392 list_add_tail(&msg->queue, &espi->msg_queue);
393 queue_work(espi->wq, &espi->msg_work);
394 spin_unlock_irqrestore(&espi->lock, flags);
395
396 return 0;
397}
398
399/**
400 * ep93xx_spi_cleanup() - cleans up master controller specific state
401 * @spi: SPI device to cleanup
402 *
403 * This function releases master controller specific state for given @spi
404 * device.
405 */
406static void ep93xx_spi_cleanup(struct spi_device *spi)
407{
408 struct ep93xx_spi_chip *chip;
409
410 chip = spi_get_ctldata(spi);
411 if (chip) {
412 if (chip->ops && chip->ops->cleanup)
413 chip->ops->cleanup(spi);
414 spi_set_ctldata(spi, NULL);
415 kfree(chip);
416 }
417}
418
419/**
420 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
421 * @espi: ep93xx SPI controller struct
422 * @chip: chip specific settings
423 *
424 * This function sets up the actual hardware registers with settings given in
425 * @chip. Note that no validation is done so make sure that callers validate
426 * settings before calling this.
427 */
428static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
429 const struct ep93xx_spi_chip *chip)
430{
431 u16 cr0;
432
433 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT;
434 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
435 cr0 |= chip->dss;
436
437 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
438 chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss);
439 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
440
441 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr);
442 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
443}
444
445static inline int bits_per_word(const struct ep93xx_spi *espi)
446{
447 struct spi_message *msg = espi->current_msg;
448 struct spi_transfer *t = msg->state;
449
450 return t->bits_per_word ? t->bits_per_word : msg->spi->bits_per_word;
451}
452
453static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
454{
455 if (bits_per_word(espi) > 8) {
456 u16 tx_val = 0;
457
458 if (t->tx_buf)
459 tx_val = ((u16 *)t->tx_buf)[espi->tx];
460 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
461 espi->tx += sizeof(tx_val);
462 } else {
463 u8 tx_val = 0;
464
465 if (t->tx_buf)
466 tx_val = ((u8 *)t->tx_buf)[espi->tx];
467 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
468 espi->tx += sizeof(tx_val);
469 }
470}
471
472static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
473{
474 if (bits_per_word(espi) > 8) {
475 u16 rx_val;
476
477 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
478 if (t->rx_buf)
479 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
480 espi->rx += sizeof(rx_val);
481 } else {
482 u8 rx_val;
483
484 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
485 if (t->rx_buf)
486 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
487 espi->rx += sizeof(rx_val);
488 }
489}
490
491/**
492 * ep93xx_spi_read_write() - perform next RX/TX transfer
493 * @espi: ep93xx SPI controller struct
494 *
495 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
496 * called several times, the whole transfer will be completed. Returns
497 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
498 *
499 * When this function is finished, RX FIFO should be empty and TX FIFO should be
500 * full.
501 */
502static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
503{
504 struct spi_message *msg = espi->current_msg;
505 struct spi_transfer *t = msg->state;
506
507 /* read as long as RX FIFO has frames in it */
508 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
509 ep93xx_do_read(espi, t);
510 espi->fifo_level--;
511 }
512
513 /* write as long as TX FIFO has room */
514 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
515 ep93xx_do_write(espi, t);
516 espi->fifo_level++;
517 }
518
519 if (espi->rx == t->len)
520 return 0;
521
522 return -EINPROGRESS;
523}
524
525static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
526{
527 /*
528 * Now everything is set up for the current transfer. We prime the TX
529 * FIFO, enable interrupts, and wait for the transfer to complete.
530 */
531 if (ep93xx_spi_read_write(espi)) {
532 ep93xx_spi_enable_interrupts(espi);
533 wait_for_completion(&espi->wait);
534 }
535}
536
537/**
538 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
539 * @espi: ep93xx SPI controller struct
540 * @dir: DMA transfer direction
541 *
542 * Function configures the DMA, maps the buffer and prepares the DMA
543 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
544 * in case of failure.
545 */
546static struct dma_async_tx_descriptor *
547ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
548{
549 struct spi_transfer *t = espi->current_msg->state;
550 struct dma_async_tx_descriptor *txd;
551 enum dma_slave_buswidth buswidth;
552 struct dma_slave_config conf;
553 struct scatterlist *sg;
554 struct sg_table *sgt;
555 struct dma_chan *chan;
556 const void *buf, *pbuf;
557 size_t len = t->len;
558 int i, ret, nents;
559
560 if (bits_per_word(espi) > 8)
561 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
562 else
563 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
564
565 memset(&conf, 0, sizeof(conf));
566 conf.direction = dir;
567
568 if (dir == DMA_FROM_DEVICE) {
569 chan = espi->dma_rx;
570 buf = t->rx_buf;
571 sgt = &espi->rx_sgt;
572
573 conf.src_addr = espi->sspdr_phys;
574 conf.src_addr_width = buswidth;
575 } else {
576 chan = espi->dma_tx;
577 buf = t->tx_buf;
578 sgt = &espi->tx_sgt;
579
580 conf.dst_addr = espi->sspdr_phys;
581 conf.dst_addr_width = buswidth;
582 }
583
584 ret = dmaengine_slave_config(chan, &conf);
585 if (ret)
586 return ERR_PTR(ret);
587
588 /*
589 * We need to split the transfer into PAGE_SIZE'd chunks. This is
590 * because we are using @espi->zeropage to provide a zero RX buffer
591 * for the TX transfers and we have only allocated one page for that.
592 *
593 * For performance reasons we allocate a new sg_table only when
594 * needed. Otherwise we will re-use the current one. Eventually the
595 * last sg_table is released in ep93xx_spi_release_dma().
596 */
597
598 nents = DIV_ROUND_UP(len, PAGE_SIZE);
599 if (nents != sgt->nents) {
600 sg_free_table(sgt);
601
602 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
603 if (ret)
604 return ERR_PTR(ret);
605 }
606
607 pbuf = buf;
608 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
609 size_t bytes = min_t(size_t, len, PAGE_SIZE);
610
611 if (buf) {
612 sg_set_page(sg, virt_to_page(pbuf), bytes,
613 offset_in_page(pbuf));
614 } else {
615 sg_set_page(sg, virt_to_page(espi->zeropage),
616 bytes, 0);
617 }
618
619 pbuf += bytes;
620 len -= bytes;
621 }
622
623 if (WARN_ON(len)) {
624 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len);
625 return ERR_PTR(-EINVAL);
626 }
627
628 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
629 if (!nents)
630 return ERR_PTR(-ENOMEM);
631
632 txd = chan->device->device_prep_slave_sg(chan, sgt->sgl, nents,
633 dir, DMA_CTRL_ACK);
634 if (!txd) {
635 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
636 return ERR_PTR(-ENOMEM);
637 }
638 return txd;
639}
640
641/**
642 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
643 * @espi: ep93xx SPI controller struct
644 * @dir: DMA transfer direction
645 *
646 * Function finishes with the DMA transfer. After this, the DMA buffer is
647 * unmapped.
648 */
649static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
650 enum dma_data_direction dir)
651{
652 struct dma_chan *chan;
653 struct sg_table *sgt;
654
655 if (dir == DMA_FROM_DEVICE) {
656 chan = espi->dma_rx;
657 sgt = &espi->rx_sgt;
658 } else {
659 chan = espi->dma_tx;
660 sgt = &espi->tx_sgt;
661 }
662
663 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
664}
665
666static void ep93xx_spi_dma_callback(void *callback_param)
667{
668 complete(callback_param);
669}
670
671static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
672{
673 struct spi_message *msg = espi->current_msg;
674 struct dma_async_tx_descriptor *rxd, *txd;
675
676 rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE);
677 if (IS_ERR(rxd)) {
678 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
679 msg->status = PTR_ERR(rxd);
680 return;
681 }
682
683 txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE);
684 if (IS_ERR(txd)) {
685 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
686 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
687 msg->status = PTR_ERR(txd);
688 return;
689 }
690
691 /* We are ready when RX is done */
692 rxd->callback = ep93xx_spi_dma_callback;
693 rxd->callback_param = &espi->wait;
694
695 /* Now submit both descriptors and wait while they finish */
696 dmaengine_submit(rxd);
697 dmaengine_submit(txd);
698
699 dma_async_issue_pending(espi->dma_rx);
700 dma_async_issue_pending(espi->dma_tx);
701
702 wait_for_completion(&espi->wait);
703
704 ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE);
705 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
706}
707
708/**
709 * ep93xx_spi_process_transfer() - processes one SPI transfer
710 * @espi: ep93xx SPI controller struct
711 * @msg: current message
712 * @t: transfer to process
713 *
714 * This function processes one SPI transfer given in @t. Function waits until
715 * transfer is complete (may sleep) and updates @msg->status based on whether
716 * transfer was successfully processed or not.
717 */
718static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
719 struct spi_message *msg,
720 struct spi_transfer *t)
721{
722 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
723
724 msg->state = t;
725
726 /*
727 * Handle any transfer specific settings if needed. We use
728 * temporary chip settings here and restore original later when
729 * the transfer is finished.
730 */
731 if (t->speed_hz || t->bits_per_word) {
732 struct ep93xx_spi_chip tmp_chip = *chip;
733
734 if (t->speed_hz) {
735 int err;
736
737 err = ep93xx_spi_calc_divisors(espi, &tmp_chip,
738 t->speed_hz);
739 if (err) {
740 dev_err(&espi->pdev->dev,
741 "failed to adjust speed\n");
742 msg->status = err;
743 return;
744 }
745 }
746
747 if (t->bits_per_word)
748 tmp_chip.dss = bits_per_word_to_dss(t->bits_per_word);
749
750 /*
751 * Set up temporary new hw settings for this transfer.
752 */
753 ep93xx_spi_chip_setup(espi, &tmp_chip);
754 }
755
756 espi->rx = 0;
757 espi->tx = 0;
758
759 /*
760 * There is no point of setting up DMA for the transfers which will
761 * fit into the FIFO and can be transferred with a single interrupt.
762 * So in these cases we will be using PIO and don't bother for DMA.
763 */
764 if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
765 ep93xx_spi_dma_transfer(espi);
766 else
767 ep93xx_spi_pio_transfer(espi);
768
769 /*
770 * In case of error during transmit, we bail out from processing
771 * the message.
772 */
773 if (msg->status)
774 return;
775
776 msg->actual_length += t->len;
777
778 /*
779 * After this transfer is finished, perform any possible
780 * post-transfer actions requested by the protocol driver.
781 */
782 if (t->delay_usecs) {
783 set_current_state(TASK_UNINTERRUPTIBLE);
784 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
785 }
786 if (t->cs_change) {
787 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
788 /*
789 * In case protocol driver is asking us to drop the
790 * chipselect briefly, we let the scheduler to handle
791 * any "delay" here.
792 */
793 ep93xx_spi_cs_control(msg->spi, false);
794 cond_resched();
795 ep93xx_spi_cs_control(msg->spi, true);
796 }
797 }
798
799 if (t->speed_hz || t->bits_per_word)
800 ep93xx_spi_chip_setup(espi, chip);
801}
802
803/*
804 * ep93xx_spi_process_message() - process one SPI message
805 * @espi: ep93xx SPI controller struct
806 * @msg: message to process
807 *
808 * This function processes a single SPI message. We go through all transfers in
809 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
810 * asserted during the whole message (unless per transfer cs_change is set).
811 *
812 * @msg->status contains %0 in case of success or negative error code in case of
813 * failure.
814 */
815static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
816 struct spi_message *msg)
817{
818 unsigned long timeout;
819 struct spi_transfer *t;
820 int err;
821
822 /*
823 * Enable the SPI controller and its clock.
824 */
825 err = ep93xx_spi_enable(espi);
826 if (err) {
827 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
828 msg->status = err;
829 return;
830 }
831
832 /*
833 * Just to be sure: flush any data from RX FIFO.
834 */
835 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
836 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
837 if (time_after(jiffies, timeout)) {
838 dev_warn(&espi->pdev->dev,
839 "timeout while flushing RX FIFO\n");
840 msg->status = -ETIMEDOUT;
841 return;
842 }
843 ep93xx_spi_read_u16(espi, SSPDR);
844 }
845
846 /*
847 * We explicitly handle FIFO level. This way we don't have to check TX
848 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
849 */
850 espi->fifo_level = 0;
851
852 /*
853 * Update SPI controller registers according to spi device and assert
854 * the chipselect.
855 */
856 ep93xx_spi_chip_setup(espi, spi_get_ctldata(msg->spi));
857 ep93xx_spi_cs_control(msg->spi, true);
858
859 list_for_each_entry(t, &msg->transfers, transfer_list) {
860 ep93xx_spi_process_transfer(espi, msg, t);
861 if (msg->status)
862 break;
863 }
864
865 /*
866 * Now the whole message is transferred (or failed for some reason). We
867 * deselect the device and disable the SPI controller.
868 */
869 ep93xx_spi_cs_control(msg->spi, false);
870 ep93xx_spi_disable(espi);
871}
872
873#define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
874
875/**
876 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
877 * @work: work struct
878 *
879 * Workqueue worker function. This function is called when there are new
880 * SPI messages to be processed. Message is taken out from the queue and then
881 * passed to ep93xx_spi_process_message().
882 *
883 * After message is transferred, protocol driver is notified by calling
884 * @msg->complete(). In case of error, @msg->status is set to negative error
885 * number, otherwise it contains zero (and @msg->actual_length is updated).
886 */
887static void ep93xx_spi_work(struct work_struct *work)
888{
889 struct ep93xx_spi *espi = work_to_espi(work);
890 struct spi_message *msg;
891
892 spin_lock_irq(&espi->lock);
893 if (!espi->running || espi->current_msg ||
894 list_empty(&espi->msg_queue)) {
895 spin_unlock_irq(&espi->lock);
896 return;
897 }
898 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
899 list_del_init(&msg->queue);
900 espi->current_msg = msg;
901 spin_unlock_irq(&espi->lock);
902
903 ep93xx_spi_process_message(espi, msg);
904
905 /*
906 * Update the current message and re-schedule ourselves if there are
907 * more messages in the queue.
908 */
909 spin_lock_irq(&espi->lock);
910 espi->current_msg = NULL;
911 if (espi->running && !list_empty(&espi->msg_queue))
912 queue_work(espi->wq, &espi->msg_work);
913 spin_unlock_irq(&espi->lock);
914
915 /* notify the protocol driver that we are done with this message */
916 msg->complete(msg->context);
917}
918
919static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
920{
921 struct ep93xx_spi *espi = dev_id;
922 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
923
924 /*
925 * If we got ROR (receive overrun) interrupt we know that something is
926 * wrong. Just abort the message.
927 */
928 if (unlikely(irq_status & SSPIIR_RORIS)) {
929 /* clear the overrun interrupt */
930 ep93xx_spi_write_u8(espi, SSPICR, 0);
931 dev_warn(&espi->pdev->dev,
932 "receive overrun, aborting the message\n");
933 espi->current_msg->status = -EIO;
934 } else {
935 /*
936 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
937 * simply execute next data transfer.
938 */
939 if (ep93xx_spi_read_write(espi)) {
940 /*
941 * In normal case, there still is some processing left
942 * for current transfer. Let's wait for the next
943 * interrupt then.
944 */
945 return IRQ_HANDLED;
946 }
947 }
948
949 /*
950 * Current transfer is finished, either with error or with success. In
951 * any case we disable interrupts and notify the worker to handle
952 * any post-processing of the message.
953 */
954 ep93xx_spi_disable_interrupts(espi);
955 complete(&espi->wait);
956 return IRQ_HANDLED;
957}
958
959static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
960{
961 if (ep93xx_dma_chan_is_m2p(chan))
962 return false;
963
964 chan->private = filter_param;
965 return true;
966}
967
968static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
969{
970 dma_cap_mask_t mask;
971 int ret;
972
973 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
974 if (!espi->zeropage)
975 return -ENOMEM;
976
977 dma_cap_zero(mask);
978 dma_cap_set(DMA_SLAVE, mask);
979
980 espi->dma_rx_data.port = EP93XX_DMA_SSP;
981 espi->dma_rx_data.direction = DMA_FROM_DEVICE;
982 espi->dma_rx_data.name = "ep93xx-spi-rx";
983
984 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
985 &espi->dma_rx_data);
986 if (!espi->dma_rx) {
987 ret = -ENODEV;
988 goto fail_free_page;
989 }
990
991 espi->dma_tx_data.port = EP93XX_DMA_SSP;
992 espi->dma_tx_data.direction = DMA_TO_DEVICE;
993 espi->dma_tx_data.name = "ep93xx-spi-tx";
994
995 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
996 &espi->dma_tx_data);
997 if (!espi->dma_tx) {
998 ret = -ENODEV;
999 goto fail_release_rx;
1000 }
1001
1002 return 0;
1003
1004fail_release_rx:
1005 dma_release_channel(espi->dma_rx);
1006 espi->dma_rx = NULL;
1007fail_free_page:
1008 free_page((unsigned long)espi->zeropage);
1009
1010 return ret;
1011}
1012
1013static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
1014{
1015 if (espi->dma_rx) {
1016 dma_release_channel(espi->dma_rx);
1017 sg_free_table(&espi->rx_sgt);
1018 }
1019 if (espi->dma_tx) {
1020 dma_release_channel(espi->dma_tx);
1021 sg_free_table(&espi->tx_sgt);
1022 }
1023
1024 if (espi->zeropage)
1025 free_page((unsigned long)espi->zeropage);
1026}
1027
1028static int __init ep93xx_spi_probe(struct platform_device *pdev)
1029{
1030 struct spi_master *master;
1031 struct ep93xx_spi_info *info;
1032 struct ep93xx_spi *espi;
1033 struct resource *res;
1034 int error;
1035
1036 info = pdev->dev.platform_data;
1037
1038 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
1039 if (!master) {
1040 dev_err(&pdev->dev, "failed to allocate spi master\n");
1041 return -ENOMEM;
1042 }
1043
1044 master->setup = ep93xx_spi_setup;
1045 master->transfer = ep93xx_spi_transfer;
1046 master->cleanup = ep93xx_spi_cleanup;
1047 master->bus_num = pdev->id;
1048 master->num_chipselect = info->num_chipselect;
1049 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1050
1051 platform_set_drvdata(pdev, master);
1052
1053 espi = spi_master_get_devdata(master);
1054
1055 espi->clk = clk_get(&pdev->dev, NULL);
1056 if (IS_ERR(espi->clk)) {
1057 dev_err(&pdev->dev, "unable to get spi clock\n");
1058 error = PTR_ERR(espi->clk);
1059 goto fail_release_master;
1060 }
1061
1062 spin_lock_init(&espi->lock);
1063 init_completion(&espi->wait);
1064
1065 /*
1066 * Calculate maximum and minimum supported clock rates
1067 * for the controller.
1068 */
1069 espi->max_rate = clk_get_rate(espi->clk) / 2;
1070 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
1071 espi->pdev = pdev;
1072
1073 espi->irq = platform_get_irq(pdev, 0);
1074 if (espi->irq < 0) {
1075 error = -EBUSY;
1076 dev_err(&pdev->dev, "failed to get irq resources\n");
1077 goto fail_put_clock;
1078 }
1079
1080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1081 if (!res) {
1082 dev_err(&pdev->dev, "unable to get iomem resource\n");
1083 error = -ENODEV;
1084 goto fail_put_clock;
1085 }
1086
1087 res = request_mem_region(res->start, resource_size(res), pdev->name);
1088 if (!res) {
1089 dev_err(&pdev->dev, "unable to request iomem resources\n");
1090 error = -EBUSY;
1091 goto fail_put_clock;
1092 }
1093
1094 espi->sspdr_phys = res->start + SSPDR;
1095 espi->regs_base = ioremap(res->start, resource_size(res));
1096 if (!espi->regs_base) {
1097 dev_err(&pdev->dev, "failed to map resources\n");
1098 error = -ENODEV;
1099 goto fail_free_mem;
1100 }
1101
1102 error = request_irq(espi->irq, ep93xx_spi_interrupt, 0,
1103 "ep93xx-spi", espi);
1104 if (error) {
1105 dev_err(&pdev->dev, "failed to request irq\n");
1106 goto fail_unmap_regs;
1107 }
1108
1109 if (info->use_dma && ep93xx_spi_setup_dma(espi))
1110 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
1111
1112 espi->wq = create_singlethread_workqueue("ep93xx_spid");
1113 if (!espi->wq) {
1114 dev_err(&pdev->dev, "unable to create workqueue\n");
1115 goto fail_free_dma;
1116 }
1117 INIT_WORK(&espi->msg_work, ep93xx_spi_work);
1118 INIT_LIST_HEAD(&espi->msg_queue);
1119 espi->running = true;
1120
1121 /* make sure that the hardware is disabled */
1122 ep93xx_spi_write_u8(espi, SSPCR1, 0);
1123
1124 error = spi_register_master(master);
1125 if (error) {
1126 dev_err(&pdev->dev, "failed to register SPI master\n");
1127 goto fail_free_queue;
1128 }
1129
1130 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
1131 (unsigned long)res->start, espi->irq);
1132
1133 return 0;
1134
1135fail_free_queue:
1136 destroy_workqueue(espi->wq);
1137fail_free_dma:
1138 ep93xx_spi_release_dma(espi);
1139 free_irq(espi->irq, espi);
1140fail_unmap_regs:
1141 iounmap(espi->regs_base);
1142fail_free_mem:
1143 release_mem_region(res->start, resource_size(res));
1144fail_put_clock:
1145 clk_put(espi->clk);
1146fail_release_master:
1147 spi_master_put(master);
1148 platform_set_drvdata(pdev, NULL);
1149
1150 return error;
1151}
1152
1153static int __exit ep93xx_spi_remove(struct platform_device *pdev)
1154{
1155 struct spi_master *master = platform_get_drvdata(pdev);
1156 struct ep93xx_spi *espi = spi_master_get_devdata(master);
1157 struct resource *res;
1158
1159 spin_lock_irq(&espi->lock);
1160 espi->running = false;
1161 spin_unlock_irq(&espi->lock);
1162
1163 destroy_workqueue(espi->wq);
1164
1165 /*
1166 * Complete remaining messages with %-ESHUTDOWN status.
1167 */
1168 spin_lock_irq(&espi->lock);
1169 while (!list_empty(&espi->msg_queue)) {
1170 struct spi_message *msg;
1171
1172 msg = list_first_entry(&espi->msg_queue,
1173 struct spi_message, queue);
1174 list_del_init(&msg->queue);
1175 msg->status = -ESHUTDOWN;
1176 spin_unlock_irq(&espi->lock);
1177 msg->complete(msg->context);
1178 spin_lock_irq(&espi->lock);
1179 }
1180 spin_unlock_irq(&espi->lock);
1181
1182 ep93xx_spi_release_dma(espi);
1183 free_irq(espi->irq, espi);
1184 iounmap(espi->regs_base);
1185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186 release_mem_region(res->start, resource_size(res));
1187 clk_put(espi->clk);
1188 platform_set_drvdata(pdev, NULL);
1189
1190 spi_unregister_master(master);
1191 return 0;
1192}
1193
1194static struct platform_driver ep93xx_spi_driver = {
1195 .driver = {
1196 .name = "ep93xx-spi",
1197 .owner = THIS_MODULE,
1198 },
1199 .remove = __exit_p(ep93xx_spi_remove),
1200};
1201
1202static int __init ep93xx_spi_init(void)
1203{
1204 return platform_driver_probe(&ep93xx_spi_driver, ep93xx_spi_probe);
1205}
1206module_init(ep93xx_spi_init);
1207
1208static void __exit ep93xx_spi_exit(void)
1209{
1210 platform_driver_unregister(&ep93xx_spi_driver);
1211}
1212module_exit(ep93xx_spi_exit);
1213
1214MODULE_DESCRIPTION("EP93xx SPI Controller driver");
1215MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1216MODULE_LICENSE("GPL");
1217MODULE_ALIAS("platform:ep93xx-spi");