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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
4 *
5 * Copyright (c) 2000 Nils Faerber
6 *
7 * Based on rtc.c by Paul Gortmaker
8 *
9 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
10 *
11 * Modifications from:
12 * CIH <cih@coventive.com>
13 * Nicolas Pitre <nico@fluxnic.net>
14 * Andrew Christian <andrew.christian@hp.com>
15 *
16 * Converted to the RTC subsystem and Driver Model
17 * by Richard Purdie <rpurdie@rpsys.net>
18 */
19
20#include <linux/platform_device.h>
21#include <linux/module.h>
22#include <linux/clk.h>
23#include <linux/rtc.h>
24#include <linux/init.h>
25#include <linux/fs.h>
26#include <linux/interrupt.h>
27#include <linux/slab.h>
28#include <linux/string.h>
29#include <linux/of.h>
30#include <linux/pm.h>
31#include <linux/bitops.h>
32#include <linux/io.h>
33
34#define RTSR_HZE BIT(3) /* HZ interrupt enable */
35#define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */
36#define RTSR_HZ BIT(1) /* HZ rising-edge detected */
37#define RTSR_AL BIT(0) /* RTC alarm detected */
38
39#include "rtc-sa1100.h"
40
41#define RTC_DEF_DIVIDER (32768 - 1)
42#define RTC_DEF_TRIM 0
43#define RTC_FREQ 1024
44
45
46static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
47{
48 struct sa1100_rtc *info = dev_get_drvdata(dev_id);
49 struct rtc_device *rtc = info->rtc;
50 unsigned int rtsr;
51 unsigned long events = 0;
52
53 spin_lock(&info->lock);
54
55 rtsr = readl_relaxed(info->rtsr);
56 /* clear interrupt sources */
57 writel_relaxed(0, info->rtsr);
58 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
59 * See also the comments in sa1100_rtc_probe(). */
60 if (rtsr & (RTSR_ALE | RTSR_HZE)) {
61 /* This is the original code, before there was the if test
62 * above. This code does not clear interrupts that were not
63 * enabled. */
64 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
65 } else {
66 /* For some reason, it is possible to enter this routine
67 * without interruptions enabled, it has been tested with
68 * several units (Bug in SA11xx chip?).
69 *
70 * This situation leads to an infinite "loop" of interrupt
71 * routine calling and as a result the processor seems to
72 * lock on its first call to open(). */
73 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
74 }
75
76 /* clear alarm interrupt if it has occurred */
77 if (rtsr & RTSR_AL)
78 rtsr &= ~RTSR_ALE;
79 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
80
81 /* update irq data & counter */
82 if (rtsr & RTSR_AL)
83 events |= RTC_AF | RTC_IRQF;
84 if (rtsr & RTSR_HZ)
85 events |= RTC_UF | RTC_IRQF;
86
87 rtc_update_irq(rtc, 1, events);
88
89 spin_unlock(&info->lock);
90
91 return IRQ_HANDLED;
92}
93
94static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
95{
96 u32 rtsr;
97 struct sa1100_rtc *info = dev_get_drvdata(dev);
98
99 spin_lock_irq(&info->lock);
100 rtsr = readl_relaxed(info->rtsr);
101 if (enabled)
102 rtsr |= RTSR_ALE;
103 else
104 rtsr &= ~RTSR_ALE;
105 writel_relaxed(rtsr, info->rtsr);
106 spin_unlock_irq(&info->lock);
107 return 0;
108}
109
110static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
111{
112 struct sa1100_rtc *info = dev_get_drvdata(dev);
113
114 rtc_time64_to_tm(readl_relaxed(info->rcnr), tm);
115 return 0;
116}
117
118static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
119{
120 struct sa1100_rtc *info = dev_get_drvdata(dev);
121
122 writel_relaxed(rtc_tm_to_time64(tm), info->rcnr);
123
124 return 0;
125}
126
127static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
128{
129 u32 rtsr;
130 struct sa1100_rtc *info = dev_get_drvdata(dev);
131
132 rtsr = readl_relaxed(info->rtsr);
133 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
134 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
135 return 0;
136}
137
138static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
139{
140 struct sa1100_rtc *info = dev_get_drvdata(dev);
141
142 spin_lock_irq(&info->lock);
143 writel_relaxed(readl_relaxed(info->rtsr) &
144 (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr);
145 writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar);
146 if (alrm->enabled)
147 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
148 else
149 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
150 spin_unlock_irq(&info->lock);
151
152 return 0;
153}
154
155static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
156{
157 struct sa1100_rtc *info = dev_get_drvdata(dev);
158
159 seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr));
160 seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr));
161
162 return 0;
163}
164
165static const struct rtc_class_ops sa1100_rtc_ops = {
166 .read_time = sa1100_rtc_read_time,
167 .set_time = sa1100_rtc_set_time,
168 .read_alarm = sa1100_rtc_read_alarm,
169 .set_alarm = sa1100_rtc_set_alarm,
170 .proc = sa1100_rtc_proc,
171 .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
172};
173
174int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info)
175{
176 int ret;
177
178 spin_lock_init(&info->lock);
179
180 info->clk = devm_clk_get(&pdev->dev, NULL);
181 if (IS_ERR(info->clk)) {
182 dev_err(&pdev->dev, "failed to find rtc clock source\n");
183 return PTR_ERR(info->clk);
184 }
185
186 ret = clk_prepare_enable(info->clk);
187 if (ret)
188 return ret;
189 /*
190 * According to the manual we should be able to let RTTR be zero
191 * and then a default diviser for a 32.768KHz clock is used.
192 * Apparently this doesn't work, at least for my SA1110 rev 5.
193 * If the clock divider is uninitialized then reset it to the
194 * default value to get the 1Hz clock.
195 */
196 if (readl_relaxed(info->rttr) == 0) {
197 writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
198 dev_warn(&pdev->dev, "warning: "
199 "initializing default clock divider/trim value\n");
200 /* The current RTC value probably doesn't make sense either */
201 writel_relaxed(0, info->rcnr);
202 }
203
204 info->rtc->ops = &sa1100_rtc_ops;
205 info->rtc->max_user_freq = RTC_FREQ;
206 info->rtc->range_max = U32_MAX;
207
208 ret = devm_rtc_register_device(info->rtc);
209 if (ret) {
210 clk_disable_unprepare(info->clk);
211 return ret;
212 }
213
214 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
215 * See also the comments in sa1100_rtc_interrupt().
216 *
217 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
218 * interrupt pending, even though interrupts were never enabled.
219 * In this case, this bit it must be reset before enabling
220 * interruptions to avoid a nonexistent interrupt to occur.
221 *
222 * In principle, the same problem would apply to bit 0, although it has
223 * never been observed to happen.
224 *
225 * This issue is addressed both here and in sa1100_rtc_interrupt().
226 * If the issue is not addressed here, in the times when the processor
227 * wakes up with the bit set there will be one spurious interrupt.
228 *
229 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
230 * safe side, once the condition that lead to this strange
231 * initialization is unknown and could in principle happen during
232 * normal processing.
233 *
234 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
235 * the corresponding bits in RTSR. */
236 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
237
238 return 0;
239}
240EXPORT_SYMBOL_GPL(sa1100_rtc_init);
241
242static int sa1100_rtc_probe(struct platform_device *pdev)
243{
244 struct sa1100_rtc *info;
245 void __iomem *base;
246 int irq_1hz, irq_alarm;
247 int ret;
248
249 irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
250 irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
251 if (irq_1hz < 0 || irq_alarm < 0)
252 return -ENODEV;
253
254 info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL);
255 if (!info)
256 return -ENOMEM;
257 info->irq_1hz = irq_1hz;
258 info->irq_alarm = irq_alarm;
259
260 info->rtc = devm_rtc_allocate_device(&pdev->dev);
261 if (IS_ERR(info->rtc))
262 return PTR_ERR(info->rtc);
263
264 ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0,
265 "rtc 1Hz", &pdev->dev);
266 if (ret) {
267 dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz);
268 return ret;
269 }
270 ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0,
271 "rtc Alrm", &pdev->dev);
272 if (ret) {
273 dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm);
274 return ret;
275 }
276
277 base = devm_platform_ioremap_resource(pdev, 0);
278 if (IS_ERR(base))
279 return PTR_ERR(base);
280
281 if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
282 of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
283 info->rcnr = base + 0x04;
284 info->rtsr = base + 0x10;
285 info->rtar = base + 0x00;
286 info->rttr = base + 0x08;
287 } else {
288 info->rcnr = base + 0x0;
289 info->rtsr = base + 0x8;
290 info->rtar = base + 0x4;
291 info->rttr = base + 0xc;
292 }
293
294 platform_set_drvdata(pdev, info);
295 device_init_wakeup(&pdev->dev, 1);
296
297 return sa1100_rtc_init(pdev, info);
298}
299
300static void sa1100_rtc_remove(struct platform_device *pdev)
301{
302 struct sa1100_rtc *info = platform_get_drvdata(pdev);
303
304 if (info) {
305 spin_lock_irq(&info->lock);
306 writel_relaxed(0, info->rtsr);
307 spin_unlock_irq(&info->lock);
308 clk_disable_unprepare(info->clk);
309 }
310}
311
312#ifdef CONFIG_PM_SLEEP
313static int sa1100_rtc_suspend(struct device *dev)
314{
315 struct sa1100_rtc *info = dev_get_drvdata(dev);
316 if (device_may_wakeup(dev))
317 enable_irq_wake(info->irq_alarm);
318 return 0;
319}
320
321static int sa1100_rtc_resume(struct device *dev)
322{
323 struct sa1100_rtc *info = dev_get_drvdata(dev);
324 if (device_may_wakeup(dev))
325 disable_irq_wake(info->irq_alarm);
326 return 0;
327}
328#endif
329
330static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend,
331 sa1100_rtc_resume);
332
333#ifdef CONFIG_OF
334static const struct of_device_id sa1100_rtc_dt_ids[] = {
335 { .compatible = "mrvl,sa1100-rtc", },
336 { .compatible = "mrvl,mmp-rtc", },
337 {}
338};
339MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
340#endif
341
342static struct platform_driver sa1100_rtc_driver = {
343 .probe = sa1100_rtc_probe,
344 .remove = sa1100_rtc_remove,
345 .driver = {
346 .name = "sa1100-rtc",
347 .pm = &sa1100_rtc_pm_ops,
348 .of_match_table = of_match_ptr(sa1100_rtc_dt_ids),
349 },
350};
351
352module_platform_driver(sa1100_rtc_driver);
353
354MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
355MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
356MODULE_LICENSE("GPL");
357MODULE_ALIAS("platform:sa1100-rtc");
1/*
2 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
3 *
4 * Copyright (c) 2000 Nils Faerber
5 *
6 * Based on rtc.c by Paul Gortmaker
7 *
8 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
9 *
10 * Modifications from:
11 * CIH <cih@coventive.com>
12 * Nicolas Pitre <nico@fluxnic.net>
13 * Andrew Christian <andrew.christian@hp.com>
14 *
15 * Converted to the RTC subsystem and Driver Model
16 * by Richard Purdie <rpurdie@rpsys.net>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24#include <linux/platform_device.h>
25#include <linux/module.h>
26#include <linux/rtc.h>
27#include <linux/init.h>
28#include <linux/fs.h>
29#include <linux/interrupt.h>
30#include <linux/string.h>
31#include <linux/pm.h>
32#include <linux/bitops.h>
33
34#include <mach/hardware.h>
35#include <asm/irq.h>
36
37#ifdef CONFIG_ARCH_PXA
38#include <mach/regs-rtc.h>
39#include <mach/regs-ost.h>
40#endif
41
42#define RTC_DEF_DIVIDER (32768 - 1)
43#define RTC_DEF_TRIM 0
44
45static const unsigned long RTC_FREQ = 1024;
46static struct rtc_time rtc_alarm;
47static DEFINE_SPINLOCK(sa1100_rtc_lock);
48
49static inline int rtc_periodic_alarm(struct rtc_time *tm)
50{
51 return (tm->tm_year == -1) ||
52 ((unsigned)tm->tm_mon >= 12) ||
53 ((unsigned)(tm->tm_mday - 1) >= 31) ||
54 ((unsigned)tm->tm_hour > 23) ||
55 ((unsigned)tm->tm_min > 59) ||
56 ((unsigned)tm->tm_sec > 59);
57}
58
59/*
60 * Calculate the next alarm time given the requested alarm time mask
61 * and the current time.
62 */
63static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now,
64 struct rtc_time *alrm)
65{
66 unsigned long next_time;
67 unsigned long now_time;
68
69 next->tm_year = now->tm_year;
70 next->tm_mon = now->tm_mon;
71 next->tm_mday = now->tm_mday;
72 next->tm_hour = alrm->tm_hour;
73 next->tm_min = alrm->tm_min;
74 next->tm_sec = alrm->tm_sec;
75
76 rtc_tm_to_time(now, &now_time);
77 rtc_tm_to_time(next, &next_time);
78
79 if (next_time < now_time) {
80 /* Advance one day */
81 next_time += 60 * 60 * 24;
82 rtc_time_to_tm(next_time, next);
83 }
84}
85
86static int rtc_update_alarm(struct rtc_time *alrm)
87{
88 struct rtc_time alarm_tm, now_tm;
89 unsigned long now, time;
90 int ret;
91
92 do {
93 now = RCNR;
94 rtc_time_to_tm(now, &now_tm);
95 rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
96 ret = rtc_tm_to_time(&alarm_tm, &time);
97 if (ret != 0)
98 break;
99
100 RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
101 RTAR = time;
102 } while (now != RCNR);
103
104 return ret;
105}
106
107static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
108{
109 struct platform_device *pdev = to_platform_device(dev_id);
110 struct rtc_device *rtc = platform_get_drvdata(pdev);
111 unsigned int rtsr;
112 unsigned long events = 0;
113
114 spin_lock(&sa1100_rtc_lock);
115
116 rtsr = RTSR;
117 /* clear interrupt sources */
118 RTSR = 0;
119 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
120 * See also the comments in sa1100_rtc_probe(). */
121 if (rtsr & (RTSR_ALE | RTSR_HZE)) {
122 /* This is the original code, before there was the if test
123 * above. This code does not clear interrupts that were not
124 * enabled. */
125 RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2);
126 } else {
127 /* For some reason, it is possible to enter this routine
128 * without interruptions enabled, it has been tested with
129 * several units (Bug in SA11xx chip?).
130 *
131 * This situation leads to an infinite "loop" of interrupt
132 * routine calling and as a result the processor seems to
133 * lock on its first call to open(). */
134 RTSR = RTSR_AL | RTSR_HZ;
135 }
136
137 /* clear alarm interrupt if it has occurred */
138 if (rtsr & RTSR_AL)
139 rtsr &= ~RTSR_ALE;
140 RTSR = rtsr & (RTSR_ALE | RTSR_HZE);
141
142 /* update irq data & counter */
143 if (rtsr & RTSR_AL)
144 events |= RTC_AF | RTC_IRQF;
145 if (rtsr & RTSR_HZ)
146 events |= RTC_UF | RTC_IRQF;
147
148 rtc_update_irq(rtc, 1, events);
149
150 if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
151 rtc_update_alarm(&rtc_alarm);
152
153 spin_unlock(&sa1100_rtc_lock);
154
155 return IRQ_HANDLED;
156}
157
158static int sa1100_rtc_open(struct device *dev)
159{
160 int ret;
161 struct platform_device *plat_dev = to_platform_device(dev);
162 struct rtc_device *rtc = platform_get_drvdata(plat_dev);
163
164 ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
165 "rtc 1Hz", dev);
166 if (ret) {
167 dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
168 goto fail_ui;
169 }
170 ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
171 "rtc Alrm", dev);
172 if (ret) {
173 dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
174 goto fail_ai;
175 }
176 rtc->max_user_freq = RTC_FREQ;
177 rtc_irq_set_freq(rtc, NULL, RTC_FREQ);
178
179 return 0;
180
181 fail_ai:
182 free_irq(IRQ_RTC1Hz, dev);
183 fail_ui:
184 return ret;
185}
186
187static void sa1100_rtc_release(struct device *dev)
188{
189 spin_lock_irq(&sa1100_rtc_lock);
190 RTSR = 0;
191 OIER &= ~OIER_E1;
192 OSSR = OSSR_M1;
193 spin_unlock_irq(&sa1100_rtc_lock);
194
195 free_irq(IRQ_RTCAlrm, dev);
196 free_irq(IRQ_RTC1Hz, dev);
197}
198
199static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
200{
201 spin_lock_irq(&sa1100_rtc_lock);
202 if (enabled)
203 RTSR |= RTSR_ALE;
204 else
205 RTSR &= ~RTSR_ALE;
206 spin_unlock_irq(&sa1100_rtc_lock);
207 return 0;
208}
209
210static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
211{
212 rtc_time_to_tm(RCNR, tm);
213 return 0;
214}
215
216static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
217{
218 unsigned long time;
219 int ret;
220
221 ret = rtc_tm_to_time(tm, &time);
222 if (ret == 0)
223 RCNR = time;
224 return ret;
225}
226
227static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
228{
229 u32 rtsr;
230
231 memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
232 rtsr = RTSR;
233 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
234 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
235 return 0;
236}
237
238static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
239{
240 int ret;
241
242 spin_lock_irq(&sa1100_rtc_lock);
243 ret = rtc_update_alarm(&alrm->time);
244 if (ret == 0) {
245 if (alrm->enabled)
246 RTSR |= RTSR_ALE;
247 else
248 RTSR &= ~RTSR_ALE;
249 }
250 spin_unlock_irq(&sa1100_rtc_lock);
251
252 return ret;
253}
254
255static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
256{
257 seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR);
258 seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR);
259
260 return 0;
261}
262
263static const struct rtc_class_ops sa1100_rtc_ops = {
264 .open = sa1100_rtc_open,
265 .release = sa1100_rtc_release,
266 .read_time = sa1100_rtc_read_time,
267 .set_time = sa1100_rtc_set_time,
268 .read_alarm = sa1100_rtc_read_alarm,
269 .set_alarm = sa1100_rtc_set_alarm,
270 .proc = sa1100_rtc_proc,
271 .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
272};
273
274static int sa1100_rtc_probe(struct platform_device *pdev)
275{
276 struct rtc_device *rtc;
277
278 /*
279 * According to the manual we should be able to let RTTR be zero
280 * and then a default diviser for a 32.768KHz clock is used.
281 * Apparently this doesn't work, at least for my SA1110 rev 5.
282 * If the clock divider is uninitialized then reset it to the
283 * default value to get the 1Hz clock.
284 */
285 if (RTTR == 0) {
286 RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
287 dev_warn(&pdev->dev, "warning: "
288 "initializing default clock divider/trim value\n");
289 /* The current RTC value probably doesn't make sense either */
290 RCNR = 0;
291 }
292
293 device_init_wakeup(&pdev->dev, 1);
294
295 rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
296 THIS_MODULE);
297
298 if (IS_ERR(rtc))
299 return PTR_ERR(rtc);
300
301 platform_set_drvdata(pdev, rtc);
302
303 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
304 * See also the comments in sa1100_rtc_interrupt().
305 *
306 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
307 * interrupt pending, even though interrupts were never enabled.
308 * In this case, this bit it must be reset before enabling
309 * interruptions to avoid a nonexistent interrupt to occur.
310 *
311 * In principle, the same problem would apply to bit 0, although it has
312 * never been observed to happen.
313 *
314 * This issue is addressed both here and in sa1100_rtc_interrupt().
315 * If the issue is not addressed here, in the times when the processor
316 * wakes up with the bit set there will be one spurious interrupt.
317 *
318 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
319 * safe side, once the condition that lead to this strange
320 * initialization is unknown and could in principle happen during
321 * normal processing.
322 *
323 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
324 * the corresponding bits in RTSR. */
325 RTSR = RTSR_AL | RTSR_HZ;
326
327 return 0;
328}
329
330static int sa1100_rtc_remove(struct platform_device *pdev)
331{
332 struct rtc_device *rtc = platform_get_drvdata(pdev);
333
334 if (rtc)
335 rtc_device_unregister(rtc);
336
337 return 0;
338}
339
340#ifdef CONFIG_PM
341static int sa1100_rtc_suspend(struct device *dev)
342{
343 if (device_may_wakeup(dev))
344 enable_irq_wake(IRQ_RTCAlrm);
345 return 0;
346}
347
348static int sa1100_rtc_resume(struct device *dev)
349{
350 if (device_may_wakeup(dev))
351 disable_irq_wake(IRQ_RTCAlrm);
352 return 0;
353}
354
355static const struct dev_pm_ops sa1100_rtc_pm_ops = {
356 .suspend = sa1100_rtc_suspend,
357 .resume = sa1100_rtc_resume,
358};
359#endif
360
361static struct platform_driver sa1100_rtc_driver = {
362 .probe = sa1100_rtc_probe,
363 .remove = sa1100_rtc_remove,
364 .driver = {
365 .name = "sa1100-rtc",
366#ifdef CONFIG_PM
367 .pm = &sa1100_rtc_pm_ops,
368#endif
369 },
370};
371
372static int __init sa1100_rtc_init(void)
373{
374 return platform_driver_register(&sa1100_rtc_driver);
375}
376
377static void __exit sa1100_rtc_exit(void)
378{
379 platform_driver_unregister(&sa1100_rtc_driver);
380}
381
382module_init(sa1100_rtc_init);
383module_exit(sa1100_rtc_exit);
384
385MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
386MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
387MODULE_LICENSE("GPL");
388MODULE_ALIAS("platform:sa1100-rtc");