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1/* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Up to 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444*/
445
446#include <linux/module.h>
447#include <linux/kernel.h>
448#include <linux/string.h>
449#include <linux/interrupt.h>
450#include <linux/ptrace.h>
451#include <linux/errno.h>
452#include <linux/ioport.h>
453#include <linux/pci.h>
454#include <linux/eisa.h>
455#include <linux/delay.h>
456#include <linux/init.h>
457#include <linux/spinlock.h>
458#include <linux/crc32.h>
459#include <linux/netdevice.h>
460#include <linux/etherdevice.h>
461#include <linux/skbuff.h>
462#include <linux/time.h>
463#include <linux/types.h>
464#include <linux/unistd.h>
465#include <linux/ctype.h>
466#include <linux/dma-mapping.h>
467#include <linux/moduleparam.h>
468#include <linux/bitops.h>
469#include <linux/gfp.h>
470
471#include <asm/io.h>
472#include <asm/dma.h>
473#include <asm/byteorder.h>
474#include <asm/unaligned.h>
475#include <asm/uaccess.h>
476#ifdef CONFIG_PPC_PMAC
477#include <asm/machdep.h>
478#endif /* CONFIG_PPC_PMAC */
479
480#include "de4x5.h"
481
482static const char version[] __devinitconst =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484
485#define c_char const char
486
487/*
488** MII Information
489*/
490struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499};
500
501struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518};
519
520#define DE4X5_MAX_PHY 8 /* Allow up to 8 attached PHY devices per board */
521
522struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530};
531
532/*
533** Define the know universe of PHY devices that can be
534** recognised by this driver.
535*/
536static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542};
543
544/*
545** These GENERIC values assumes that the PHY devices follow 802.3u and
546** allow parallel detection to set the link partner ability register.
547** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548*/
549#define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550#define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553/*
554** Define special SROM detection cases
555*/
556static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559};
560
561#define SMC 1
562#define ACCTON 2
563
564/*
565** SROM Repair definitions. If a broken SROM is detected a card may
566** use this information to help figure out what to do. This is a
567** "stab in the dark" and so far for SMC9332's only.
568*/
569static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574};
575
576
577#ifdef DE4X5_DEBUG
578static int de4x5_debug = DE4X5_DEBUG;
579#else
580/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582#endif
583
584/*
585** Allow per adapter set up. For modules this is simply a command line
586** parameter, e.g.:
587** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588**
589** For a compiled in driver, place e.g.
590** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591** here
592*/
593#ifdef DE4X5_PARM
594static char *args = DE4X5_PARM;
595#else
596static char *args;
597#endif
598
599struct parameters {
600 bool fdx;
601 int autosense;
602};
603
604#define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606#define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608/*
609** Ethernet PROM defines
610*/
611#define PROBE_LENGTH 32
612#define ETH_PROM_SIG 0xAA5500FFUL
613
614/*
615** Ethernet Info
616*/
617#define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618#define IEEE802_3_SZ 1518 /* Packet + CRC */
619#define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620#define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621#define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622#define PKT_HDR_LEN 14 /* Addresses and data length info */
623#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624#define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627/*
628** EISA bus defines
629*/
630#define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631#define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636#define DE4X5_NAME_LENGTH 8
637
638static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640/*
641** Ethernet PROM defines for DC21040
642*/
643#define PROBE_LENGTH 32
644#define ETH_PROM_SIG 0xAA5500FFUL
645
646/*
647** PCI Bus defines
648*/
649#define PCI_MAX_BUS_NUM 8
650#define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651#define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653/*
654** Memory Alignment. Each descriptor is 4 longwords long. To force a
655** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657** and hence the RX descriptor ring's first entry.
658*/
659#define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660#define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661#define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662#define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663#define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664#define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666#define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667#define DE4X5_CACHE_ALIGN CAL_16LONG
668#define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669/*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670#define DESC_ALIGN
671
672#ifndef DEC_ONLY /* See README.de4x5 for using this */
673static int dec_only;
674#else
675static int dec_only = 1;
676#endif
677
678/*
679** DE4X5 IRQ ENABLE/DISABLE
680*/
681#define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684}
685
686#define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690}
691
692#define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695}
696
697#define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701}
702
703/*
704** DE4X5 START/STOP
705*/
706#define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710}
711
712#define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716}
717
718/*
719** DE4X5 SIA RESET
720*/
721#define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723/*
724** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725*/
726#define DE4X5_AUTOSENSE_MS 250
727
728/*
729** SROM Structure
730*/
731struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742};
743#define SUB_VENDOR_ID 0x500a
744
745/*
746** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747** and have sizes of both a power of 2 and a multiple of 4.
748** A size of 256 bytes for each buffer could be chosen because over 90% of
749** all packets in our network are <256 bytes long and 64 longword alignment
750** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751** descriptors are needed for machines with an ALPHA CPU.
752*/
753#define NUM_RX_DESC 8 /* Number of RX descriptors */
754#define NUM_TX_DESC 32 /* Number of TX descriptors */
755#define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758struct de4x5_desc {
759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
763 DESC_ALIGN
764};
765
766/*
767** The DE4X5 private structure
768*/
769#define DE4X5_PKT_STAT_SZ 16
770#define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785};
786
787struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860};
861
862/*
863** To get around certain poxy cards that don't provide an SROM
864** for the second and more DECchip, I have to key off the first
865** chip's address. I'll assume there's not a bad SROM iff:
866**
867** o the chipset is the same
868** o the bus number is the same and > 0
869** o the sum of all the returned hw address bytes is 0 or 0x5fa
870**
871** Also have to save the irq for those cards whose hardware designers
872** can't follow the PCI to PCI Bridge Architecture spec.
873*/
874static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879} last = {0,};
880
881/*
882** The transmit ring full condition is described by the tx_old and tx_new
883** pointers by:
884** tx_old = tx_new Empty ring
885** tx_old = tx_new+1 Full ring
886** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887*/
888#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894/*
895** Public Functions
896*/
897static int de4x5_open(struct net_device *dev);
898static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
900static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901static int de4x5_close(struct net_device *dev);
902static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904static void set_multicast_list(struct net_device *dev);
905static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907/*
908** Private functions
909*/
910static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911static int de4x5_init(struct net_device *dev);
912static int de4x5_sw_reset(struct net_device *dev);
913static int de4x5_rx(struct net_device *dev);
914static int de4x5_tx(struct net_device *dev);
915static void de4x5_ast(struct net_device *dev);
916static int de4x5_txur(struct net_device *dev);
917static int de4x5_rx_ovfc(struct net_device *dev);
918
919static int autoconf_media(struct net_device *dev);
920static void create_packet(struct net_device *dev, char *frame, int len);
921static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922static int dc21040_autoconf(struct net_device *dev);
923static int dc21041_autoconf(struct net_device *dev);
924static int dc21140m_autoconf(struct net_device *dev);
925static int dc2114x_autoconf(struct net_device *dev);
926static int srom_autoconf(struct net_device *dev);
927static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930static int test_for_100Mb(struct net_device *dev, int msec);
931static int wait_for_link(struct net_device *dev);
932static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933static int is_spd_100(struct net_device *dev);
934static int is_100_up(struct net_device *dev);
935static int is_10_up(struct net_device *dev);
936static int is_anc_capable(struct net_device *dev);
937static int ping_media(struct net_device *dev, int msec);
938static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939static void de4x5_free_rx_buffs(struct net_device *dev);
940static void de4x5_free_tx_buffs(struct net_device *dev);
941static void de4x5_save_skbs(struct net_device *dev);
942static void de4x5_rst_desc_ring(struct net_device *dev);
943static void de4x5_cache_state(struct net_device *dev, int flag);
944static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947static void de4x5_setup_intr(struct net_device *dev);
948static void de4x5_init_connection(struct net_device *dev);
949static int de4x5_reset_phy(struct net_device *dev);
950static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952static int test_tp(struct net_device *dev, s32 msec);
953static int EISA_signature(char *name, struct device *device);
954static int PCI_signature(char *name, struct de4x5_private *lp);
955static void DevicePresent(struct net_device *dev, u_long iobase);
956static void enet_addr_rst(u_long aprom_addr);
957static int de4x5_bad_srom(struct de4x5_private *lp);
958static short srom_rd(u_long address, u_char offset);
959static void srom_latch(u_int command, u_long address);
960static void srom_command(u_int command, u_long address);
961static void srom_address(u_int command, u_long address, u_char offset);
962static short srom_data(u_int command, u_long address);
963/*static void srom_busy(u_int command, u_long address);*/
964static void sendto_srom(u_int command, u_long addr);
965static int getfrom_srom(u_long addr);
966static int srom_map_media(struct net_device *dev);
967static int srom_infoleaf_info(struct net_device *dev);
968static void srom_init(struct net_device *dev);
969static void srom_exec(struct net_device *dev, u_char *p);
970static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972static int mii_rdata(u_long ioaddr);
973static void mii_wdata(int data, int len, u_long ioaddr);
974static void mii_ta(u_long rw, u_long ioaddr);
975static int mii_swap(int data, int len);
976static void mii_address(u_char addr, u_long ioaddr);
977static void sendto_mii(u32 command, int data, u_long ioaddr);
978static int getfrom_mii(u32 command, u_long ioaddr);
979static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980static int mii_get_phy(struct net_device *dev);
981static void SetMulticastFilter(struct net_device *dev);
982static int get_hw_addr(struct net_device *dev);
983static void srom_repair(struct net_device *dev, int card);
984static int test_bad_enet(struct net_device *dev, int status);
985static int an_exception(struct de4x5_private *lp);
986static char *build_setup_frame(struct net_device *dev, int mode);
987static void disable_ast(struct net_device *dev);
988static long de4x5_switch_mac_port(struct net_device *dev);
989static int gep_rd(struct net_device *dev);
990static void gep_wr(s32 data, struct net_device *dev);
991static void yawn(struct net_device *dev, int state);
992static void de4x5_parse_params(struct net_device *dev);
993static void de4x5_dbg_open(struct net_device *dev);
994static void de4x5_dbg_mii(struct net_device *dev, int k);
995static void de4x5_dbg_media(struct net_device *dev);
996static void de4x5_dbg_srom(struct de4x5_srom *p);
997static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998static int de4x5_strncmp(char *a, char *b, int n);
999static int dc21041_infoleaf(struct net_device *dev);
1000static int dc21140_infoleaf(struct net_device *dev);
1001static int dc21142_infoleaf(struct net_device *dev);
1002static int dc21143_infoleaf(struct net_device *dev);
1003static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1004static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1005static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1010
1011/*
1012** Note now that module autoprobing is allowed under EISA and PCI. The
1013** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1014** to "do the right thing".
1015*/
1016
1017static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1018
1019module_param(io, int, 0);
1020module_param(de4x5_debug, int, 0);
1021module_param(dec_only, int, 0);
1022module_param(args, charp, 0);
1023
1024MODULE_PARM_DESC(io, "de4x5 I/O base address");
1025MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1026MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1027MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028MODULE_LICENSE("GPL");
1029
1030/*
1031** List the SROM infoleaf functions and chipsets
1032*/
1033struct InfoLeaf {
1034 int chipset;
1035 int (*fn)(struct net_device *);
1036};
1037static struct InfoLeaf infoleaf_array[] = {
1038 {DC21041, dc21041_infoleaf},
1039 {DC21140, dc21140_infoleaf},
1040 {DC21142, dc21142_infoleaf},
1041 {DC21143, dc21143_infoleaf}
1042};
1043#define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1044
1045/*
1046** List the SROM info block functions
1047*/
1048static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1049 type0_infoblock,
1050 type1_infoblock,
1051 type2_infoblock,
1052 type3_infoblock,
1053 type4_infoblock,
1054 type5_infoblock,
1055 compact_infoblock
1056};
1057
1058#define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1059
1060/*
1061** Miscellaneous defines...
1062*/
1063#define RESET_DE4X5 {\
1064 int i;\
1065 i=inl(DE4X5_BMR);\
1066 mdelay(1);\
1067 outl(i | BMR_SWR, DE4X5_BMR);\
1068 mdelay(1);\
1069 outl(i, DE4X5_BMR);\
1070 mdelay(1);\
1071 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1072 mdelay(1);\
1073}
1074
1075#define PHY_HARD_RESET {\
1076 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1077 mdelay(1); /* Assert for 1ms */\
1078 outl(0x00, DE4X5_GEP);\
1079 mdelay(2); /* Wait for 2ms */\
1080}
1081
1082static const struct net_device_ops de4x5_netdev_ops = {
1083 .ndo_open = de4x5_open,
1084 .ndo_stop = de4x5_close,
1085 .ndo_start_xmit = de4x5_queue_pkt,
1086 .ndo_get_stats = de4x5_get_stats,
1087 .ndo_set_multicast_list = set_multicast_list,
1088 .ndo_do_ioctl = de4x5_ioctl,
1089 .ndo_change_mtu = eth_change_mtu,
1090 .ndo_set_mac_address= eth_mac_addr,
1091 .ndo_validate_addr = eth_validate_addr,
1092};
1093
1094
1095static int __devinit
1096de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1097{
1098 char name[DE4X5_NAME_LENGTH + 1];
1099 struct de4x5_private *lp = netdev_priv(dev);
1100 struct pci_dev *pdev = NULL;
1101 int i, status=0;
1102
1103 dev_set_drvdata(gendev, dev);
1104
1105 /* Ensure we're not sleeping */
1106 if (lp->bus == EISA) {
1107 outb(WAKEUP, PCI_CFPM);
1108 } else {
1109 pdev = to_pci_dev (gendev);
1110 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1111 }
1112 mdelay(10);
1113
1114 RESET_DE4X5;
1115
1116 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1117 return -ENXIO; /* Hardware could not reset */
1118 }
1119
1120 /*
1121 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1122 */
1123 lp->useSROM = false;
1124 if (lp->bus == PCI) {
1125 PCI_signature(name, lp);
1126 } else {
1127 EISA_signature(name, gendev);
1128 }
1129
1130 if (*name == '\0') { /* Not found a board signature */
1131 return -ENXIO;
1132 }
1133
1134 dev->base_addr = iobase;
1135 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1136
1137 status = get_hw_addr(dev);
1138 printk(", h/w address %pM\n", dev->dev_addr);
1139
1140 if (status != 0) {
1141 printk(" which has an Ethernet PROM CRC error.\n");
1142 return -ENXIO;
1143 } else {
1144 skb_queue_head_init(&lp->cache.queue);
1145 lp->cache.gepc = GEP_INIT;
1146 lp->asBit = GEP_SLNK;
1147 lp->asPolarity = GEP_SLNK;
1148 lp->asBitValid = ~0;
1149 lp->timeout = -1;
1150 lp->gendev = gendev;
1151 spin_lock_init(&lp->lock);
1152 init_timer(&lp->timer);
1153 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154 lp->timer.data = (unsigned long)dev;
1155 de4x5_parse_params(dev);
1156
1157 /*
1158 ** Choose correct autosensing in case someone messed up
1159 */
1160 lp->autosense = lp->params.autosense;
1161 if (lp->chipset != DC21140) {
1162 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163 lp->params.autosense = TP;
1164 }
1165 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166 lp->params.autosense = BNC;
1167 }
1168 }
1169 lp->fdx = lp->params.fdx;
1170 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1171
1172 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1173#if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1174 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1175#endif
1176 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1177 &lp->dma_rings, GFP_ATOMIC);
1178 if (lp->rx_ring == NULL) {
1179 return -ENOMEM;
1180 }
1181
1182 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1183
1184 /*
1185 ** Set up the RX descriptor ring (Intels)
1186 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1187 */
1188#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1189 for (i=0; i<NUM_RX_DESC; i++) {
1190 lp->rx_ring[i].status = 0;
1191 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1192 lp->rx_ring[i].buf = 0;
1193 lp->rx_ring[i].next = 0;
1194 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1195 }
1196
1197#else
1198 {
1199 dma_addr_t dma_rx_bufs;
1200
1201 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1202 * sizeof(struct de4x5_desc);
1203 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1204 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1205 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1206 for (i=0; i<NUM_RX_DESC; i++) {
1207 lp->rx_ring[i].status = 0;
1208 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1209 lp->rx_ring[i].buf =
1210 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1211 lp->rx_ring[i].next = 0;
1212 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1213 }
1214
1215 }
1216#endif
1217
1218 barrier();
1219
1220 lp->rxRingSize = NUM_RX_DESC;
1221 lp->txRingSize = NUM_TX_DESC;
1222
1223 /* Write the end of list marker to the descriptor lists */
1224 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1225 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1226
1227 /* Tell the adapter where the TX/RX rings are located. */
1228 outl(lp->dma_rings, DE4X5_RRBA);
1229 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1230 DE4X5_TRBA);
1231
1232 /* Initialise the IRQ mask and Enable/Disable */
1233 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1234 lp->irq_en = IMR_NIM | IMR_AIM;
1235
1236 /* Create a loopback packet frame for later media probing */
1237 create_packet(dev, lp->frame, sizeof(lp->frame));
1238
1239 /* Check if the RX overflow bug needs testing for */
1240 i = lp->cfrv & 0x000000fe;
1241 if ((lp->chipset == DC21140) && (i == 0x20)) {
1242 lp->rx_ovf = 1;
1243 }
1244
1245 /* Initialise the SROM pointers if possible */
1246 if (lp->useSROM) {
1247 lp->state = INITIALISED;
1248 if (srom_infoleaf_info(dev)) {
1249 dma_free_coherent (gendev, lp->dma_size,
1250 lp->rx_ring, lp->dma_rings);
1251 return -ENXIO;
1252 }
1253 srom_init(dev);
1254 }
1255
1256 lp->state = CLOSED;
1257
1258 /*
1259 ** Check for an MII interface
1260 */
1261 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1262 mii_get_phy(dev);
1263 }
1264
1265 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1266 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1267 }
1268
1269 if (de4x5_debug & DEBUG_VERSION) {
1270 printk(version);
1271 }
1272
1273 /* The DE4X5-specific entries in the device structure. */
1274 SET_NETDEV_DEV(dev, gendev);
1275 dev->netdev_ops = &de4x5_netdev_ops;
1276 dev->mem_start = 0;
1277
1278 /* Fill in the generic fields of the device structure. */
1279 if ((status = register_netdev (dev))) {
1280 dma_free_coherent (gendev, lp->dma_size,
1281 lp->rx_ring, lp->dma_rings);
1282 return status;
1283 }
1284
1285 /* Let the adapter sleep to save power */
1286 yawn(dev, SLEEP);
1287
1288 return status;
1289}
1290
1291
1292static int
1293de4x5_open(struct net_device *dev)
1294{
1295 struct de4x5_private *lp = netdev_priv(dev);
1296 u_long iobase = dev->base_addr;
1297 int i, status = 0;
1298 s32 omr;
1299
1300 /* Allocate the RX buffers */
1301 for (i=0; i<lp->rxRingSize; i++) {
1302 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1303 de4x5_free_rx_buffs(dev);
1304 return -EAGAIN;
1305 }
1306 }
1307
1308 /*
1309 ** Wake up the adapter
1310 */
1311 yawn(dev, WAKEUP);
1312
1313 /*
1314 ** Re-initialize the DE4X5...
1315 */
1316 status = de4x5_init(dev);
1317 spin_lock_init(&lp->lock);
1318 lp->state = OPEN;
1319 de4x5_dbg_open(dev);
1320
1321 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1322 lp->adapter_name, dev)) {
1323 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1324 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1325 lp->adapter_name, dev)) {
1326 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1327 disable_ast(dev);
1328 de4x5_free_rx_buffs(dev);
1329 de4x5_free_tx_buffs(dev);
1330 yawn(dev, SLEEP);
1331 lp->state = CLOSED;
1332 return -EAGAIN;
1333 } else {
1334 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1335 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1336 }
1337 }
1338
1339 lp->interrupt = UNMASK_INTERRUPTS;
1340 dev->trans_start = jiffies; /* prevent tx timeout */
1341
1342 START_DE4X5;
1343
1344 de4x5_setup_intr(dev);
1345
1346 if (de4x5_debug & DEBUG_OPEN) {
1347 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1348 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1349 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1350 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1351 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1352 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1353 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1354 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1355 }
1356
1357 return status;
1358}
1359
1360/*
1361** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1362** DC21140 requires using perfect filtering mode for that chip. Since I can't
1363** see why I'd want > 14 multicast addresses, I have changed all chips to use
1364** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1365** to be data corruption problems if it is larger (UDP errors seen from a
1366** ttcp source).
1367*/
1368static int
1369de4x5_init(struct net_device *dev)
1370{
1371 /* Lock out other processes whilst setting up the hardware */
1372 netif_stop_queue(dev);
1373
1374 de4x5_sw_reset(dev);
1375
1376 /* Autoconfigure the connected port */
1377 autoconf_media(dev);
1378
1379 return 0;
1380}
1381
1382static int
1383de4x5_sw_reset(struct net_device *dev)
1384{
1385 struct de4x5_private *lp = netdev_priv(dev);
1386 u_long iobase = dev->base_addr;
1387 int i, j, status = 0;
1388 s32 bmr, omr;
1389
1390 /* Select the MII or SRL port now and RESET the MAC */
1391 if (!lp->useSROM) {
1392 if (lp->phy[lp->active].id != 0) {
1393 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1394 } else {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1396 }
1397 de4x5_switch_mac_port(dev);
1398 }
1399
1400 /*
1401 ** Set the programmable burst length to 8 longwords for all the DC21140
1402 ** Fasternet chips and 4 longwords for all others: DMA errors result
1403 ** without these values. Cache align 16 long.
1404 */
1405 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1406 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1407 outl(bmr, DE4X5_BMR);
1408
1409 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1410 if (lp->chipset == DC21140) {
1411 omr |= (OMR_SDP | OMR_SB);
1412 }
1413 lp->setup_f = PERFECT;
1414 outl(lp->dma_rings, DE4X5_RRBA);
1415 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1416 DE4X5_TRBA);
1417
1418 lp->rx_new = lp->rx_old = 0;
1419 lp->tx_new = lp->tx_old = 0;
1420
1421 for (i = 0; i < lp->rxRingSize; i++) {
1422 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1423 }
1424
1425 for (i = 0; i < lp->txRingSize; i++) {
1426 lp->tx_ring[i].status = cpu_to_le32(0);
1427 }
1428
1429 barrier();
1430
1431 /* Build the setup frame depending on filtering mode */
1432 SetMulticastFilter(dev);
1433
1434 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1435 outl(omr|OMR_ST, DE4X5_OMR);
1436
1437 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1438
1439 for (j=0, i=0;(i<500) && (j==0);i++) { /* Up to 500ms delay */
1440 mdelay(1);
1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1442 }
1443 outl(omr, DE4X5_OMR); /* Stop everything! */
1444
1445 if (j == 0) {
1446 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1447 inl(DE4X5_STS));
1448 status = -EIO;
1449 }
1450
1451 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1452 lp->tx_old = lp->tx_new;
1453
1454 return status;
1455}
1456
1457/*
1458** Writes a socket buffer address to the next available transmit descriptor.
1459*/
1460static netdev_tx_t
1461de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1462{
1463 struct de4x5_private *lp = netdev_priv(dev);
1464 u_long iobase = dev->base_addr;
1465 u_long flags = 0;
1466
1467 netif_stop_queue(dev);
1468 if (!lp->tx_enable) /* Cannot send for now */
1469 return NETDEV_TX_LOCKED;
1470
1471 /*
1472 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1473 ** interrupts are lost by delayed descriptor status updates relative to
1474 ** the irq assertion, especially with a busy PCI bus.
1475 */
1476 spin_lock_irqsave(&lp->lock, flags);
1477 de4x5_tx(dev);
1478 spin_unlock_irqrestore(&lp->lock, flags);
1479
1480 /* Test if cache is already locked - requeue skb if so */
1481 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1482 return NETDEV_TX_LOCKED;
1483
1484 /* Transmit descriptor ring full or stale skb */
1485 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1486 if (lp->interrupt) {
1487 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1488 } else {
1489 de4x5_put_cache(dev, skb);
1490 }
1491 if (de4x5_debug & DEBUG_TX) {
1492 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1493 }
1494 } else if (skb->len > 0) {
1495 /* If we already have stuff queued locally, use that first */
1496 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1497 de4x5_put_cache(dev, skb);
1498 skb = de4x5_get_cache(dev);
1499 }
1500
1501 while (skb && !netif_queue_stopped(dev) &&
1502 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1503 spin_lock_irqsave(&lp->lock, flags);
1504 netif_stop_queue(dev);
1505 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1506 lp->stats.tx_bytes += skb->len;
1507 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1508
1509 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1510
1511 if (TX_BUFFS_AVAIL) {
1512 netif_start_queue(dev); /* Another pkt may be queued */
1513 }
1514 skb = de4x5_get_cache(dev);
1515 spin_unlock_irqrestore(&lp->lock, flags);
1516 }
1517 if (skb) de4x5_putb_cache(dev, skb);
1518 }
1519
1520 lp->cache.lock = 0;
1521
1522 return NETDEV_TX_OK;
1523}
1524
1525/*
1526** The DE4X5 interrupt handler.
1527**
1528** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1529** so that the asserted interrupt always has some real data to work with -
1530** if these I/O accesses are ever changed to memory accesses, ensure the
1531** STS write is read immediately to complete the transaction if the adapter
1532** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1533** is high and descriptor status bits cannot be set before the associated
1534** interrupt is asserted and this routine entered.
1535*/
1536static irqreturn_t
1537de4x5_interrupt(int irq, void *dev_id)
1538{
1539 struct net_device *dev = dev_id;
1540 struct de4x5_private *lp;
1541 s32 imr, omr, sts, limit;
1542 u_long iobase;
1543 unsigned int handled = 0;
1544
1545 lp = netdev_priv(dev);
1546 spin_lock(&lp->lock);
1547 iobase = dev->base_addr;
1548
1549 DISABLE_IRQs; /* Ensure non re-entrancy */
1550
1551 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1552 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1553
1554 synchronize_irq(dev->irq);
1555
1556 for (limit=0; limit<8; limit++) {
1557 sts = inl(DE4X5_STS); /* Read IRQ status */
1558 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1559
1560 if (!(sts & lp->irq_mask)) break;/* All done */
1561 handled = 1;
1562
1563 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1564 de4x5_rx(dev);
1565
1566 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1567 de4x5_tx(dev);
1568
1569 if (sts & STS_LNF) { /* TP Link has failed */
1570 lp->irq_mask &= ~IMR_LFM;
1571 }
1572
1573 if (sts & STS_UNF) { /* Transmit underrun */
1574 de4x5_txur(dev);
1575 }
1576
1577 if (sts & STS_SE) { /* Bus Error */
1578 STOP_DE4X5;
1579 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1580 dev->name, sts);
1581 spin_unlock(&lp->lock);
1582 return IRQ_HANDLED;
1583 }
1584 }
1585
1586 /* Load the TX ring with any locally stored packets */
1587 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1588 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1589 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1590 }
1591 lp->cache.lock = 0;
1592 }
1593
1594 lp->interrupt = UNMASK_INTERRUPTS;
1595 ENABLE_IRQs;
1596 spin_unlock(&lp->lock);
1597
1598 return IRQ_RETVAL(handled);
1599}
1600
1601static int
1602de4x5_rx(struct net_device *dev)
1603{
1604 struct de4x5_private *lp = netdev_priv(dev);
1605 u_long iobase = dev->base_addr;
1606 int entry;
1607 s32 status;
1608
1609 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1610 entry=lp->rx_new) {
1611 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1612
1613 if (lp->rx_ovf) {
1614 if (inl(DE4X5_MFC) & MFC_FOCM) {
1615 de4x5_rx_ovfc(dev);
1616 break;
1617 }
1618 }
1619
1620 if (status & RD_FS) { /* Remember the start of frame */
1621 lp->rx_old = entry;
1622 }
1623
1624 if (status & RD_LS) { /* Valid frame status */
1625 if (lp->tx_enable) lp->linkOK++;
1626 if (status & RD_ES) { /* There was an error. */
1627 lp->stats.rx_errors++; /* Update the error stats. */
1628 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1629 if (status & RD_CE) lp->stats.rx_crc_errors++;
1630 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1631 if (status & RD_TL) lp->stats.rx_length_errors++;
1632 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1633 if (status & RD_CS) lp->pktStats.rx_collision++;
1634 if (status & RD_DB) lp->pktStats.rx_dribble++;
1635 if (status & RD_OF) lp->pktStats.rx_overflow++;
1636 } else { /* A valid frame received */
1637 struct sk_buff *skb;
1638 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1639 >> 16) - 4;
1640
1641 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1642 printk("%s: Insufficient memory; nuking packet.\n",
1643 dev->name);
1644 lp->stats.rx_dropped++;
1645 } else {
1646 de4x5_dbg_rx(skb, pkt_len);
1647
1648 /* Push up the protocol stack */
1649 skb->protocol=eth_type_trans(skb,dev);
1650 de4x5_local_stats(dev, skb->data, pkt_len);
1651 netif_rx(skb);
1652
1653 /* Update stats */
1654 lp->stats.rx_packets++;
1655 lp->stats.rx_bytes += pkt_len;
1656 }
1657 }
1658
1659 /* Change buffer ownership for this frame, back to the adapter */
1660 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1661 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1662 barrier();
1663 }
1664 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1665 barrier();
1666 }
1667
1668 /*
1669 ** Update entry information
1670 */
1671 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1672 }
1673
1674 return 0;
1675}
1676
1677static inline void
1678de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1679{
1680 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1681 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1682 DMA_TO_DEVICE);
1683 if ((u_long) lp->tx_skb[entry] > 1)
1684 dev_kfree_skb_irq(lp->tx_skb[entry]);
1685 lp->tx_skb[entry] = NULL;
1686}
1687
1688/*
1689** Buffer sent - check for TX buffer errors.
1690*/
1691static int
1692de4x5_tx(struct net_device *dev)
1693{
1694 struct de4x5_private *lp = netdev_priv(dev);
1695 u_long iobase = dev->base_addr;
1696 int entry;
1697 s32 status;
1698
1699 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1700 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1701 if (status < 0) { /* Buffer not sent yet */
1702 break;
1703 } else if (status != 0x7fffffff) { /* Not setup frame */
1704 if (status & TD_ES) { /* An error happened */
1705 lp->stats.tx_errors++;
1706 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1707 if (status & TD_LC) lp->stats.tx_window_errors++;
1708 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1709 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1710 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1711
1712 if (TX_PKT_PENDING) {
1713 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1714 }
1715 } else { /* Packet sent */
1716 lp->stats.tx_packets++;
1717 if (lp->tx_enable) lp->linkOK++;
1718 }
1719 /* Update the collision counter */
1720 lp->stats.collisions += ((status & TD_EC) ? 16 :
1721 ((status & TD_CC) >> 3));
1722
1723 /* Free the buffer. */
1724 if (lp->tx_skb[entry] != NULL)
1725 de4x5_free_tx_buff(lp, entry);
1726 }
1727
1728 /* Update all the pointers */
1729 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1730 }
1731
1732 /* Any resources available? */
1733 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1734 if (lp->interrupt)
1735 netif_wake_queue(dev);
1736 else
1737 netif_start_queue(dev);
1738 }
1739
1740 return 0;
1741}
1742
1743static void
1744de4x5_ast(struct net_device *dev)
1745{
1746 struct de4x5_private *lp = netdev_priv(dev);
1747 int next_tick = DE4X5_AUTOSENSE_MS;
1748 int dt;
1749
1750 if (lp->useSROM)
1751 next_tick = srom_autoconf(dev);
1752 else if (lp->chipset == DC21140)
1753 next_tick = dc21140m_autoconf(dev);
1754 else if (lp->chipset == DC21041)
1755 next_tick = dc21041_autoconf(dev);
1756 else if (lp->chipset == DC21040)
1757 next_tick = dc21040_autoconf(dev);
1758 lp->linkOK = 0;
1759
1760 dt = (next_tick * HZ) / 1000;
1761
1762 if (!dt)
1763 dt = 1;
1764
1765 mod_timer(&lp->timer, jiffies + dt);
1766}
1767
1768static int
1769de4x5_txur(struct net_device *dev)
1770{
1771 struct de4x5_private *lp = netdev_priv(dev);
1772 u_long iobase = dev->base_addr;
1773 int omr;
1774
1775 omr = inl(DE4X5_OMR);
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1777 omr &= ~(OMR_ST|OMR_SR);
1778 outl(omr, DE4X5_OMR);
1779 while (inl(DE4X5_STS) & STS_TS);
1780 if ((omr & OMR_TR) < OMR_TR) {
1781 omr += 0x4000;
1782 } else {
1783 omr |= OMR_SF;
1784 }
1785 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1786 }
1787
1788 return 0;
1789}
1790
1791static int
1792de4x5_rx_ovfc(struct net_device *dev)
1793{
1794 struct de4x5_private *lp = netdev_priv(dev);
1795 u_long iobase = dev->base_addr;
1796 int omr;
1797
1798 omr = inl(DE4X5_OMR);
1799 outl(omr & ~OMR_SR, DE4X5_OMR);
1800 while (inl(DE4X5_STS) & STS_RS);
1801
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1805 }
1806
1807 outl(omr, DE4X5_OMR);
1808
1809 return 0;
1810}
1811
1812static int
1813de4x5_close(struct net_device *dev)
1814{
1815 struct de4x5_private *lp = netdev_priv(dev);
1816 u_long iobase = dev->base_addr;
1817 s32 imr, omr;
1818
1819 disable_ast(dev);
1820
1821 netif_stop_queue(dev);
1822
1823 if (de4x5_debug & DEBUG_CLOSE) {
1824 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1825 dev->name, inl(DE4X5_STS));
1826 }
1827
1828 /*
1829 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1830 */
1831 DISABLE_IRQs;
1832 STOP_DE4X5;
1833
1834 /* Free the associated irq */
1835 free_irq(dev->irq, dev);
1836 lp->state = CLOSED;
1837
1838 /* Free any socket buffers */
1839 de4x5_free_rx_buffs(dev);
1840 de4x5_free_tx_buffs(dev);
1841
1842 /* Put the adapter to sleep to save power */
1843 yawn(dev, SLEEP);
1844
1845 return 0;
1846}
1847
1848static struct net_device_stats *
1849de4x5_get_stats(struct net_device *dev)
1850{
1851 struct de4x5_private *lp = netdev_priv(dev);
1852 u_long iobase = dev->base_addr;
1853
1854 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1855
1856 return &lp->stats;
1857}
1858
1859static void
1860de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1861{
1862 struct de4x5_private *lp = netdev_priv(dev);
1863 int i;
1864
1865 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1866 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1867 lp->pktStats.bins[i]++;
1868 i = DE4X5_PKT_STAT_SZ;
1869 }
1870 }
1871 if (is_multicast_ether_addr(buf)) {
1872 if (is_broadcast_ether_addr(buf)) {
1873 lp->pktStats.broadcast++;
1874 } else {
1875 lp->pktStats.multicast++;
1876 }
1877 } else if (compare_ether_addr(buf, dev->dev_addr) == 0) {
1878 lp->pktStats.unicast++;
1879 }
1880
1881 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1882 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1883 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1884 }
1885}
1886
1887/*
1888** Removes the TD_IC flag from previous descriptor to improve TX performance.
1889** If the flag is changed on a descriptor that is being read by the hardware,
1890** I assume PCI transaction ordering will mean you are either successful or
1891** just miss asserting the change to the hardware. Anyway you're messing with
1892** a descriptor you don't own, but this shouldn't kill the chip provided
1893** the descriptor register is read only to the hardware.
1894*/
1895static void
1896load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1897{
1898 struct de4x5_private *lp = netdev_priv(dev);
1899 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1900 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1901
1902 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1903 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1904 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1905 lp->tx_skb[lp->tx_new] = skb;
1906 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1907 barrier();
1908
1909 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1910 barrier();
1911}
1912
1913/*
1914** Set or clear the multicast filter for this adaptor.
1915*/
1916static void
1917set_multicast_list(struct net_device *dev)
1918{
1919 struct de4x5_private *lp = netdev_priv(dev);
1920 u_long iobase = dev->base_addr;
1921
1922 /* First, double check that the adapter is open */
1923 if (lp->state == OPEN) {
1924 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1925 u32 omr;
1926 omr = inl(DE4X5_OMR);
1927 omr |= OMR_PR;
1928 outl(omr, DE4X5_OMR);
1929 } else {
1930 SetMulticastFilter(dev);
1931 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1932 SETUP_FRAME_LEN, (struct sk_buff *)1);
1933
1934 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1935 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1936 dev->trans_start = jiffies; /* prevent tx timeout */
1937 }
1938 }
1939}
1940
1941/*
1942** Calculate the hash code and update the logical address filter
1943** from a list of ethernet multicast addresses.
1944** Little endian crc one liner from Matt Thomas, DEC.
1945*/
1946static void
1947SetMulticastFilter(struct net_device *dev)
1948{
1949 struct de4x5_private *lp = netdev_priv(dev);
1950 struct netdev_hw_addr *ha;
1951 u_long iobase = dev->base_addr;
1952 int i, bit, byte;
1953 u16 hashcode;
1954 u32 omr, crc;
1955 char *pa;
1956 unsigned char *addrs;
1957
1958 omr = inl(DE4X5_OMR);
1959 omr &= ~(OMR_PR | OMR_PM);
1960 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1961
1962 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1963 omr |= OMR_PM; /* Pass all multicasts */
1964 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1965 netdev_for_each_mc_addr(ha, dev) {
1966 crc = ether_crc_le(ETH_ALEN, ha->addr);
1967 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1968
1969 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1970 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1971
1972 byte <<= 1; /* calc offset into setup frame */
1973 if (byte & 0x02) {
1974 byte -= 1;
1975 }
1976 lp->setup_frame[byte] |= bit;
1977 }
1978 } else { /* Perfect filtering */
1979 netdev_for_each_mc_addr(ha, dev) {
1980 addrs = ha->addr;
1981 for (i=0; i<ETH_ALEN; i++) {
1982 *(pa + (i&1)) = *addrs++;
1983 if (i & 0x01) pa += 4;
1984 }
1985 }
1986 }
1987 outl(omr, DE4X5_OMR);
1988}
1989
1990#ifdef CONFIG_EISA
1991
1992static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1993
1994static int __init de4x5_eisa_probe (struct device *gendev)
1995{
1996 struct eisa_device *edev;
1997 u_long iobase;
1998 u_char irq, regval;
1999 u_short vendor;
2000 u32 cfid;
2001 int status, device;
2002 struct net_device *dev;
2003 struct de4x5_private *lp;
2004
2005 edev = to_eisa_device (gendev);
2006 iobase = edev->base_addr;
2007
2008 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2009 return -EBUSY;
2010
2011 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2012 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2013 status = -EBUSY;
2014 goto release_reg_1;
2015 }
2016
2017 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2018 status = -ENOMEM;
2019 goto release_reg_2;
2020 }
2021 lp = netdev_priv(dev);
2022
2023 cfid = (u32) inl(PCI_CFID);
2024 lp->cfrv = (u_short) inl(PCI_CFRV);
2025 device = (cfid >> 8) & 0x00ffff00;
2026 vendor = (u_short) cfid;
2027
2028 /* Read the EISA Configuration Registers */
2029 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2030#ifdef CONFIG_ALPHA
2031 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2032 * care about the EISA configuration, and thus doesn't
2033 * configure the PLX bridge properly. Oh well... Simply mimic
2034 * the EISA config file to sort it out. */
2035
2036 /* EISA REG1: Assert DecChip 21040 HW Reset */
2037 outb (ER1_IAM | 1, EISA_REG1);
2038 mdelay (1);
2039
2040 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2041 outb (ER1_IAM, EISA_REG1);
2042 mdelay (1);
2043
2044 /* EISA REG3: R/W Burst Transfer Enable */
2045 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2046
2047 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2048 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2049#endif
2050 irq = de4x5_irq[(regval >> 1) & 0x03];
2051
2052 if (is_DC2114x) {
2053 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2054 }
2055 lp->chipset = device;
2056 lp->bus = EISA;
2057
2058 /* Write the PCI Configuration Registers */
2059 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2060 outl(0x00006000, PCI_CFLT);
2061 outl(iobase, PCI_CBIO);
2062
2063 DevicePresent(dev, EISA_APROM);
2064
2065 dev->irq = irq;
2066
2067 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2068 return 0;
2069 }
2070
2071 free_netdev (dev);
2072 release_reg_2:
2073 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2074 release_reg_1:
2075 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2076
2077 return status;
2078}
2079
2080static int __devexit de4x5_eisa_remove (struct device *device)
2081{
2082 struct net_device *dev;
2083 u_long iobase;
2084
2085 dev = dev_get_drvdata(device);
2086 iobase = dev->base_addr;
2087
2088 unregister_netdev (dev);
2089 free_netdev (dev);
2090 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2091 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2092
2093 return 0;
2094}
2095
2096static struct eisa_device_id de4x5_eisa_ids[] = {
2097 { "DEC4250", 0 }, /* 0 is the board name index... */
2098 { "" }
2099};
2100MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2101
2102static struct eisa_driver de4x5_eisa_driver = {
2103 .id_table = de4x5_eisa_ids,
2104 .driver = {
2105 .name = "de4x5",
2106 .probe = de4x5_eisa_probe,
2107 .remove = __devexit_p (de4x5_eisa_remove),
2108 }
2109};
2110MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2111#endif
2112
2113#ifdef CONFIG_PCI
2114
2115/*
2116** This function searches the current bus (which is >0) for a DECchip with an
2117** SROM, so that in multiport cards that have one SROM shared between multiple
2118** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2119** For single port cards this is a time waster...
2120*/
2121static void __devinit
2122srom_search(struct net_device *dev, struct pci_dev *pdev)
2123{
2124 u_char pb;
2125 u_short vendor, status;
2126 u_int irq = 0, device;
2127 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2128 int i, j;
2129 struct de4x5_private *lp = netdev_priv(dev);
2130 struct list_head *walk;
2131
2132 list_for_each(walk, &pdev->bus_list) {
2133 struct pci_dev *this_dev = pci_dev_b(walk);
2134
2135 /* Skip the pci_bus list entry */
2136 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2137
2138 vendor = this_dev->vendor;
2139 device = this_dev->device << 8;
2140 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2141
2142 /* Get the chip configuration revision register */
2143 pb = this_dev->bus->number;
2144
2145 /* Set the device number information */
2146 lp->device = PCI_SLOT(this_dev->devfn);
2147 lp->bus_num = pb;
2148
2149 /* Set the chipset information */
2150 if (is_DC2114x) {
2151 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2152 ? DC21142 : DC21143);
2153 }
2154 lp->chipset = device;
2155
2156 /* Get the board I/O address (64 bits on sparc64) */
2157 iobase = pci_resource_start(this_dev, 0);
2158
2159 /* Fetch the IRQ to be used */
2160 irq = this_dev->irq;
2161 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2162
2163 /* Check if I/O accesses are enabled */
2164 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2165 if (!(status & PCI_COMMAND_IO)) continue;
2166
2167 /* Search for a valid SROM attached to this DECchip */
2168 DevicePresent(dev, DE4X5_APROM);
2169 for (j=0, i=0; i<ETH_ALEN; i++) {
2170 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2171 }
2172 if (j != 0 && j != 6 * 0xff) {
2173 last.chipset = device;
2174 last.bus = pb;
2175 last.irq = irq;
2176 for (i=0; i<ETH_ALEN; i++) {
2177 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2178 }
2179 return;
2180 }
2181 }
2182}
2183
2184/*
2185** PCI bus I/O device probe
2186** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2187** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2188** enabled by the user first in the set up utility. Hence we just check for
2189** enabled features and silently ignore the card if they're not.
2190**
2191** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2192** bit. Here, check for I/O accesses and then set BM. If you put the card in
2193** a non BM slot, you're on your own (and complain to the PC vendor that your
2194** PC doesn't conform to the PCI standard)!
2195**
2196** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2197** kernels use the V0.535[n] drivers.
2198*/
2199
2200static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2201 const struct pci_device_id *ent)
2202{
2203 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2204 u_short vendor, status;
2205 u_int irq = 0, device;
2206 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2207 int error;
2208 struct net_device *dev;
2209 struct de4x5_private *lp;
2210
2211 dev_num = PCI_SLOT(pdev->devfn);
2212 pb = pdev->bus->number;
2213
2214 if (io) { /* probe a single PCI device */
2215 pbus = (u_short)(io >> 8);
2216 dnum = (u_short)(io & 0xff);
2217 if ((pbus != pb) || (dnum != dev_num))
2218 return -ENODEV;
2219 }
2220
2221 vendor = pdev->vendor;
2222 device = pdev->device << 8;
2223 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2224 return -ENODEV;
2225
2226 /* Ok, the device seems to be for us. */
2227 if ((error = pci_enable_device (pdev)))
2228 return error;
2229
2230 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2231 error = -ENOMEM;
2232 goto disable_dev;
2233 }
2234
2235 lp = netdev_priv(dev);
2236 lp->bus = PCI;
2237 lp->bus_num = 0;
2238
2239 /* Search for an SROM on this bus */
2240 if (lp->bus_num != pb) {
2241 lp->bus_num = pb;
2242 srom_search(dev, pdev);
2243 }
2244
2245 /* Get the chip configuration revision register */
2246 lp->cfrv = pdev->revision;
2247
2248 /* Set the device number information */
2249 lp->device = dev_num;
2250 lp->bus_num = pb;
2251
2252 /* Set the chipset information */
2253 if (is_DC2114x) {
2254 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2255 }
2256 lp->chipset = device;
2257
2258 /* Get the board I/O address (64 bits on sparc64) */
2259 iobase = pci_resource_start(pdev, 0);
2260
2261 /* Fetch the IRQ to be used */
2262 irq = pdev->irq;
2263 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2264 error = -ENODEV;
2265 goto free_dev;
2266 }
2267
2268 /* Check if I/O accesses and Bus Mastering are enabled */
2269 pci_read_config_word(pdev, PCI_COMMAND, &status);
2270#ifdef __powerpc__
2271 if (!(status & PCI_COMMAND_IO)) {
2272 status |= PCI_COMMAND_IO;
2273 pci_write_config_word(pdev, PCI_COMMAND, status);
2274 pci_read_config_word(pdev, PCI_COMMAND, &status);
2275 }
2276#endif /* __powerpc__ */
2277 if (!(status & PCI_COMMAND_IO)) {
2278 error = -ENODEV;
2279 goto free_dev;
2280 }
2281
2282 if (!(status & PCI_COMMAND_MASTER)) {
2283 status |= PCI_COMMAND_MASTER;
2284 pci_write_config_word(pdev, PCI_COMMAND, status);
2285 pci_read_config_word(pdev, PCI_COMMAND, &status);
2286 }
2287 if (!(status & PCI_COMMAND_MASTER)) {
2288 error = -ENODEV;
2289 goto free_dev;
2290 }
2291
2292 /* Check the latency timer for values >= 0x60 */
2293 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2294 if (timer < 0x60) {
2295 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2296 }
2297
2298 DevicePresent(dev, DE4X5_APROM);
2299
2300 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2301 error = -EBUSY;
2302 goto free_dev;
2303 }
2304
2305 dev->irq = irq;
2306
2307 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2308 goto release;
2309 }
2310
2311 return 0;
2312
2313 release:
2314 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2315 free_dev:
2316 free_netdev (dev);
2317 disable_dev:
2318 pci_disable_device (pdev);
2319 return error;
2320}
2321
2322static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2323{
2324 struct net_device *dev;
2325 u_long iobase;
2326
2327 dev = dev_get_drvdata(&pdev->dev);
2328 iobase = dev->base_addr;
2329
2330 unregister_netdev (dev);
2331 free_netdev (dev);
2332 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2333 pci_disable_device (pdev);
2334}
2335
2336static struct pci_device_id de4x5_pci_tbl[] = {
2337 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2339 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2341 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2343 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2345 { },
2346};
2347
2348static struct pci_driver de4x5_pci_driver = {
2349 .name = "de4x5",
2350 .id_table = de4x5_pci_tbl,
2351 .probe = de4x5_pci_probe,
2352 .remove = __devexit_p (de4x5_pci_remove),
2353};
2354
2355#endif
2356
2357/*
2358** Auto configure the media here rather than setting the port at compile
2359** time. This routine is called by de4x5_init() and when a loss of media is
2360** detected (excessive collisions, loss of carrier, no carrier or link fail
2361** [TP] or no recent receive activity) to check whether the user has been
2362** sneaky and changed the port on us.
2363*/
2364static int
2365autoconf_media(struct net_device *dev)
2366{
2367 struct de4x5_private *lp = netdev_priv(dev);
2368 u_long iobase = dev->base_addr;
2369
2370 disable_ast(dev);
2371
2372 lp->c_media = AUTO; /* Bogus last media */
2373 inl(DE4X5_MFC); /* Zero the lost frames counter */
2374 lp->media = INIT;
2375 lp->tcount = 0;
2376
2377 de4x5_ast(dev);
2378
2379 return lp->media;
2380}
2381
2382/*
2383** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2384** from BNC as the port has a jumper to set thick or thin wire. When set for
2385** BNC, the BNC port will indicate activity if it's not terminated correctly.
2386** The only way to test for that is to place a loopback packet onto the
2387** network and watch for errors. Since we're messing with the interrupt mask
2388** register, disable the board interrupts and do not allow any more packets to
2389** be queued to the hardware. Re-enable everything only when the media is
2390** found.
2391** I may have to "age out" locally queued packets so that the higher layer
2392** timeouts don't effectively duplicate packets on the network.
2393*/
2394static int
2395dc21040_autoconf(struct net_device *dev)
2396{
2397 struct de4x5_private *lp = netdev_priv(dev);
2398 u_long iobase = dev->base_addr;
2399 int next_tick = DE4X5_AUTOSENSE_MS;
2400 s32 imr;
2401
2402 switch (lp->media) {
2403 case INIT:
2404 DISABLE_IRQs;
2405 lp->tx_enable = false;
2406 lp->timeout = -1;
2407 de4x5_save_skbs(dev);
2408 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2409 lp->media = TP;
2410 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2411 lp->media = BNC_AUI;
2412 } else if (lp->autosense == EXT_SIA) {
2413 lp->media = EXT_SIA;
2414 } else {
2415 lp->media = NC;
2416 }
2417 lp->local_state = 0;
2418 next_tick = dc21040_autoconf(dev);
2419 break;
2420
2421 case TP:
2422 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2423 TP_SUSPECT, test_tp);
2424 break;
2425
2426 case TP_SUSPECT:
2427 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2428 break;
2429
2430 case BNC:
2431 case AUI:
2432 case BNC_AUI:
2433 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2434 BNC_AUI_SUSPECT, ping_media);
2435 break;
2436
2437 case BNC_AUI_SUSPECT:
2438 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2439 break;
2440
2441 case EXT_SIA:
2442 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2443 NC, EXT_SIA_SUSPECT, ping_media);
2444 break;
2445
2446 case EXT_SIA_SUSPECT:
2447 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2448 break;
2449
2450 case NC:
2451 /* default to TP for all */
2452 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2453 if (lp->media != lp->c_media) {
2454 de4x5_dbg_media(dev);
2455 lp->c_media = lp->media;
2456 }
2457 lp->media = INIT;
2458 lp->tx_enable = false;
2459 break;
2460 }
2461
2462 return next_tick;
2463}
2464
2465static int
2466dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2467 int next_state, int suspect_state,
2468 int (*fn)(struct net_device *, int))
2469{
2470 struct de4x5_private *lp = netdev_priv(dev);
2471 int next_tick = DE4X5_AUTOSENSE_MS;
2472 int linkBad;
2473
2474 switch (lp->local_state) {
2475 case 0:
2476 reset_init_sia(dev, csr13, csr14, csr15);
2477 lp->local_state++;
2478 next_tick = 500;
2479 break;
2480
2481 case 1:
2482 if (!lp->tx_enable) {
2483 linkBad = fn(dev, timeout);
2484 if (linkBad < 0) {
2485 next_tick = linkBad & ~TIMER_CB;
2486 } else {
2487 if (linkBad && (lp->autosense == AUTO)) {
2488 lp->local_state = 0;
2489 lp->media = next_state;
2490 } else {
2491 de4x5_init_connection(dev);
2492 }
2493 }
2494 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2495 lp->media = suspect_state;
2496 next_tick = 3000;
2497 }
2498 break;
2499 }
2500
2501 return next_tick;
2502}
2503
2504static int
2505de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2506 int (*fn)(struct net_device *, int),
2507 int (*asfn)(struct net_device *))
2508{
2509 struct de4x5_private *lp = netdev_priv(dev);
2510 int next_tick = DE4X5_AUTOSENSE_MS;
2511 int linkBad;
2512
2513 switch (lp->local_state) {
2514 case 1:
2515 if (lp->linkOK) {
2516 lp->media = prev_state;
2517 } else {
2518 lp->local_state++;
2519 next_tick = asfn(dev);
2520 }
2521 break;
2522
2523 case 2:
2524 linkBad = fn(dev, timeout);
2525 if (linkBad < 0) {
2526 next_tick = linkBad & ~TIMER_CB;
2527 } else if (!linkBad) {
2528 lp->local_state--;
2529 lp->media = prev_state;
2530 } else {
2531 lp->media = INIT;
2532 lp->tcount++;
2533 }
2534 }
2535
2536 return next_tick;
2537}
2538
2539/*
2540** Autoconfigure the media when using the DC21041. AUI needs to be tested
2541** before BNC, because the BNC port will indicate activity if it's not
2542** terminated correctly. The only way to test for that is to place a loopback
2543** packet onto the network and watch for errors. Since we're messing with
2544** the interrupt mask register, disable the board interrupts and do not allow
2545** any more packets to be queued to the hardware. Re-enable everything only
2546** when the media is found.
2547*/
2548static int
2549dc21041_autoconf(struct net_device *dev)
2550{
2551 struct de4x5_private *lp = netdev_priv(dev);
2552 u_long iobase = dev->base_addr;
2553 s32 sts, irqs, irq_mask, imr, omr;
2554 int next_tick = DE4X5_AUTOSENSE_MS;
2555
2556 switch (lp->media) {
2557 case INIT:
2558 DISABLE_IRQs;
2559 lp->tx_enable = false;
2560 lp->timeout = -1;
2561 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2562 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2563 lp->media = TP; /* On chip auto negotiation is broken */
2564 } else if (lp->autosense == TP) {
2565 lp->media = TP;
2566 } else if (lp->autosense == BNC) {
2567 lp->media = BNC;
2568 } else if (lp->autosense == AUI) {
2569 lp->media = AUI;
2570 } else {
2571 lp->media = NC;
2572 }
2573 lp->local_state = 0;
2574 next_tick = dc21041_autoconf(dev);
2575 break;
2576
2577 case TP_NW:
2578 if (lp->timeout < 0) {
2579 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2580 outl(omr | OMR_FDX, DE4X5_OMR);
2581 }
2582 irqs = STS_LNF | STS_LNP;
2583 irq_mask = IMR_LFM | IMR_LPM;
2584 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2585 if (sts < 0) {
2586 next_tick = sts & ~TIMER_CB;
2587 } else {
2588 if (sts & STS_LNP) {
2589 lp->media = ANS;
2590 } else {
2591 lp->media = AUI;
2592 }
2593 next_tick = dc21041_autoconf(dev);
2594 }
2595 break;
2596
2597 case ANS:
2598 if (!lp->tx_enable) {
2599 irqs = STS_LNP;
2600 irq_mask = IMR_LPM;
2601 sts = test_ans(dev, irqs, irq_mask, 3000);
2602 if (sts < 0) {
2603 next_tick = sts & ~TIMER_CB;
2604 } else {
2605 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2606 lp->media = TP;
2607 next_tick = dc21041_autoconf(dev);
2608 } else {
2609 lp->local_state = 1;
2610 de4x5_init_connection(dev);
2611 }
2612 }
2613 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2614 lp->media = ANS_SUSPECT;
2615 next_tick = 3000;
2616 }
2617 break;
2618
2619 case ANS_SUSPECT:
2620 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2621 break;
2622
2623 case TP:
2624 if (!lp->tx_enable) {
2625 if (lp->timeout < 0) {
2626 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2627 outl(omr & ~OMR_FDX, DE4X5_OMR);
2628 }
2629 irqs = STS_LNF | STS_LNP;
2630 irq_mask = IMR_LFM | IMR_LPM;
2631 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2632 if (sts < 0) {
2633 next_tick = sts & ~TIMER_CB;
2634 } else {
2635 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2636 if (inl(DE4X5_SISR) & SISR_NRA) {
2637 lp->media = AUI; /* Non selected port activity */
2638 } else {
2639 lp->media = BNC;
2640 }
2641 next_tick = dc21041_autoconf(dev);
2642 } else {
2643 lp->local_state = 1;
2644 de4x5_init_connection(dev);
2645 }
2646 }
2647 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2648 lp->media = TP_SUSPECT;
2649 next_tick = 3000;
2650 }
2651 break;
2652
2653 case TP_SUSPECT:
2654 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2655 break;
2656
2657 case AUI:
2658 if (!lp->tx_enable) {
2659 if (lp->timeout < 0) {
2660 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2661 outl(omr & ~OMR_FDX, DE4X5_OMR);
2662 }
2663 irqs = 0;
2664 irq_mask = 0;
2665 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2666 if (sts < 0) {
2667 next_tick = sts & ~TIMER_CB;
2668 } else {
2669 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2670 lp->media = BNC;
2671 next_tick = dc21041_autoconf(dev);
2672 } else {
2673 lp->local_state = 1;
2674 de4x5_init_connection(dev);
2675 }
2676 }
2677 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2678 lp->media = AUI_SUSPECT;
2679 next_tick = 3000;
2680 }
2681 break;
2682
2683 case AUI_SUSPECT:
2684 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2685 break;
2686
2687 case BNC:
2688 switch (lp->local_state) {
2689 case 0:
2690 if (lp->timeout < 0) {
2691 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2692 outl(omr & ~OMR_FDX, DE4X5_OMR);
2693 }
2694 irqs = 0;
2695 irq_mask = 0;
2696 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2697 if (sts < 0) {
2698 next_tick = sts & ~TIMER_CB;
2699 } else {
2700 lp->local_state++; /* Ensure media connected */
2701 next_tick = dc21041_autoconf(dev);
2702 }
2703 break;
2704
2705 case 1:
2706 if (!lp->tx_enable) {
2707 if ((sts = ping_media(dev, 3000)) < 0) {
2708 next_tick = sts & ~TIMER_CB;
2709 } else {
2710 if (sts) {
2711 lp->local_state = 0;
2712 lp->media = NC;
2713 } else {
2714 de4x5_init_connection(dev);
2715 }
2716 }
2717 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2718 lp->media = BNC_SUSPECT;
2719 next_tick = 3000;
2720 }
2721 break;
2722 }
2723 break;
2724
2725 case BNC_SUSPECT:
2726 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2727 break;
2728
2729 case NC:
2730 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2731 outl(omr | OMR_FDX, DE4X5_OMR);
2732 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2733 if (lp->media != lp->c_media) {
2734 de4x5_dbg_media(dev);
2735 lp->c_media = lp->media;
2736 }
2737 lp->media = INIT;
2738 lp->tx_enable = false;
2739 break;
2740 }
2741
2742 return next_tick;
2743}
2744
2745/*
2746** Some autonegotiation chips are broken in that they do not return the
2747** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2748** register, except at the first power up negotiation.
2749*/
2750static int
2751dc21140m_autoconf(struct net_device *dev)
2752{
2753 struct de4x5_private *lp = netdev_priv(dev);
2754 int ana, anlpa, cap, cr, slnk, sr;
2755 int next_tick = DE4X5_AUTOSENSE_MS;
2756 u_long imr, omr, iobase = dev->base_addr;
2757
2758 switch(lp->media) {
2759 case INIT:
2760 if (lp->timeout < 0) {
2761 DISABLE_IRQs;
2762 lp->tx_enable = false;
2763 lp->linkOK = 0;
2764 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2765 }
2766 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2767 next_tick &= ~TIMER_CB;
2768 } else {
2769 if (lp->useSROM) {
2770 if (srom_map_media(dev) < 0) {
2771 lp->tcount++;
2772 return next_tick;
2773 }
2774 srom_exec(dev, lp->phy[lp->active].gep);
2775 if (lp->infoblock_media == ANS) {
2776 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2777 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2778 }
2779 } else {
2780 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2781 SET_10Mb;
2782 if (lp->autosense == _100Mb) {
2783 lp->media = _100Mb;
2784 } else if (lp->autosense == _10Mb) {
2785 lp->media = _10Mb;
2786 } else if ((lp->autosense == AUTO) &&
2787 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2788 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2789 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2790 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2791 lp->media = ANS;
2792 } else if (lp->autosense == AUTO) {
2793 lp->media = SPD_DET;
2794 } else if (is_spd_100(dev) && is_100_up(dev)) {
2795 lp->media = _100Mb;
2796 } else {
2797 lp->media = NC;
2798 }
2799 }
2800 lp->local_state = 0;
2801 next_tick = dc21140m_autoconf(dev);
2802 }
2803 break;
2804
2805 case ANS:
2806 switch (lp->local_state) {
2807 case 0:
2808 if (lp->timeout < 0) {
2809 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2810 }
2811 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2812 if (cr < 0) {
2813 next_tick = cr & ~TIMER_CB;
2814 } else {
2815 if (cr) {
2816 lp->local_state = 0;
2817 lp->media = SPD_DET;
2818 } else {
2819 lp->local_state++;
2820 }
2821 next_tick = dc21140m_autoconf(dev);
2822 }
2823 break;
2824
2825 case 1:
2826 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2827 next_tick = sr & ~TIMER_CB;
2828 } else {
2829 lp->media = SPD_DET;
2830 lp->local_state = 0;
2831 if (sr) { /* Success! */
2832 lp->tmp = MII_SR_ASSC;
2833 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2834 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2835 if (!(anlpa & MII_ANLPA_RF) &&
2836 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2837 if (cap & MII_ANA_100M) {
2838 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2839 lp->media = _100Mb;
2840 } else if (cap & MII_ANA_10M) {
2841 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2842
2843 lp->media = _10Mb;
2844 }
2845 }
2846 } /* Auto Negotiation failed to finish */
2847 next_tick = dc21140m_autoconf(dev);
2848 } /* Auto Negotiation failed to start */
2849 break;
2850 }
2851 break;
2852
2853 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2854 if (lp->timeout < 0) {
2855 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2856 (~gep_rd(dev) & GEP_LNP));
2857 SET_100Mb_PDET;
2858 }
2859 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2860 next_tick = slnk & ~TIMER_CB;
2861 } else {
2862 if (is_spd_100(dev) && is_100_up(dev)) {
2863 lp->media = _100Mb;
2864 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2865 lp->media = _10Mb;
2866 } else {
2867 lp->media = NC;
2868 }
2869 next_tick = dc21140m_autoconf(dev);
2870 }
2871 break;
2872
2873 case _100Mb: /* Set 100Mb/s */
2874 next_tick = 3000;
2875 if (!lp->tx_enable) {
2876 SET_100Mb;
2877 de4x5_init_connection(dev);
2878 } else {
2879 if (!lp->linkOK && (lp->autosense == AUTO)) {
2880 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2881 lp->media = INIT;
2882 lp->tcount++;
2883 next_tick = DE4X5_AUTOSENSE_MS;
2884 }
2885 }
2886 }
2887 break;
2888
2889 case BNC:
2890 case AUI:
2891 case _10Mb: /* Set 10Mb/s */
2892 next_tick = 3000;
2893 if (!lp->tx_enable) {
2894 SET_10Mb;
2895 de4x5_init_connection(dev);
2896 } else {
2897 if (!lp->linkOK && (lp->autosense == AUTO)) {
2898 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2899 lp->media = INIT;
2900 lp->tcount++;
2901 next_tick = DE4X5_AUTOSENSE_MS;
2902 }
2903 }
2904 }
2905 break;
2906
2907 case NC:
2908 if (lp->media != lp->c_media) {
2909 de4x5_dbg_media(dev);
2910 lp->c_media = lp->media;
2911 }
2912 lp->media = INIT;
2913 lp->tx_enable = false;
2914 break;
2915 }
2916
2917 return next_tick;
2918}
2919
2920/*
2921** This routine may be merged into dc21140m_autoconf() sometime as I'm
2922** changing how I figure out the media - but trying to keep it backwards
2923** compatible with the de500-xa and de500-aa.
2924** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2925** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2926** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2927** active.
2928** When autonegotiation is working, the ANS part searches the SROM for
2929** the highest common speed (TP) link that both can run and if that can
2930** be full duplex. That infoblock is executed and then the link speed set.
2931**
2932** Only _10Mb and _100Mb are tested here.
2933*/
2934static int
2935dc2114x_autoconf(struct net_device *dev)
2936{
2937 struct de4x5_private *lp = netdev_priv(dev);
2938 u_long iobase = dev->base_addr;
2939 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2940 int next_tick = DE4X5_AUTOSENSE_MS;
2941
2942 switch (lp->media) {
2943 case INIT:
2944 if (lp->timeout < 0) {
2945 DISABLE_IRQs;
2946 lp->tx_enable = false;
2947 lp->linkOK = 0;
2948 lp->timeout = -1;
2949 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2950 if (lp->params.autosense & ~AUTO) {
2951 srom_map_media(dev); /* Fixed media requested */
2952 if (lp->media != lp->params.autosense) {
2953 lp->tcount++;
2954 lp->media = INIT;
2955 return next_tick;
2956 }
2957 lp->media = INIT;
2958 }
2959 }
2960 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2961 next_tick &= ~TIMER_CB;
2962 } else {
2963 if (lp->autosense == _100Mb) {
2964 lp->media = _100Mb;
2965 } else if (lp->autosense == _10Mb) {
2966 lp->media = _10Mb;
2967 } else if (lp->autosense == TP) {
2968 lp->media = TP;
2969 } else if (lp->autosense == BNC) {
2970 lp->media = BNC;
2971 } else if (lp->autosense == AUI) {
2972 lp->media = AUI;
2973 } else {
2974 lp->media = SPD_DET;
2975 if ((lp->infoblock_media == ANS) &&
2976 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2977 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2978 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2979 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2980 lp->media = ANS;
2981 }
2982 }
2983 lp->local_state = 0;
2984 next_tick = dc2114x_autoconf(dev);
2985 }
2986 break;
2987
2988 case ANS:
2989 switch (lp->local_state) {
2990 case 0:
2991 if (lp->timeout < 0) {
2992 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2993 }
2994 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2995 if (cr < 0) {
2996 next_tick = cr & ~TIMER_CB;
2997 } else {
2998 if (cr) {
2999 lp->local_state = 0;
3000 lp->media = SPD_DET;
3001 } else {
3002 lp->local_state++;
3003 }
3004 next_tick = dc2114x_autoconf(dev);
3005 }
3006 break;
3007
3008 case 1:
3009 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3010 if (sr < 0) {
3011 next_tick = sr & ~TIMER_CB;
3012 } else {
3013 lp->media = SPD_DET;
3014 lp->local_state = 0;
3015 if (sr) { /* Success! */
3016 lp->tmp = MII_SR_ASSC;
3017 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3018 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3019 if (!(anlpa & MII_ANLPA_RF) &&
3020 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3021 if (cap & MII_ANA_100M) {
3022 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3023 lp->media = _100Mb;
3024 } else if (cap & MII_ANA_10M) {
3025 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3026 lp->media = _10Mb;
3027 }
3028 }
3029 } /* Auto Negotiation failed to finish */
3030 next_tick = dc2114x_autoconf(dev);
3031 } /* Auto Negotiation failed to start */
3032 break;
3033 }
3034 break;
3035
3036 case AUI:
3037 if (!lp->tx_enable) {
3038 if (lp->timeout < 0) {
3039 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3040 outl(omr & ~OMR_FDX, DE4X5_OMR);
3041 }
3042 irqs = 0;
3043 irq_mask = 0;
3044 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3045 if (sts < 0) {
3046 next_tick = sts & ~TIMER_CB;
3047 } else {
3048 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3049 lp->media = BNC;
3050 next_tick = dc2114x_autoconf(dev);
3051 } else {
3052 lp->local_state = 1;
3053 de4x5_init_connection(dev);
3054 }
3055 }
3056 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3057 lp->media = AUI_SUSPECT;
3058 next_tick = 3000;
3059 }
3060 break;
3061
3062 case AUI_SUSPECT:
3063 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3064 break;
3065
3066 case BNC:
3067 switch (lp->local_state) {
3068 case 0:
3069 if (lp->timeout < 0) {
3070 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3071 outl(omr & ~OMR_FDX, DE4X5_OMR);
3072 }
3073 irqs = 0;
3074 irq_mask = 0;
3075 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3076 if (sts < 0) {
3077 next_tick = sts & ~TIMER_CB;
3078 } else {
3079 lp->local_state++; /* Ensure media connected */
3080 next_tick = dc2114x_autoconf(dev);
3081 }
3082 break;
3083
3084 case 1:
3085 if (!lp->tx_enable) {
3086 if ((sts = ping_media(dev, 3000)) < 0) {
3087 next_tick = sts & ~TIMER_CB;
3088 } else {
3089 if (sts) {
3090 lp->local_state = 0;
3091 lp->tcount++;
3092 lp->media = INIT;
3093 } else {
3094 de4x5_init_connection(dev);
3095 }
3096 }
3097 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3098 lp->media = BNC_SUSPECT;
3099 next_tick = 3000;
3100 }
3101 break;
3102 }
3103 break;
3104
3105 case BNC_SUSPECT:
3106 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3107 break;
3108
3109 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3110 if (srom_map_media(dev) < 0) {
3111 lp->tcount++;
3112 lp->media = INIT;
3113 return next_tick;
3114 }
3115 if (lp->media == _100Mb) {
3116 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3117 lp->media = SPD_DET;
3118 return slnk & ~TIMER_CB;
3119 }
3120 } else {
3121 if (wait_for_link(dev) < 0) {
3122 lp->media = SPD_DET;
3123 return PDET_LINK_WAIT;
3124 }
3125 }
3126 if (lp->media == ANS) { /* Do MII parallel detection */
3127 if (is_spd_100(dev)) {
3128 lp->media = _100Mb;
3129 } else {
3130 lp->media = _10Mb;
3131 }
3132 next_tick = dc2114x_autoconf(dev);
3133 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3134 (((lp->media == _10Mb) || (lp->media == TP) ||
3135 (lp->media == BNC) || (lp->media == AUI)) &&
3136 is_10_up(dev))) {
3137 next_tick = dc2114x_autoconf(dev);
3138 } else {
3139 lp->tcount++;
3140 lp->media = INIT;
3141 }
3142 break;
3143
3144 case _10Mb:
3145 next_tick = 3000;
3146 if (!lp->tx_enable) {
3147 SET_10Mb;
3148 de4x5_init_connection(dev);
3149 } else {
3150 if (!lp->linkOK && (lp->autosense == AUTO)) {
3151 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3152 lp->media = INIT;
3153 lp->tcount++;
3154 next_tick = DE4X5_AUTOSENSE_MS;
3155 }
3156 }
3157 }
3158 break;
3159
3160 case _100Mb:
3161 next_tick = 3000;
3162 if (!lp->tx_enable) {
3163 SET_100Mb;
3164 de4x5_init_connection(dev);
3165 } else {
3166 if (!lp->linkOK && (lp->autosense == AUTO)) {
3167 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3168 lp->media = INIT;
3169 lp->tcount++;
3170 next_tick = DE4X5_AUTOSENSE_MS;
3171 }
3172 }
3173 }
3174 break;
3175
3176 default:
3177 lp->tcount++;
3178printk("Huh?: media:%02x\n", lp->media);
3179 lp->media = INIT;
3180 break;
3181 }
3182
3183 return next_tick;
3184}
3185
3186static int
3187srom_autoconf(struct net_device *dev)
3188{
3189 struct de4x5_private *lp = netdev_priv(dev);
3190
3191 return lp->infoleaf_fn(dev);
3192}
3193
3194/*
3195** This mapping keeps the original media codes and FDX flag unchanged.
3196** While it isn't strictly necessary, it helps me for the moment...
3197** The early return avoids a media state / SROM media space clash.
3198*/
3199static int
3200srom_map_media(struct net_device *dev)
3201{
3202 struct de4x5_private *lp = netdev_priv(dev);
3203
3204 lp->fdx = false;
3205 if (lp->infoblock_media == lp->media)
3206 return 0;
3207
3208 switch(lp->infoblock_media) {
3209 case SROM_10BASETF:
3210 if (!lp->params.fdx) return -1;
3211 lp->fdx = true;
3212 case SROM_10BASET:
3213 if (lp->params.fdx && !lp->fdx) return -1;
3214 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3215 lp->media = _10Mb;
3216 } else {
3217 lp->media = TP;
3218 }
3219 break;
3220
3221 case SROM_10BASE2:
3222 lp->media = BNC;
3223 break;
3224
3225 case SROM_10BASE5:
3226 lp->media = AUI;
3227 break;
3228
3229 case SROM_100BASETF:
3230 if (!lp->params.fdx) return -1;
3231 lp->fdx = true;
3232 case SROM_100BASET:
3233 if (lp->params.fdx && !lp->fdx) return -1;
3234 lp->media = _100Mb;
3235 break;
3236
3237 case SROM_100BASET4:
3238 lp->media = _100Mb;
3239 break;
3240
3241 case SROM_100BASEFF:
3242 if (!lp->params.fdx) return -1;
3243 lp->fdx = true;
3244 case SROM_100BASEF:
3245 if (lp->params.fdx && !lp->fdx) return -1;
3246 lp->media = _100Mb;
3247 break;
3248
3249 case ANS:
3250 lp->media = ANS;
3251 lp->fdx = lp->params.fdx;
3252 break;
3253
3254 default:
3255 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3256 lp->infoblock_media);
3257 return -1;
3258 break;
3259 }
3260
3261 return 0;
3262}
3263
3264static void
3265de4x5_init_connection(struct net_device *dev)
3266{
3267 struct de4x5_private *lp = netdev_priv(dev);
3268 u_long iobase = dev->base_addr;
3269 u_long flags = 0;
3270
3271 if (lp->media != lp->c_media) {
3272 de4x5_dbg_media(dev);
3273 lp->c_media = lp->media; /* Stop scrolling media messages */
3274 }
3275
3276 spin_lock_irqsave(&lp->lock, flags);
3277 de4x5_rst_desc_ring(dev);
3278 de4x5_setup_intr(dev);
3279 lp->tx_enable = true;
3280 spin_unlock_irqrestore(&lp->lock, flags);
3281 outl(POLL_DEMAND, DE4X5_TPD);
3282
3283 netif_wake_queue(dev);
3284}
3285
3286/*
3287** General PHY reset function. Some MII devices don't reset correctly
3288** since their MII address pins can float at voltages that are dependent
3289** on the signal pin use. Do a double reset to ensure a reset.
3290*/
3291static int
3292de4x5_reset_phy(struct net_device *dev)
3293{
3294 struct de4x5_private *lp = netdev_priv(dev);
3295 u_long iobase = dev->base_addr;
3296 int next_tick = 0;
3297
3298 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3299 if (lp->timeout < 0) {
3300 if (lp->useSROM) {
3301 if (lp->phy[lp->active].rst) {
3302 srom_exec(dev, lp->phy[lp->active].rst);
3303 srom_exec(dev, lp->phy[lp->active].rst);
3304 } else if (lp->rst) { /* Type 5 infoblock reset */
3305 srom_exec(dev, lp->rst);
3306 srom_exec(dev, lp->rst);
3307 }
3308 } else {
3309 PHY_HARD_RESET;
3310 }
3311 if (lp->useMII) {
3312 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3313 }
3314 }
3315 if (lp->useMII) {
3316 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3317 }
3318 } else if (lp->chipset == DC21140) {
3319 PHY_HARD_RESET;
3320 }
3321
3322 return next_tick;
3323}
3324
3325static int
3326test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3327{
3328 struct de4x5_private *lp = netdev_priv(dev);
3329 u_long iobase = dev->base_addr;
3330 s32 sts, csr12;
3331
3332 if (lp->timeout < 0) {
3333 lp->timeout = msec/100;
3334 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3335 reset_init_sia(dev, csr13, csr14, csr15);
3336 }
3337
3338 /* set up the interrupt mask */
3339 outl(irq_mask, DE4X5_IMR);
3340
3341 /* clear all pending interrupts */
3342 sts = inl(DE4X5_STS);
3343 outl(sts, DE4X5_STS);
3344
3345 /* clear csr12 NRA and SRA bits */
3346 if ((lp->chipset == DC21041) || lp->useSROM) {
3347 csr12 = inl(DE4X5_SISR);
3348 outl(csr12, DE4X5_SISR);
3349 }
3350 }
3351
3352 sts = inl(DE4X5_STS) & ~TIMER_CB;
3353
3354 if (!(sts & irqs) && --lp->timeout) {
3355 sts = 100 | TIMER_CB;
3356 } else {
3357 lp->timeout = -1;
3358 }
3359
3360 return sts;
3361}
3362
3363static int
3364test_tp(struct net_device *dev, s32 msec)
3365{
3366 struct de4x5_private *lp = netdev_priv(dev);
3367 u_long iobase = dev->base_addr;
3368 int sisr;
3369
3370 if (lp->timeout < 0) {
3371 lp->timeout = msec/100;
3372 }
3373
3374 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3375
3376 if (sisr && --lp->timeout) {
3377 sisr = 100 | TIMER_CB;
3378 } else {
3379 lp->timeout = -1;
3380 }
3381
3382 return sisr;
3383}
3384
3385/*
3386** Samples the 100Mb Link State Signal. The sample interval is important
3387** because too fast a rate can give erroneous results and confuse the
3388** speed sense algorithm.
3389*/
3390#define SAMPLE_INTERVAL 500 /* ms */
3391#define SAMPLE_DELAY 2000 /* ms */
3392static int
3393test_for_100Mb(struct net_device *dev, int msec)
3394{
3395 struct de4x5_private *lp = netdev_priv(dev);
3396 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3397
3398 if (lp->timeout < 0) {
3399 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3400 if (msec > SAMPLE_DELAY) {
3401 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3402 gep = SAMPLE_DELAY | TIMER_CB;
3403 return gep;
3404 } else {
3405 lp->timeout = msec/SAMPLE_INTERVAL;
3406 }
3407 }
3408
3409 if (lp->phy[lp->active].id || lp->useSROM) {
3410 gep = is_100_up(dev) | is_spd_100(dev);
3411 } else {
3412 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3413 }
3414 if (!(gep & ret) && --lp->timeout) {
3415 gep = SAMPLE_INTERVAL | TIMER_CB;
3416 } else {
3417 lp->timeout = -1;
3418 }
3419
3420 return gep;
3421}
3422
3423static int
3424wait_for_link(struct net_device *dev)
3425{
3426 struct de4x5_private *lp = netdev_priv(dev);
3427
3428 if (lp->timeout < 0) {
3429 lp->timeout = 1;
3430 }
3431
3432 if (lp->timeout--) {
3433 return TIMER_CB;
3434 } else {
3435 lp->timeout = -1;
3436 }
3437
3438 return 0;
3439}
3440
3441/*
3442**
3443**
3444*/
3445static int
3446test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3447{
3448 struct de4x5_private *lp = netdev_priv(dev);
3449 int test;
3450 u_long iobase = dev->base_addr;
3451
3452 if (lp->timeout < 0) {
3453 lp->timeout = msec/100;
3454 }
3455
3456 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3457 test = (reg ^ (pol ? ~0 : 0)) & mask;
3458
3459 if (test && --lp->timeout) {
3460 reg = 100 | TIMER_CB;
3461 } else {
3462 lp->timeout = -1;
3463 }
3464
3465 return reg;
3466}
3467
3468static int
3469is_spd_100(struct net_device *dev)
3470{
3471 struct de4x5_private *lp = netdev_priv(dev);
3472 u_long iobase = dev->base_addr;
3473 int spd;
3474
3475 if (lp->useMII) {
3476 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3477 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3478 spd &= lp->phy[lp->active].spd.mask;
3479 } else if (!lp->useSROM) { /* de500-xa */
3480 spd = ((~gep_rd(dev)) & GEP_SLNK);
3481 } else {
3482 if ((lp->ibn == 2) || !lp->asBitValid)
3483 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3484
3485 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3486 (lp->linkOK & ~lp->asBitValid);
3487 }
3488
3489 return spd;
3490}
3491
3492static int
3493is_100_up(struct net_device *dev)
3494{
3495 struct de4x5_private *lp = netdev_priv(dev);
3496 u_long iobase = dev->base_addr;
3497
3498 if (lp->useMII) {
3499 /* Double read for sticky bits & temporary drops */
3500 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3501 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3502 } else if (!lp->useSROM) { /* de500-xa */
3503 return (~gep_rd(dev)) & GEP_SLNK;
3504 } else {
3505 if ((lp->ibn == 2) || !lp->asBitValid)
3506 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3507
3508 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3509 (lp->linkOK & ~lp->asBitValid);
3510 }
3511}
3512
3513static int
3514is_10_up(struct net_device *dev)
3515{
3516 struct de4x5_private *lp = netdev_priv(dev);
3517 u_long iobase = dev->base_addr;
3518
3519 if (lp->useMII) {
3520 /* Double read for sticky bits & temporary drops */
3521 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3522 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3523 } else if (!lp->useSROM) { /* de500-xa */
3524 return (~gep_rd(dev)) & GEP_LNP;
3525 } else {
3526 if ((lp->ibn == 2) || !lp->asBitValid)
3527 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3528 (~inl(DE4X5_SISR)&SISR_LS10):
3529 0;
3530
3531 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3532 (lp->linkOK & ~lp->asBitValid);
3533 }
3534}
3535
3536static int
3537is_anc_capable(struct net_device *dev)
3538{
3539 struct de4x5_private *lp = netdev_priv(dev);
3540 u_long iobase = dev->base_addr;
3541
3542 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3543 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3544 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3545 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3546 } else {
3547 return 0;
3548 }
3549}
3550
3551/*
3552** Send a packet onto the media and watch for send errors that indicate the
3553** media is bad or unconnected.
3554*/
3555static int
3556ping_media(struct net_device *dev, int msec)
3557{
3558 struct de4x5_private *lp = netdev_priv(dev);
3559 u_long iobase = dev->base_addr;
3560 int sisr;
3561
3562 if (lp->timeout < 0) {
3563 lp->timeout = msec/100;
3564
3565 lp->tmp = lp->tx_new; /* Remember the ring position */
3566 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3567 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3568 outl(POLL_DEMAND, DE4X5_TPD);
3569 }
3570
3571 sisr = inl(DE4X5_SISR);
3572
3573 if ((!(sisr & SISR_NCR)) &&
3574 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3575 (--lp->timeout)) {
3576 sisr = 100 | TIMER_CB;
3577 } else {
3578 if ((!(sisr & SISR_NCR)) &&
3579 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3580 lp->timeout) {
3581 sisr = 0;
3582 } else {
3583 sisr = 1;
3584 }
3585 lp->timeout = -1;
3586 }
3587
3588 return sisr;
3589}
3590
3591/*
3592** This function does 2 things: on Intels it kmalloc's another buffer to
3593** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3594** into which the packet is copied.
3595*/
3596static struct sk_buff *
3597de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3598{
3599 struct de4x5_private *lp = netdev_priv(dev);
3600 struct sk_buff *p;
3601
3602#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3603 struct sk_buff *ret;
3604 u_long i=0, tmp;
3605
3606 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3607 if (!p) return NULL;
3608
3609 tmp = virt_to_bus(p->data);
3610 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3611 skb_reserve(p, i);
3612 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3613
3614 ret = lp->rx_skb[index];
3615 lp->rx_skb[index] = p;
3616
3617 if ((u_long) ret > 1) {
3618 skb_put(ret, len);
3619 }
3620
3621 return ret;
3622
3623#else
3624 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3625
3626 p = dev_alloc_skb(len + 2);
3627 if (!p) return NULL;
3628
3629 skb_reserve(p, 2); /* Align */
3630 if (index < lp->rx_old) { /* Wrapped buffer */
3631 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3632 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3633 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3634 } else { /* Linear buffer */
3635 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3636 }
3637
3638 return p;
3639#endif
3640}
3641
3642static void
3643de4x5_free_rx_buffs(struct net_device *dev)
3644{
3645 struct de4x5_private *lp = netdev_priv(dev);
3646 int i;
3647
3648 for (i=0; i<lp->rxRingSize; i++) {
3649 if ((u_long) lp->rx_skb[i] > 1) {
3650 dev_kfree_skb(lp->rx_skb[i]);
3651 }
3652 lp->rx_ring[i].status = 0;
3653 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3654 }
3655}
3656
3657static void
3658de4x5_free_tx_buffs(struct net_device *dev)
3659{
3660 struct de4x5_private *lp = netdev_priv(dev);
3661 int i;
3662
3663 for (i=0; i<lp->txRingSize; i++) {
3664 if (lp->tx_skb[i])
3665 de4x5_free_tx_buff(lp, i);
3666 lp->tx_ring[i].status = 0;
3667 }
3668
3669 /* Unload the locally queued packets */
3670 __skb_queue_purge(&lp->cache.queue);
3671}
3672
3673/*
3674** When a user pulls a connection, the DECchip can end up in a
3675** 'running - waiting for end of transmission' state. This means that we
3676** have to perform a chip soft reset to ensure that we can synchronize
3677** the hardware and software and make any media probes using a loopback
3678** packet meaningful.
3679*/
3680static void
3681de4x5_save_skbs(struct net_device *dev)
3682{
3683 struct de4x5_private *lp = netdev_priv(dev);
3684 u_long iobase = dev->base_addr;
3685 s32 omr;
3686
3687 if (!lp->cache.save_cnt) {
3688 STOP_DE4X5;
3689 de4x5_tx(dev); /* Flush any sent skb's */
3690 de4x5_free_tx_buffs(dev);
3691 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3692 de4x5_sw_reset(dev);
3693 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3694 lp->cache.save_cnt++;
3695 START_DE4X5;
3696 }
3697}
3698
3699static void
3700de4x5_rst_desc_ring(struct net_device *dev)
3701{
3702 struct de4x5_private *lp = netdev_priv(dev);
3703 u_long iobase = dev->base_addr;
3704 int i;
3705 s32 omr;
3706
3707 if (lp->cache.save_cnt) {
3708 STOP_DE4X5;
3709 outl(lp->dma_rings, DE4X5_RRBA);
3710 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3711 DE4X5_TRBA);
3712
3713 lp->rx_new = lp->rx_old = 0;
3714 lp->tx_new = lp->tx_old = 0;
3715
3716 for (i = 0; i < lp->rxRingSize; i++) {
3717 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3718 }
3719
3720 for (i = 0; i < lp->txRingSize; i++) {
3721 lp->tx_ring[i].status = cpu_to_le32(0);
3722 }
3723
3724 barrier();
3725 lp->cache.save_cnt--;
3726 START_DE4X5;
3727 }
3728}
3729
3730static void
3731de4x5_cache_state(struct net_device *dev, int flag)
3732{
3733 struct de4x5_private *lp = netdev_priv(dev);
3734 u_long iobase = dev->base_addr;
3735
3736 switch(flag) {
3737 case DE4X5_SAVE_STATE:
3738 lp->cache.csr0 = inl(DE4X5_BMR);
3739 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3740 lp->cache.csr7 = inl(DE4X5_IMR);
3741 break;
3742
3743 case DE4X5_RESTORE_STATE:
3744 outl(lp->cache.csr0, DE4X5_BMR);
3745 outl(lp->cache.csr6, DE4X5_OMR);
3746 outl(lp->cache.csr7, DE4X5_IMR);
3747 if (lp->chipset == DC21140) {
3748 gep_wr(lp->cache.gepc, dev);
3749 gep_wr(lp->cache.gep, dev);
3750 } else {
3751 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3752 lp->cache.csr15);
3753 }
3754 break;
3755 }
3756}
3757
3758static void
3759de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3760{
3761 struct de4x5_private *lp = netdev_priv(dev);
3762
3763 __skb_queue_tail(&lp->cache.queue, skb);
3764}
3765
3766static void
3767de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3768{
3769 struct de4x5_private *lp = netdev_priv(dev);
3770
3771 __skb_queue_head(&lp->cache.queue, skb);
3772}
3773
3774static struct sk_buff *
3775de4x5_get_cache(struct net_device *dev)
3776{
3777 struct de4x5_private *lp = netdev_priv(dev);
3778
3779 return __skb_dequeue(&lp->cache.queue);
3780}
3781
3782/*
3783** Check the Auto Negotiation State. Return OK when a link pass interrupt
3784** is received and the auto-negotiation status is NWAY OK.
3785*/
3786static int
3787test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3788{
3789 struct de4x5_private *lp = netdev_priv(dev);
3790 u_long iobase = dev->base_addr;
3791 s32 sts, ans;
3792
3793 if (lp->timeout < 0) {
3794 lp->timeout = msec/100;
3795 outl(irq_mask, DE4X5_IMR);
3796
3797 /* clear all pending interrupts */
3798 sts = inl(DE4X5_STS);
3799 outl(sts, DE4X5_STS);
3800 }
3801
3802 ans = inl(DE4X5_SISR) & SISR_ANS;
3803 sts = inl(DE4X5_STS) & ~TIMER_CB;
3804
3805 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3806 sts = 100 | TIMER_CB;
3807 } else {
3808 lp->timeout = -1;
3809 }
3810
3811 return sts;
3812}
3813
3814static void
3815de4x5_setup_intr(struct net_device *dev)
3816{
3817 struct de4x5_private *lp = netdev_priv(dev);
3818 u_long iobase = dev->base_addr;
3819 s32 imr, sts;
3820
3821 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3822 imr = 0;
3823 UNMASK_IRQs;
3824 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3825 outl(sts, DE4X5_STS);
3826 ENABLE_IRQs;
3827 }
3828}
3829
3830/*
3831**
3832*/
3833static void
3834reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3835{
3836 struct de4x5_private *lp = netdev_priv(dev);
3837 u_long iobase = dev->base_addr;
3838
3839 RESET_SIA;
3840 if (lp->useSROM) {
3841 if (lp->ibn == 3) {
3842 srom_exec(dev, lp->phy[lp->active].rst);
3843 srom_exec(dev, lp->phy[lp->active].gep);
3844 outl(1, DE4X5_SICR);
3845 return;
3846 } else {
3847 csr15 = lp->cache.csr15;
3848 csr14 = lp->cache.csr14;
3849 csr13 = lp->cache.csr13;
3850 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3851 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3852 }
3853 } else {
3854 outl(csr15, DE4X5_SIGR);
3855 }
3856 outl(csr14, DE4X5_STRR);
3857 outl(csr13, DE4X5_SICR);
3858
3859 mdelay(10);
3860}
3861
3862/*
3863** Create a loopback ethernet packet
3864*/
3865static void
3866create_packet(struct net_device *dev, char *frame, int len)
3867{
3868 int i;
3869 char *buf = frame;
3870
3871 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3872 *buf++ = dev->dev_addr[i];
3873 }
3874 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3875 *buf++ = dev->dev_addr[i];
3876 }
3877
3878 *buf++ = 0; /* Packet length (2 bytes) */
3879 *buf++ = 1;
3880}
3881
3882/*
3883** Look for a particular board name in the EISA configuration space
3884*/
3885static int
3886EISA_signature(char *name, struct device *device)
3887{
3888 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3889 struct eisa_device *edev;
3890
3891 *name = '\0';
3892 edev = to_eisa_device (device);
3893 i = edev->id.driver_data;
3894
3895 if (i >= 0 && i < siglen) {
3896 strcpy (name, de4x5_signatures[i]);
3897 status = 1;
3898 }
3899
3900 return status; /* return the device name string */
3901}
3902
3903/*
3904** Look for a particular board name in the PCI configuration space
3905*/
3906static int
3907PCI_signature(char *name, struct de4x5_private *lp)
3908{
3909 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3910
3911 if (lp->chipset == DC21040) {
3912 strcpy(name, "DE434/5");
3913 return status;
3914 } else { /* Search for a DEC name in the SROM */
3915 int tmp = *((char *)&lp->srom + 19) * 3;
3916 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3917 }
3918 name[8] = '\0';
3919 for (i=0; i<siglen; i++) {
3920 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3921 }
3922 if (i == siglen) {
3923 if (dec_only) {
3924 *name = '\0';
3925 } else { /* Use chip name to avoid confusion */
3926 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3927 ((lp->chipset == DC21041) ? "DC21041" :
3928 ((lp->chipset == DC21140) ? "DC21140" :
3929 ((lp->chipset == DC21142) ? "DC21142" :
3930 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3931 )))))));
3932 }
3933 if (lp->chipset != DC21041) {
3934 lp->useSROM = true; /* card is not recognisably DEC */
3935 }
3936 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3937 lp->useSROM = true;
3938 }
3939
3940 return status;
3941}
3942
3943/*
3944** Set up the Ethernet PROM counter to the start of the Ethernet address on
3945** the DC21040, else read the SROM for the other chips.
3946** The SROM may not be present in a multi-MAC card, so first read the
3947** MAC address and check for a bad address. If there is a bad one then exit
3948** immediately with the prior srom contents intact (the h/w address will
3949** be fixed up later).
3950*/
3951static void
3952DevicePresent(struct net_device *dev, u_long aprom_addr)
3953{
3954 int i, j=0;
3955 struct de4x5_private *lp = netdev_priv(dev);
3956
3957 if (lp->chipset == DC21040) {
3958 if (lp->bus == EISA) {
3959 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3960 } else {
3961 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3962 }
3963 } else { /* Read new srom */
3964 u_short tmp;
3965 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3966 for (i=0; i<(ETH_ALEN>>1); i++) {
3967 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3968 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3969 *p = cpu_to_le16(tmp);
3970 }
3971 if (j == 0 || j == 3 * 0xffff) {
3972 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
3973 return;
3974 }
3975
3976 p = (__le16 *)&lp->srom;
3977 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3978 tmp = srom_rd(aprom_addr, i);
3979 *p++ = cpu_to_le16(tmp);
3980 }
3981 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
3982 }
3983}
3984
3985/*
3986** Since the write on the Enet PROM register doesn't seem to reset the PROM
3987** pointer correctly (at least on my DE425 EISA card), this routine should do
3988** it...from depca.c.
3989*/
3990static void
3991enet_addr_rst(u_long aprom_addr)
3992{
3993 union {
3994 struct {
3995 u32 a;
3996 u32 b;
3997 } llsig;
3998 char Sig[sizeof(u32) << 1];
3999 } dev;
4000 short sigLength=0;
4001 s8 data;
4002 int i, j;
4003
4004 dev.llsig.a = ETH_PROM_SIG;
4005 dev.llsig.b = ETH_PROM_SIG;
4006 sigLength = sizeof(u32) << 1;
4007
4008 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4009 data = inb(aprom_addr);
4010 if (dev.Sig[j] == data) { /* track signature */
4011 j++;
4012 } else { /* lost signature; begin search again */
4013 if (data == dev.Sig[0]) { /* rare case.... */
4014 j=1;
4015 } else {
4016 j=0;
4017 }
4018 }
4019 }
4020}
4021
4022/*
4023** For the bad status case and no SROM, then add one to the previous
4024** address. However, need to add one backwards in case we have 0xff
4025** as one or more of the bytes. Only the last 3 bytes should be checked
4026** as the first three are invariant - assigned to an organisation.
4027*/
4028static int
4029get_hw_addr(struct net_device *dev)
4030{
4031 u_long iobase = dev->base_addr;
4032 int broken, i, k, tmp, status = 0;
4033 u_short j,chksum;
4034 struct de4x5_private *lp = netdev_priv(dev);
4035
4036 broken = de4x5_bad_srom(lp);
4037
4038 for (i=0,k=0,j=0;j<3;j++) {
4039 k <<= 1;
4040 if (k > 0xffff) k-=0xffff;
4041
4042 if (lp->bus == PCI) {
4043 if (lp->chipset == DC21040) {
4044 while ((tmp = inl(DE4X5_APROM)) < 0);
4045 k += (u_char) tmp;
4046 dev->dev_addr[i++] = (u_char) tmp;
4047 while ((tmp = inl(DE4X5_APROM)) < 0);
4048 k += (u_short) (tmp << 8);
4049 dev->dev_addr[i++] = (u_char) tmp;
4050 } else if (!broken) {
4051 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4052 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4053 } else if ((broken == SMC) || (broken == ACCTON)) {
4054 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4055 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4056 }
4057 } else {
4058 k += (u_char) (tmp = inb(EISA_APROM));
4059 dev->dev_addr[i++] = (u_char) tmp;
4060 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4061 dev->dev_addr[i++] = (u_char) tmp;
4062 }
4063
4064 if (k > 0xffff) k-=0xffff;
4065 }
4066 if (k == 0xffff) k=0;
4067
4068 if (lp->bus == PCI) {
4069 if (lp->chipset == DC21040) {
4070 while ((tmp = inl(DE4X5_APROM)) < 0);
4071 chksum = (u_char) tmp;
4072 while ((tmp = inl(DE4X5_APROM)) < 0);
4073 chksum |= (u_short) (tmp << 8);
4074 if ((k != chksum) && (dec_only)) status = -1;
4075 }
4076 } else {
4077 chksum = (u_char) inb(EISA_APROM);
4078 chksum |= (u_short) (inb(EISA_APROM) << 8);
4079 if ((k != chksum) && (dec_only)) status = -1;
4080 }
4081
4082 /* If possible, try to fix a broken card - SMC only so far */
4083 srom_repair(dev, broken);
4084
4085#ifdef CONFIG_PPC_PMAC
4086 /*
4087 ** If the address starts with 00 a0, we have to bit-reverse
4088 ** each byte of the address.
4089 */
4090 if ( machine_is(powermac) &&
4091 (dev->dev_addr[0] == 0) &&
4092 (dev->dev_addr[1] == 0xa0) )
4093 {
4094 for (i = 0; i < ETH_ALEN; ++i)
4095 {
4096 int x = dev->dev_addr[i];
4097 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4098 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4099 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4100 }
4101 }
4102#endif /* CONFIG_PPC_PMAC */
4103
4104 /* Test for a bad enet address */
4105 status = test_bad_enet(dev, status);
4106
4107 return status;
4108}
4109
4110/*
4111** Test for enet addresses in the first 32 bytes. The built-in strncmp
4112** didn't seem to work here...?
4113*/
4114static int
4115de4x5_bad_srom(struct de4x5_private *lp)
4116{
4117 int i, status = 0;
4118
4119 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4120 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4121 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4122 if (i == 0) {
4123 status = SMC;
4124 } else if (i == 1) {
4125 status = ACCTON;
4126 }
4127 break;
4128 }
4129 }
4130
4131 return status;
4132}
4133
4134static int
4135de4x5_strncmp(char *a, char *b, int n)
4136{
4137 int ret=0;
4138
4139 for (;n && !ret; n--) {
4140 ret = *a++ - *b++;
4141 }
4142
4143 return ret;
4144}
4145
4146static void
4147srom_repair(struct net_device *dev, int card)
4148{
4149 struct de4x5_private *lp = netdev_priv(dev);
4150
4151 switch(card) {
4152 case SMC:
4153 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4154 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4155 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4156 lp->useSROM = true;
4157 break;
4158 }
4159}
4160
4161/*
4162** Assume that the irq's do not follow the PCI spec - this is seems
4163** to be true so far (2 for 2).
4164*/
4165static int
4166test_bad_enet(struct net_device *dev, int status)
4167{
4168 struct de4x5_private *lp = netdev_priv(dev);
4169 int i, tmp;
4170
4171 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4172 if ((tmp == 0) || (tmp == 0x5fa)) {
4173 if ((lp->chipset == last.chipset) &&
4174 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4175 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4176 for (i=ETH_ALEN-1; i>2; --i) {
4177 dev->dev_addr[i] += 1;
4178 if (dev->dev_addr[i] != 0) break;
4179 }
4180 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4181 if (!an_exception(lp)) {
4182 dev->irq = last.irq;
4183 }
4184
4185 status = 0;
4186 }
4187 } else if (!status) {
4188 last.chipset = lp->chipset;
4189 last.bus = lp->bus_num;
4190 last.irq = dev->irq;
4191 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4192 }
4193
4194 return status;
4195}
4196
4197/*
4198** List of board exceptions with correctly wired IRQs
4199*/
4200static int
4201an_exception(struct de4x5_private *lp)
4202{
4203 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4204 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4205 return -1;
4206 }
4207
4208 return 0;
4209}
4210
4211/*
4212** SROM Read
4213*/
4214static short
4215srom_rd(u_long addr, u_char offset)
4216{
4217 sendto_srom(SROM_RD | SROM_SR, addr);
4218
4219 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4220 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4221 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4222
4223 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4224}
4225
4226static void
4227srom_latch(u_int command, u_long addr)
4228{
4229 sendto_srom(command, addr);
4230 sendto_srom(command | DT_CLK, addr);
4231 sendto_srom(command, addr);
4232}
4233
4234static void
4235srom_command(u_int command, u_long addr)
4236{
4237 srom_latch(command, addr);
4238 srom_latch(command, addr);
4239 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4240}
4241
4242static void
4243srom_address(u_int command, u_long addr, u_char offset)
4244{
4245 int i, a;
4246
4247 a = offset << 2;
4248 for (i=0; i<6; i++, a <<= 1) {
4249 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4250 }
4251 udelay(1);
4252
4253 i = (getfrom_srom(addr) >> 3) & 0x01;
4254}
4255
4256static short
4257srom_data(u_int command, u_long addr)
4258{
4259 int i;
4260 short word = 0;
4261 s32 tmp;
4262
4263 for (i=0; i<16; i++) {
4264 sendto_srom(command | DT_CLK, addr);
4265 tmp = getfrom_srom(addr);
4266 sendto_srom(command, addr);
4267
4268 word = (word << 1) | ((tmp >> 3) & 0x01);
4269 }
4270
4271 sendto_srom(command & 0x0000ff00, addr);
4272
4273 return word;
4274}
4275
4276/*
4277static void
4278srom_busy(u_int command, u_long addr)
4279{
4280 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4281
4282 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4283 mdelay(1);
4284 }
4285
4286 sendto_srom(command & 0x0000ff00, addr);
4287}
4288*/
4289
4290static void
4291sendto_srom(u_int command, u_long addr)
4292{
4293 outl(command, addr);
4294 udelay(1);
4295}
4296
4297static int
4298getfrom_srom(u_long addr)
4299{
4300 s32 tmp;
4301
4302 tmp = inl(addr);
4303 udelay(1);
4304
4305 return tmp;
4306}
4307
4308static int
4309srom_infoleaf_info(struct net_device *dev)
4310{
4311 struct de4x5_private *lp = netdev_priv(dev);
4312 int i, count;
4313 u_char *p;
4314
4315 /* Find the infoleaf decoder function that matches this chipset */
4316 for (i=0; i<INFOLEAF_SIZE; i++) {
4317 if (lp->chipset == infoleaf_array[i].chipset) break;
4318 }
4319 if (i == INFOLEAF_SIZE) {
4320 lp->useSROM = false;
4321 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4322 dev->name);
4323 return -ENXIO;
4324 }
4325
4326 lp->infoleaf_fn = infoleaf_array[i].fn;
4327
4328 /* Find the information offset that this function should use */
4329 count = *((u_char *)&lp->srom + 19);
4330 p = (u_char *)&lp->srom + 26;
4331
4332 if (count > 1) {
4333 for (i=count; i; --i, p+=3) {
4334 if (lp->device == *p) break;
4335 }
4336 if (i == 0) {
4337 lp->useSROM = false;
4338 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4339 dev->name, lp->device);
4340 return -ENXIO;
4341 }
4342 }
4343
4344 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4345
4346 return 0;
4347}
4348
4349/*
4350** This routine loads any type 1 or 3 MII info into the mii device
4351** struct and executes any type 5 code to reset PHY devices for this
4352** controller.
4353** The info for the MII devices will be valid since the index used
4354** will follow the discovery process from MII address 1-31 then 0.
4355*/
4356static void
4357srom_init(struct net_device *dev)
4358{
4359 struct de4x5_private *lp = netdev_priv(dev);
4360 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4361 u_char count;
4362
4363 p+=2;
4364 if (lp->chipset == DC21140) {
4365 lp->cache.gepc = (*p++ | GEP_CTRL);
4366 gep_wr(lp->cache.gepc, dev);
4367 }
4368
4369 /* Block count */
4370 count = *p++;
4371
4372 /* Jump the infoblocks to find types */
4373 for (;count; --count) {
4374 if (*p < 128) {
4375 p += COMPACT_LEN;
4376 } else if (*(p+1) == 5) {
4377 type5_infoblock(dev, 1, p);
4378 p += ((*p & BLOCK_LEN) + 1);
4379 } else if (*(p+1) == 4) {
4380 p += ((*p & BLOCK_LEN) + 1);
4381 } else if (*(p+1) == 3) {
4382 type3_infoblock(dev, 1, p);
4383 p += ((*p & BLOCK_LEN) + 1);
4384 } else if (*(p+1) == 2) {
4385 p += ((*p & BLOCK_LEN) + 1);
4386 } else if (*(p+1) == 1) {
4387 type1_infoblock(dev, 1, p);
4388 p += ((*p & BLOCK_LEN) + 1);
4389 } else {
4390 p += ((*p & BLOCK_LEN) + 1);
4391 }
4392 }
4393}
4394
4395/*
4396** A generic routine that writes GEP control, data and reset information
4397** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4398*/
4399static void
4400srom_exec(struct net_device *dev, u_char *p)
4401{
4402 struct de4x5_private *lp = netdev_priv(dev);
4403 u_long iobase = dev->base_addr;
4404 u_char count = (p ? *p++ : 0);
4405 u_short *w = (u_short *)p;
4406
4407 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4408
4409 if (lp->chipset != DC21140) RESET_SIA;
4410
4411 while (count--) {
4412 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4413 *p++ : get_unaligned_le16(w++)), dev);
4414 mdelay(2); /* 2ms per action */
4415 }
4416
4417 if (lp->chipset != DC21140) {
4418 outl(lp->cache.csr14, DE4X5_STRR);
4419 outl(lp->cache.csr13, DE4X5_SICR);
4420 }
4421}
4422
4423/*
4424** Basically this function is a NOP since it will never be called,
4425** unless I implement the DC21041 SROM functions. There's no need
4426** since the existing code will be satisfactory for all boards.
4427*/
4428static int
4429dc21041_infoleaf(struct net_device *dev)
4430{
4431 return DE4X5_AUTOSENSE_MS;
4432}
4433
4434static int
4435dc21140_infoleaf(struct net_device *dev)
4436{
4437 struct de4x5_private *lp = netdev_priv(dev);
4438 u_char count = 0;
4439 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4440 int next_tick = DE4X5_AUTOSENSE_MS;
4441
4442 /* Read the connection type */
4443 p+=2;
4444
4445 /* GEP control */
4446 lp->cache.gepc = (*p++ | GEP_CTRL);
4447
4448 /* Block count */
4449 count = *p++;
4450
4451 /* Recursively figure out the info blocks */
4452 if (*p < 128) {
4453 next_tick = dc_infoblock[COMPACT](dev, count, p);
4454 } else {
4455 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4456 }
4457
4458 if (lp->tcount == count) {
4459 lp->media = NC;
4460 if (lp->media != lp->c_media) {
4461 de4x5_dbg_media(dev);
4462 lp->c_media = lp->media;
4463 }
4464 lp->media = INIT;
4465 lp->tcount = 0;
4466 lp->tx_enable = false;
4467 }
4468
4469 return next_tick & ~TIMER_CB;
4470}
4471
4472static int
4473dc21142_infoleaf(struct net_device *dev)
4474{
4475 struct de4x5_private *lp = netdev_priv(dev);
4476 u_char count = 0;
4477 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4478 int next_tick = DE4X5_AUTOSENSE_MS;
4479
4480 /* Read the connection type */
4481 p+=2;
4482
4483 /* Block count */
4484 count = *p++;
4485
4486 /* Recursively figure out the info blocks */
4487 if (*p < 128) {
4488 next_tick = dc_infoblock[COMPACT](dev, count, p);
4489 } else {
4490 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4491 }
4492
4493 if (lp->tcount == count) {
4494 lp->media = NC;
4495 if (lp->media != lp->c_media) {
4496 de4x5_dbg_media(dev);
4497 lp->c_media = lp->media;
4498 }
4499 lp->media = INIT;
4500 lp->tcount = 0;
4501 lp->tx_enable = false;
4502 }
4503
4504 return next_tick & ~TIMER_CB;
4505}
4506
4507static int
4508dc21143_infoleaf(struct net_device *dev)
4509{
4510 struct de4x5_private *lp = netdev_priv(dev);
4511 u_char count = 0;
4512 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4513 int next_tick = DE4X5_AUTOSENSE_MS;
4514
4515 /* Read the connection type */
4516 p+=2;
4517
4518 /* Block count */
4519 count = *p++;
4520
4521 /* Recursively figure out the info blocks */
4522 if (*p < 128) {
4523 next_tick = dc_infoblock[COMPACT](dev, count, p);
4524 } else {
4525 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4526 }
4527 if (lp->tcount == count) {
4528 lp->media = NC;
4529 if (lp->media != lp->c_media) {
4530 de4x5_dbg_media(dev);
4531 lp->c_media = lp->media;
4532 }
4533 lp->media = INIT;
4534 lp->tcount = 0;
4535 lp->tx_enable = false;
4536 }
4537
4538 return next_tick & ~TIMER_CB;
4539}
4540
4541/*
4542** The compact infoblock is only designed for DC21140[A] chips, so
4543** we'll reuse the dc21140m_autoconf function. Non MII media only.
4544*/
4545static int
4546compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4547{
4548 struct de4x5_private *lp = netdev_priv(dev);
4549 u_char flags, csr6;
4550
4551 /* Recursively figure out the info blocks */
4552 if (--count > lp->tcount) {
4553 if (*(p+COMPACT_LEN) < 128) {
4554 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4555 } else {
4556 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4557 }
4558 }
4559
4560 if ((lp->media == INIT) && (lp->timeout < 0)) {
4561 lp->ibn = COMPACT;
4562 lp->active = 0;
4563 gep_wr(lp->cache.gepc, dev);
4564 lp->infoblock_media = (*p++) & COMPACT_MC;
4565 lp->cache.gep = *p++;
4566 csr6 = *p++;
4567 flags = *p++;
4568
4569 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4570 lp->defMedium = (flags & 0x40) ? -1 : 0;
4571 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4572 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4573 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4574 lp->useMII = false;
4575
4576 de4x5_switch_mac_port(dev);
4577 }
4578
4579 return dc21140m_autoconf(dev);
4580}
4581
4582/*
4583** This block describes non MII media for the DC21140[A] only.
4584*/
4585static int
4586type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4587{
4588 struct de4x5_private *lp = netdev_priv(dev);
4589 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4590
4591 /* Recursively figure out the info blocks */
4592 if (--count > lp->tcount) {
4593 if (*(p+len) < 128) {
4594 return dc_infoblock[COMPACT](dev, count, p+len);
4595 } else {
4596 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4597 }
4598 }
4599
4600 if ((lp->media == INIT) && (lp->timeout < 0)) {
4601 lp->ibn = 0;
4602 lp->active = 0;
4603 gep_wr(lp->cache.gepc, dev);
4604 p+=2;
4605 lp->infoblock_media = (*p++) & BLOCK0_MC;
4606 lp->cache.gep = *p++;
4607 csr6 = *p++;
4608 flags = *p++;
4609
4610 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4611 lp->defMedium = (flags & 0x40) ? -1 : 0;
4612 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4613 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4614 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4615 lp->useMII = false;
4616
4617 de4x5_switch_mac_port(dev);
4618 }
4619
4620 return dc21140m_autoconf(dev);
4621}
4622
4623/* These functions are under construction! */
4624
4625static int
4626type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4627{
4628 struct de4x5_private *lp = netdev_priv(dev);
4629 u_char len = (*p & BLOCK_LEN)+1;
4630
4631 /* Recursively figure out the info blocks */
4632 if (--count > lp->tcount) {
4633 if (*(p+len) < 128) {
4634 return dc_infoblock[COMPACT](dev, count, p+len);
4635 } else {
4636 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4637 }
4638 }
4639
4640 p += 2;
4641 if (lp->state == INITIALISED) {
4642 lp->ibn = 1;
4643 lp->active = *p++;
4644 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4645 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4646 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4647 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4648 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4649 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4650 return 0;
4651 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4652 lp->ibn = 1;
4653 lp->active = *p;
4654 lp->infoblock_csr6 = OMR_MII_100;
4655 lp->useMII = true;
4656 lp->infoblock_media = ANS;
4657
4658 de4x5_switch_mac_port(dev);
4659 }
4660
4661 return dc21140m_autoconf(dev);
4662}
4663
4664static int
4665type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4666{
4667 struct de4x5_private *lp = netdev_priv(dev);
4668 u_char len = (*p & BLOCK_LEN)+1;
4669
4670 /* Recursively figure out the info blocks */
4671 if (--count > lp->tcount) {
4672 if (*(p+len) < 128) {
4673 return dc_infoblock[COMPACT](dev, count, p+len);
4674 } else {
4675 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4676 }
4677 }
4678
4679 if ((lp->media == INIT) && (lp->timeout < 0)) {
4680 lp->ibn = 2;
4681 lp->active = 0;
4682 p += 2;
4683 lp->infoblock_media = (*p) & MEDIA_CODE;
4684
4685 if ((*p++) & EXT_FIELD) {
4686 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4687 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4688 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4689 } else {
4690 lp->cache.csr13 = CSR13;
4691 lp->cache.csr14 = CSR14;
4692 lp->cache.csr15 = CSR15;
4693 }
4694 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4695 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4696 lp->infoblock_csr6 = OMR_SIA;
4697 lp->useMII = false;
4698
4699 de4x5_switch_mac_port(dev);
4700 }
4701
4702 return dc2114x_autoconf(dev);
4703}
4704
4705static int
4706type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4707{
4708 struct de4x5_private *lp = netdev_priv(dev);
4709 u_char len = (*p & BLOCK_LEN)+1;
4710
4711 /* Recursively figure out the info blocks */
4712 if (--count > lp->tcount) {
4713 if (*(p+len) < 128) {
4714 return dc_infoblock[COMPACT](dev, count, p+len);
4715 } else {
4716 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4717 }
4718 }
4719
4720 p += 2;
4721 if (lp->state == INITIALISED) {
4722 lp->ibn = 3;
4723 lp->active = *p++;
4724 if (MOTO_SROM_BUG) lp->active = 0;
4725 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4726 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4727 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4728 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4729 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4730 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4731 lp->phy[lp->active].mci = *p;
4732 return 0;
4733 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4734 lp->ibn = 3;
4735 lp->active = *p;
4736 if (MOTO_SROM_BUG) lp->active = 0;
4737 lp->infoblock_csr6 = OMR_MII_100;
4738 lp->useMII = true;
4739 lp->infoblock_media = ANS;
4740
4741 de4x5_switch_mac_port(dev);
4742 }
4743
4744 return dc2114x_autoconf(dev);
4745}
4746
4747static int
4748type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4749{
4750 struct de4x5_private *lp = netdev_priv(dev);
4751 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4752
4753 /* Recursively figure out the info blocks */
4754 if (--count > lp->tcount) {
4755 if (*(p+len) < 128) {
4756 return dc_infoblock[COMPACT](dev, count, p+len);
4757 } else {
4758 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4759 }
4760 }
4761
4762 if ((lp->media == INIT) && (lp->timeout < 0)) {
4763 lp->ibn = 4;
4764 lp->active = 0;
4765 p+=2;
4766 lp->infoblock_media = (*p++) & MEDIA_CODE;
4767 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4768 lp->cache.csr14 = CSR14;
4769 lp->cache.csr15 = CSR15;
4770 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4771 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4772 csr6 = *p++;
4773 flags = *p++;
4774
4775 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4776 lp->defMedium = (flags & 0x40) ? -1 : 0;
4777 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4778 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4779 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4780 lp->useMII = false;
4781
4782 de4x5_switch_mac_port(dev);
4783 }
4784
4785 return dc2114x_autoconf(dev);
4786}
4787
4788/*
4789** This block type provides information for resetting external devices
4790** (chips) through the General Purpose Register.
4791*/
4792static int
4793type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4794{
4795 struct de4x5_private *lp = netdev_priv(dev);
4796 u_char len = (*p & BLOCK_LEN)+1;
4797
4798 /* Recursively figure out the info blocks */
4799 if (--count > lp->tcount) {
4800 if (*(p+len) < 128) {
4801 return dc_infoblock[COMPACT](dev, count, p+len);
4802 } else {
4803 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4804 }
4805 }
4806
4807 /* Must be initializing to run this code */
4808 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4809 p+=2;
4810 lp->rst = p;
4811 srom_exec(dev, lp->rst);
4812 }
4813
4814 return DE4X5_AUTOSENSE_MS;
4815}
4816
4817/*
4818** MII Read/Write
4819*/
4820
4821static int
4822mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4823{
4824 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4825 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4826 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4827 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4828 mii_address(phyreg, ioaddr); /* PHY Register to read */
4829 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4830
4831 return mii_rdata(ioaddr); /* Read data */
4832}
4833
4834static void
4835mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4836{
4837 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4838 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4839 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4840 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4841 mii_address(phyreg, ioaddr); /* PHY Register to write */
4842 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4843 data = mii_swap(data, 16); /* Swap data bit ordering */
4844 mii_wdata(data, 16, ioaddr); /* Write data */
4845}
4846
4847static int
4848mii_rdata(u_long ioaddr)
4849{
4850 int i;
4851 s32 tmp = 0;
4852
4853 for (i=0; i<16; i++) {
4854 tmp <<= 1;
4855 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4856 }
4857
4858 return tmp;
4859}
4860
4861static void
4862mii_wdata(int data, int len, u_long ioaddr)
4863{
4864 int i;
4865
4866 for (i=0; i<len; i++) {
4867 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4868 data >>= 1;
4869 }
4870}
4871
4872static void
4873mii_address(u_char addr, u_long ioaddr)
4874{
4875 int i;
4876
4877 addr = mii_swap(addr, 5);
4878 for (i=0; i<5; i++) {
4879 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4880 addr >>= 1;
4881 }
4882}
4883
4884static void
4885mii_ta(u_long rw, u_long ioaddr)
4886{
4887 if (rw == MII_STWR) {
4888 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4889 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4890 } else {
4891 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4892 }
4893}
4894
4895static int
4896mii_swap(int data, int len)
4897{
4898 int i, tmp = 0;
4899
4900 for (i=0; i<len; i++) {
4901 tmp <<= 1;
4902 tmp |= (data & 1);
4903 data >>= 1;
4904 }
4905
4906 return tmp;
4907}
4908
4909static void
4910sendto_mii(u32 command, int data, u_long ioaddr)
4911{
4912 u32 j;
4913
4914 j = (data & 1) << 17;
4915 outl(command | j, ioaddr);
4916 udelay(1);
4917 outl(command | MII_MDC | j, ioaddr);
4918 udelay(1);
4919}
4920
4921static int
4922getfrom_mii(u32 command, u_long ioaddr)
4923{
4924 outl(command, ioaddr);
4925 udelay(1);
4926 outl(command | MII_MDC, ioaddr);
4927 udelay(1);
4928
4929 return (inl(ioaddr) >> 19) & 1;
4930}
4931
4932/*
4933** Here's 3 ways to calculate the OUI from the ID registers.
4934*/
4935static int
4936mii_get_oui(u_char phyaddr, u_long ioaddr)
4937{
4938/*
4939 union {
4940 u_short reg;
4941 u_char breg[2];
4942 } a;
4943 int i, r2, r3, ret=0;*/
4944 int r2, r3;
4945
4946 /* Read r2 and r3 */
4947 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4948 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4949 /* SEEQ and Cypress way * /
4950 / * Shuffle r2 and r3 * /
4951 a.reg=0;
4952 r3 = ((r3>>10)|(r2<<6))&0x0ff;
4953 r2 = ((r2>>2)&0x3fff);
4954
4955 / * Bit reverse r3 * /
4956 for (i=0;i<8;i++) {
4957 ret<<=1;
4958 ret |= (r3&1);
4959 r3>>=1;
4960 }
4961
4962 / * Bit reverse r2 * /
4963 for (i=0;i<16;i++) {
4964 a.reg<<=1;
4965 a.reg |= (r2&1);
4966 r2>>=1;
4967 }
4968
4969 / * Swap r2 bytes * /
4970 i=a.breg[0];
4971 a.breg[0]=a.breg[1];
4972 a.breg[1]=i;
4973
4974 return (a.reg<<8)|ret; */ /* SEEQ and Cypress way */
4975/* return (r2<<6)|(u_int)(r3>>10); */ /* NATIONAL and BROADCOM way */
4976 return r2; /* (I did it) My way */
4977}
4978
4979/*
4980** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4981*/
4982static int
4983mii_get_phy(struct net_device *dev)
4984{
4985 struct de4x5_private *lp = netdev_priv(dev);
4986 u_long iobase = dev->base_addr;
4987 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4988 int id;
4989
4990 lp->active = 0;
4991 lp->useMII = true;
4992
4993 /* Search the MII address space for possible PHY devices */
4994 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4995 lp->phy[lp->active].addr = i;
4996 if (i==0) n++; /* Count cycles */
4997 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
4998 id = mii_get_oui(i, DE4X5_MII);
4999 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5000 for (j=0; j<limit; j++) { /* Search PHY table */
5001 if (id != phy_info[j].id) continue; /* ID match? */
5002 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5003 if (k < DE4X5_MAX_PHY) {
5004 memcpy((char *)&lp->phy[k],
5005 (char *)&phy_info[j], sizeof(struct phy_table));
5006 lp->phy[k].addr = i;
5007 lp->mii_cnt++;
5008 lp->active++;
5009 } else {
5010 goto purgatory; /* Stop the search */
5011 }
5012 break;
5013 }
5014 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5015 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5016 lp->phy[k].addr = i;
5017 lp->phy[k].id = id;
5018 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5019 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5020 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5021 lp->mii_cnt++;
5022 lp->active++;
5023 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5024 j = de4x5_debug;
5025 de4x5_debug |= DEBUG_MII;
5026 de4x5_dbg_mii(dev, k);
5027 de4x5_debug = j;
5028 printk("\n");
5029 }
5030 }
5031 purgatory:
5032 lp->active = 0;
5033 if (lp->phy[0].id) { /* Reset the PHY devices */
5034 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5035 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5036 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5037
5038 de4x5_dbg_mii(dev, k);
5039 }
5040 }
5041 if (!lp->mii_cnt) lp->useMII = false;
5042
5043 return lp->mii_cnt;
5044}
5045
5046static char *
5047build_setup_frame(struct net_device *dev, int mode)
5048{
5049 struct de4x5_private *lp = netdev_priv(dev);
5050 int i;
5051 char *pa = lp->setup_frame;
5052
5053 /* Initialise the setup frame */
5054 if (mode == ALL) {
5055 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5056 }
5057
5058 if (lp->setup_f == HASH_PERF) {
5059 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5060 *(pa + i) = dev->dev_addr[i]; /* Host address */
5061 if (i & 0x01) pa += 2;
5062 }
5063 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5064 } else {
5065 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5066 *(pa + (i&1)) = dev->dev_addr[i];
5067 if (i & 0x01) pa += 4;
5068 }
5069 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5070 *(pa + (i&1)) = (char) 0xff;
5071 if (i & 0x01) pa += 4;
5072 }
5073 }
5074
5075 return pa; /* Points to the next entry */
5076}
5077
5078static void
5079disable_ast(struct net_device *dev)
5080{
5081 struct de4x5_private *lp = netdev_priv(dev);
5082 del_timer_sync(&lp->timer);
5083}
5084
5085static long
5086de4x5_switch_mac_port(struct net_device *dev)
5087{
5088 struct de4x5_private *lp = netdev_priv(dev);
5089 u_long iobase = dev->base_addr;
5090 s32 omr;
5091
5092 STOP_DE4X5;
5093
5094 /* Assert the OMR_PS bit in CSR6 */
5095 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5096 OMR_FDX));
5097 omr |= lp->infoblock_csr6;
5098 if (omr & OMR_PS) omr |= OMR_HBD;
5099 outl(omr, DE4X5_OMR);
5100
5101 /* Soft Reset */
5102 RESET_DE4X5;
5103
5104 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5105 if (lp->chipset == DC21140) {
5106 gep_wr(lp->cache.gepc, dev);
5107 gep_wr(lp->cache.gep, dev);
5108 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5109 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5110 }
5111
5112 /* Restore CSR6 */
5113 outl(omr, DE4X5_OMR);
5114
5115 /* Reset CSR8 */
5116 inl(DE4X5_MFC);
5117
5118 return omr;
5119}
5120
5121static void
5122gep_wr(s32 data, struct net_device *dev)
5123{
5124 struct de4x5_private *lp = netdev_priv(dev);
5125 u_long iobase = dev->base_addr;
5126
5127 if (lp->chipset == DC21140) {
5128 outl(data, DE4X5_GEP);
5129 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5130 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5131 }
5132}
5133
5134static int
5135gep_rd(struct net_device *dev)
5136{
5137 struct de4x5_private *lp = netdev_priv(dev);
5138 u_long iobase = dev->base_addr;
5139
5140 if (lp->chipset == DC21140) {
5141 return inl(DE4X5_GEP);
5142 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5143 return inl(DE4X5_SIGR) & 0x000fffff;
5144 }
5145
5146 return 0;
5147}
5148
5149static void
5150yawn(struct net_device *dev, int state)
5151{
5152 struct de4x5_private *lp = netdev_priv(dev);
5153 u_long iobase = dev->base_addr;
5154
5155 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5156
5157 if(lp->bus == EISA) {
5158 switch(state) {
5159 case WAKEUP:
5160 outb(WAKEUP, PCI_CFPM);
5161 mdelay(10);
5162 break;
5163
5164 case SNOOZE:
5165 outb(SNOOZE, PCI_CFPM);
5166 break;
5167
5168 case SLEEP:
5169 outl(0, DE4X5_SICR);
5170 outb(SLEEP, PCI_CFPM);
5171 break;
5172 }
5173 } else {
5174 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5175 switch(state) {
5176 case WAKEUP:
5177 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5178 mdelay(10);
5179 break;
5180
5181 case SNOOZE:
5182 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5183 break;
5184
5185 case SLEEP:
5186 outl(0, DE4X5_SICR);
5187 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5188 break;
5189 }
5190 }
5191}
5192
5193static void
5194de4x5_parse_params(struct net_device *dev)
5195{
5196 struct de4x5_private *lp = netdev_priv(dev);
5197 char *p, *q, t;
5198
5199 lp->params.fdx = 0;
5200 lp->params.autosense = AUTO;
5201
5202 if (args == NULL) return;
5203
5204 if ((p = strstr(args, dev->name))) {
5205 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5206 t = *q;
5207 *q = '\0';
5208
5209 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5210
5211 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5212 if (strstr(p, "TP")) {
5213 lp->params.autosense = TP;
5214 } else if (strstr(p, "TP_NW")) {
5215 lp->params.autosense = TP_NW;
5216 } else if (strstr(p, "BNC")) {
5217 lp->params.autosense = BNC;
5218 } else if (strstr(p, "AUI")) {
5219 lp->params.autosense = AUI;
5220 } else if (strstr(p, "BNC_AUI")) {
5221 lp->params.autosense = BNC;
5222 } else if (strstr(p, "10Mb")) {
5223 lp->params.autosense = _10Mb;
5224 } else if (strstr(p, "100Mb")) {
5225 lp->params.autosense = _100Mb;
5226 } else if (strstr(p, "AUTO")) {
5227 lp->params.autosense = AUTO;
5228 }
5229 }
5230 *q = t;
5231 }
5232}
5233
5234static void
5235de4x5_dbg_open(struct net_device *dev)
5236{
5237 struct de4x5_private *lp = netdev_priv(dev);
5238 int i;
5239
5240 if (de4x5_debug & DEBUG_OPEN) {
5241 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5242 printk("\tphysical address: ");
5243 for (i=0;i<6;i++) {
5244 printk("%2.2x:",(short)dev->dev_addr[i]);
5245 }
5246 printk("\n");
5247 printk("Descriptor head addresses:\n");
5248 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5249 printk("Descriptor addresses:\nRX: ");
5250 for (i=0;i<lp->rxRingSize-1;i++){
5251 if (i < 3) {
5252 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5253 }
5254 }
5255 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5256 printk("TX: ");
5257 for (i=0;i<lp->txRingSize-1;i++){
5258 if (i < 3) {
5259 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5260 }
5261 }
5262 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5263 printk("Descriptor buffers:\nRX: ");
5264 for (i=0;i<lp->rxRingSize-1;i++){
5265 if (i < 3) {
5266 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5267 }
5268 }
5269 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5270 printk("TX: ");
5271 for (i=0;i<lp->txRingSize-1;i++){
5272 if (i < 3) {
5273 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5274 }
5275 }
5276 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5277 printk("Ring size:\nRX: %d\nTX: %d\n",
5278 (short)lp->rxRingSize,
5279 (short)lp->txRingSize);
5280 }
5281}
5282
5283static void
5284de4x5_dbg_mii(struct net_device *dev, int k)
5285{
5286 struct de4x5_private *lp = netdev_priv(dev);
5287 u_long iobase = dev->base_addr;
5288
5289 if (de4x5_debug & DEBUG_MII) {
5290 printk("\nMII device address: %d\n", lp->phy[k].addr);
5291 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5292 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5293 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5294 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5295 if (lp->phy[k].id != BROADCOM_T4) {
5296 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5297 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5298 }
5299 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5300 if (lp->phy[k].id != BROADCOM_T4) {
5301 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5302 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5303 } else {
5304 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5305 }
5306 }
5307}
5308
5309static void
5310de4x5_dbg_media(struct net_device *dev)
5311{
5312 struct de4x5_private *lp = netdev_priv(dev);
5313
5314 if (lp->media != lp->c_media) {
5315 if (de4x5_debug & DEBUG_MEDIA) {
5316 printk("%s: media is %s%s\n", dev->name,
5317 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5318 (lp->media == TP ? "TP" :
5319 (lp->media == ANS ? "TP/Nway" :
5320 (lp->media == BNC ? "BNC" :
5321 (lp->media == AUI ? "AUI" :
5322 (lp->media == BNC_AUI ? "BNC/AUI" :
5323 (lp->media == EXT_SIA ? "EXT SIA" :
5324 (lp->media == _100Mb ? "100Mb/s" :
5325 (lp->media == _10Mb ? "10Mb/s" :
5326 "???"
5327 ))))))))), (lp->fdx?" full duplex.":"."));
5328 }
5329 lp->c_media = lp->media;
5330 }
5331}
5332
5333static void
5334de4x5_dbg_srom(struct de4x5_srom *p)
5335{
5336 int i;
5337
5338 if (de4x5_debug & DEBUG_SROM) {
5339 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5340 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5341 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5342 printk("SROM version: %02x\n", (u_char)(p->version));
5343 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5344
5345 printk("Hardware Address: %pM\n", p->ieee_addr);
5346 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5347 for (i=0; i<64; i++) {
5348 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5349 }
5350 }
5351}
5352
5353static void
5354de4x5_dbg_rx(struct sk_buff *skb, int len)
5355{
5356 int i, j;
5357
5358 if (de4x5_debug & DEBUG_RX) {
5359 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5360 skb->data, &skb->data[6],
5361 (u_char)skb->data[12],
5362 (u_char)skb->data[13],
5363 len);
5364 for (j=0; len>0;j+=16, len-=16) {
5365 printk(" %03x: ",j);
5366 for (i=0; i<16 && i<len; i++) {
5367 printk("%02x ",(u_char)skb->data[i+j]);
5368 }
5369 printk("\n");
5370 }
5371 }
5372}
5373
5374/*
5375** Perform IOCTL call functions here. Some are privileged operations and the
5376** effective uid is checked in those cases. In the normal course of events
5377** this function is only used for my testing.
5378*/
5379static int
5380de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5381{
5382 struct de4x5_private *lp = netdev_priv(dev);
5383 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5384 u_long iobase = dev->base_addr;
5385 int i, j, status = 0;
5386 s32 omr;
5387 union {
5388 u8 addr[144];
5389 u16 sval[72];
5390 u32 lval[36];
5391 } tmp;
5392 u_long flags = 0;
5393
5394 switch(ioc->cmd) {
5395 case DE4X5_GET_HWADDR: /* Get the hardware address */
5396 ioc->len = ETH_ALEN;
5397 for (i=0; i<ETH_ALEN; i++) {
5398 tmp.addr[i] = dev->dev_addr[i];
5399 }
5400 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5401 break;
5402
5403 case DE4X5_SET_HWADDR: /* Set the hardware address */
5404 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5405 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5406 if (netif_queue_stopped(dev))
5407 return -EBUSY;
5408 netif_stop_queue(dev);
5409 for (i=0; i<ETH_ALEN; i++) {
5410 dev->dev_addr[i] = tmp.addr[i];
5411 }
5412 build_setup_frame(dev, PHYS_ADDR_ONLY);
5413 /* Set up the descriptor and give ownership to the card */
5414 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5415 SETUP_FRAME_LEN, (struct sk_buff *)1);
5416 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5417 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5418 netif_wake_queue(dev); /* Unlock the TX ring */
5419 break;
5420
5421 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5422 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5423 printk("%s: Boo!\n", dev->name);
5424 break;
5425
5426 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5427 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5428 omr = inl(DE4X5_OMR);
5429 omr |= OMR_PM;
5430 outl(omr, DE4X5_OMR);
5431 break;
5432
5433 case DE4X5_GET_STATS: /* Get the driver statistics */
5434 {
5435 struct pkt_stats statbuf;
5436 ioc->len = sizeof(statbuf);
5437 spin_lock_irqsave(&lp->lock, flags);
5438 memcpy(&statbuf, &lp->pktStats, ioc->len);
5439 spin_unlock_irqrestore(&lp->lock, flags);
5440 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5441 return -EFAULT;
5442 break;
5443 }
5444 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5445 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5446 spin_lock_irqsave(&lp->lock, flags);
5447 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5448 spin_unlock_irqrestore(&lp->lock, flags);
5449 break;
5450
5451 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5452 tmp.addr[0] = inl(DE4X5_OMR);
5453 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5454 break;
5455
5456 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5457 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5458 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5459 outl(tmp.addr[0], DE4X5_OMR);
5460 break;
5461
5462 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5463 j = 0;
5464 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5465 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5466 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5467 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5468 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5469 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5470 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5471 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5472 ioc->len = j;
5473 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5474 return -EFAULT;
5475 break;
5476
5477#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5478/*
5479 case DE4X5_DUMP:
5480 j = 0;
5481 tmp.addr[j++] = dev->irq;
5482 for (i=0; i<ETH_ALEN; i++) {
5483 tmp.addr[j++] = dev->dev_addr[i];
5484 }
5485 tmp.addr[j++] = lp->rxRingSize;
5486 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5487 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5488
5489 for (i=0;i<lp->rxRingSize-1;i++){
5490 if (i < 3) {
5491 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5492 }
5493 }
5494 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5495 for (i=0;i<lp->txRingSize-1;i++){
5496 if (i < 3) {
5497 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5498 }
5499 }
5500 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5501
5502 for (i=0;i<lp->rxRingSize-1;i++){
5503 if (i < 3) {
5504 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5505 }
5506 }
5507 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5508 for (i=0;i<lp->txRingSize-1;i++){
5509 if (i < 3) {
5510 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5511 }
5512 }
5513 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5514
5515 for (i=0;i<lp->rxRingSize;i++){
5516 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5517 }
5518 for (i=0;i<lp->txRingSize;i++){
5519 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5520 }
5521
5522 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5523 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5524 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5525 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5526 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5527 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5528 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5529 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5530 tmp.lval[j>>2] = lp->chipset; j+=4;
5531 if (lp->chipset == DC21140) {
5532 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5533 } else {
5534 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5535 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5536 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5537 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5538 }
5539 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5540 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5541 tmp.lval[j>>2] = lp->active; j+=4;
5542 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5543 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5544 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5545 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5546 if (lp->phy[lp->active].id != BROADCOM_T4) {
5547 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5548 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5549 }
5550 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5551 if (lp->phy[lp->active].id != BROADCOM_T4) {
5552 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5553 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5554 } else {
5555 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5556 }
5557 }
5558
5559 tmp.addr[j++] = lp->txRingSize;
5560 tmp.addr[j++] = netif_queue_stopped(dev);
5561
5562 ioc->len = j;
5563 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5564 break;
5565
5566*/
5567 default:
5568 return -EOPNOTSUPP;
5569 }
5570
5571 return status;
5572}
5573
5574static int __init de4x5_module_init (void)
5575{
5576 int err = 0;
5577
5578#ifdef CONFIG_PCI
5579 err = pci_register_driver(&de4x5_pci_driver);
5580#endif
5581#ifdef CONFIG_EISA
5582 err |= eisa_driver_register (&de4x5_eisa_driver);
5583#endif
5584
5585 return err;
5586}
5587
5588static void __exit de4x5_module_exit (void)
5589{
5590#ifdef CONFIG_PCI
5591 pci_unregister_driver (&de4x5_pci_driver);
5592#endif
5593#ifdef CONFIG_EISA
5594 eisa_driver_unregister (&de4x5_eisa_driver);
5595#endif
5596}
5597
5598module_init (de4x5_module_init);
5599module_exit (de4x5_module_exit);