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1/*
2 * Tehuti Networks(R) Network Driver
3 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef _TEHUTI_H
12#define _TEHUTI_H
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/ethtool.h>
21#include <linux/mii.h>
22#include <linux/crc32.h>
23#include <linux/uaccess.h>
24#include <linux/in.h>
25#include <linux/ip.h>
26#include <linux/tcp.h>
27#include <linux/sched.h>
28#include <linux/tty.h>
29#include <linux/if_vlan.h>
30#include <linux/interrupt.h>
31#include <linux/vmalloc.h>
32#include <linux/firmware.h>
33#include <asm/byteorder.h>
34#include <linux/dma-mapping.h>
35#include <linux/slab.h>
36
37/* Compile Time Switches */
38/* start */
39#define BDX_TSO
40#define BDX_LLTX
41#define BDX_DELAY_WPTR
42/* #define BDX_MSI */
43/* end */
44
45#if !defined CONFIG_PCI_MSI
46# undef BDX_MSI
47#endif
48
49#define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
50 NETIF_MSG_PROBE | \
51 NETIF_MSG_LINK)
52
53/* ioctl ops */
54#define BDX_OP_READ 1
55#define BDX_OP_WRITE 2
56
57/* RX copy break size */
58#define BDX_COPYBREAK 257
59
60#define DRIVER_AUTHOR "Tehuti Networks(R)"
61#define BDX_DRV_DESC "Tehuti Networks(R) Network Driver"
62#define BDX_DRV_NAME "tehuti"
63#define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC"
64#define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
65#define BDX_DRV_VERSION "7.29.3"
66
67#ifdef BDX_MSI
68# define BDX_MSI_STRING "msi "
69#else
70# define BDX_MSI_STRING ""
71#endif
72
73/* netdev tx queue len for Luxor. default value is, btw, 1000
74 * ifcontig eth1 txqueuelen 3000 - to change it at runtime */
75#define BDX_NDEV_TXQ_LEN 3000
76
77#define FIFO_SIZE 4096
78#define FIFO_EXTRA_SPACE 1024
79
80#if BITS_PER_LONG == 64
81# define H32_64(x) (u32) ((u64)(x) >> 32)
82# define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
83#elif BITS_PER_LONG == 32
84# define H32_64(x) 0
85# define L32_64(x) ((u32) (x))
86#else /* BITS_PER_LONG == ?? */
87# error BITS_PER_LONG is undefined. Must be 64 or 32
88#endif /* BITS_PER_LONG */
89
90#ifdef __BIG_ENDIAN
91# define CPU_CHIP_SWAP32(x) swab32(x)
92# define CPU_CHIP_SWAP16(x) swab16(x)
93#else
94# define CPU_CHIP_SWAP32(x) (x)
95# define CPU_CHIP_SWAP16(x) (x)
96#endif
97
98#define READ_REG(pp, reg) readl(pp->pBdxRegs + reg)
99#define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg)
100
101#ifndef NET_IP_ALIGN
102# define NET_IP_ALIGN 2
103#endif
104
105#ifndef NETDEV_TX_OK
106# define NETDEV_TX_OK 0
107#endif
108
109#define LUXOR_MAX_PORT 2
110#define BDX_MAX_RX_DONE 150
111#define BDX_TXF_DESC_SZ 16
112#define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16)
113#define BDX_MIN_TX_LEVEL 256
114#define BDX_NO_UPD_PACKETS 40
115
116struct pci_nic {
117 int port_num;
118 void __iomem *regs;
119 int irq_type;
120 struct bdx_priv *priv[LUXOR_MAX_PORT];
121};
122
123enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX };
124
125#define PCK_TH_MULT 128
126#define INT_COAL_MULT 2
127
128#define BITS_MASK(nbits) ((1<<nbits)-1)
129#define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits))
130#define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift)
131#define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift)
132#define BITS_SHIFT_CLEAR(x, nbits, nshift) \
133 ((x)&(~BITS_SHIFT_MASK(nbits, nshift)))
134
135#define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
136#define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15)
137#define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16)
138#define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20)
139
140#define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \
141 ((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20))
142
143struct fifo {
144 dma_addr_t da; /* physical address of fifo (used by HW) */
145 char *va; /* virtual address of fifo (used by SW) */
146 u32 rptr, wptr; /* cached values of RPTR and WPTR registers,
147 they're 32 bits on both 32 and 64 archs */
148 u16 reg_CFG0, reg_CFG1;
149 u16 reg_RPTR, reg_WPTR;
150 u16 memsz; /* memory size allocated for fifo */
151 u16 size_mask;
152 u16 pktsz; /* skb packet size to allocate */
153 u16 rcvno; /* number of buffers that come from this RXF */
154};
155
156struct txf_fifo {
157 struct fifo m; /* minimal set of variables used by all fifos */
158};
159
160struct txd_fifo {
161 struct fifo m; /* minimal set of variables used by all fifos */
162};
163
164struct rxf_fifo {
165 struct fifo m; /* minimal set of variables used by all fifos */
166};
167
168struct rxd_fifo {
169 struct fifo m; /* minimal set of variables used by all fifos */
170};
171
172struct rx_map {
173 u64 dma;
174 struct sk_buff *skb;
175};
176
177struct rxdb {
178 int *stack;
179 struct rx_map *elems;
180 int nelem;
181 int top;
182};
183
184union bdx_dma_addr {
185 dma_addr_t dma;
186 struct sk_buff *skb;
187};
188
189/* Entry in the db.
190 * if len == 0 addr is dma
191 * if len != 0 addr is skb */
192struct tx_map {
193 union bdx_dma_addr addr;
194 int len;
195};
196
197/* tx database - implemented as circular fifo buffer*/
198struct txdb {
199 struct tx_map *start; /* points to the first element */
200 struct tx_map *end; /* points just AFTER the last element */
201 struct tx_map *rptr; /* points to the next element to read */
202 struct tx_map *wptr; /* points to the next element to write */
203 int size; /* number of elements in the db */
204};
205
206/*Internal stats structure*/
207struct bdx_stats {
208 u64 InUCast; /* 0x7200 */
209 u64 InMCast; /* 0x7210 */
210 u64 InBCast; /* 0x7220 */
211 u64 InPkts; /* 0x7230 */
212 u64 InErrors; /* 0x7240 */
213 u64 InDropped; /* 0x7250 */
214 u64 FrameTooLong; /* 0x7260 */
215 u64 FrameSequenceErrors; /* 0x7270 */
216 u64 InVLAN; /* 0x7280 */
217 u64 InDroppedDFE; /* 0x7290 */
218 u64 InDroppedIntFull; /* 0x72A0 */
219 u64 InFrameAlignErrors; /* 0x72B0 */
220
221 /* 0x72C0-0x72E0 RSRV */
222
223 u64 OutUCast; /* 0x72F0 */
224 u64 OutMCast; /* 0x7300 */
225 u64 OutBCast; /* 0x7310 */
226 u64 OutPkts; /* 0x7320 */
227
228 /* 0x7330-0x7360 RSRV */
229
230 u64 OutVLAN; /* 0x7370 */
231 u64 InUCastOctects; /* 0x7380 */
232 u64 OutUCastOctects; /* 0x7390 */
233
234 /* 0x73A0-0x73B0 RSRV */
235
236 u64 InBCastOctects; /* 0x73C0 */
237 u64 OutBCastOctects; /* 0x73D0 */
238 u64 InOctects; /* 0x73E0 */
239 u64 OutOctects; /* 0x73F0 */
240};
241
242struct bdx_priv {
243 void __iomem *pBdxRegs;
244 struct net_device *ndev;
245
246 struct napi_struct napi;
247
248 /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
249 struct rxd_fifo rxd_fifo0;
250 struct rxf_fifo rxf_fifo0;
251 struct rxdb *rxdb; /* rx dbs to store skb pointers */
252 int napi_stop;
253
254 /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
255 struct txd_fifo txd_fifo0;
256 struct txf_fifo txf_fifo0;
257
258 struct txdb txdb;
259 int tx_level;
260#ifdef BDX_DELAY_WPTR
261 int tx_update_mark;
262 int tx_noupd;
263#endif
264 spinlock_t tx_lock; /* NETIF_F_LLTX mode */
265
266 /* rarely used */
267 u8 port;
268 u32 msg_enable;
269 int stats_flag;
270 struct bdx_stats hw_stats;
271 struct pci_dev *pdev;
272
273 struct pci_nic *nic;
274
275 u8 txd_size;
276 u8 txf_size;
277 u8 rxd_size;
278 u8 rxf_size;
279 u32 rdintcm;
280 u32 tdintcm;
281};
282
283/* RX FREE descriptor - 64bit*/
284struct rxf_desc {
285 u32 info; /* Buffer Count + Info - described below */
286 u32 va_lo; /* VAdr[31:0] */
287 u32 va_hi; /* VAdr[63:32] */
288 u32 pa_lo; /* PAdr[31:0] */
289 u32 pa_hi; /* PAdr[63:32] */
290 u32 len; /* Buffer Length */
291};
292
293#define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0)
294#define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8)
295#define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15)
296#define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16)
297#define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21)
298#define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27)
299#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28)
300#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31)
301#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0)
302#define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0)
303#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12)
304#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13)
305
306struct rxd_desc {
307 u32 rxd_val1;
308 u16 len;
309 u16 rxd_vlan;
310 u32 va_lo;
311 u32 va_hi;
312};
313
314/* PBL describes each virtual buffer to be */
315/* transmitted from the host.*/
316struct pbl {
317 u32 pa_lo;
318 u32 pa_hi;
319 u32 len;
320};
321
322/* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
323 * hw_csum = 7 for ip+udp+tcp hw checksums */
324#define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \
325 ((bc) | ((checksum)<<5) | ((vtag)<<8) | \
326 ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))
327
328struct txd_desc {
329 u32 txd_val1;
330 u16 mss;
331 u16 length;
332 u32 va_lo;
333 u32 va_hi;
334 struct pbl pbl[0]; /* Fragments */
335} __packed;
336
337/* Register region size */
338#define BDX_REGS_SIZE 0x1000
339
340/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
341#define regTXD_CFG1_0 0x4000
342#define regRXF_CFG1_0 0x4010
343#define regRXD_CFG1_0 0x4020
344#define regTXF_CFG1_0 0x4030
345#define regTXD_CFG0_0 0x4040
346#define regRXF_CFG0_0 0x4050
347#define regRXD_CFG0_0 0x4060
348#define regTXF_CFG0_0 0x4070
349#define regTXD_WPTR_0 0x4080
350#define regRXF_WPTR_0 0x4090
351#define regRXD_WPTR_0 0x40A0
352#define regTXF_WPTR_0 0x40B0
353#define regTXD_RPTR_0 0x40C0
354#define regRXF_RPTR_0 0x40D0
355#define regRXD_RPTR_0 0x40E0
356#define regTXF_RPTR_0 0x40F0
357#define regTXF_RPTR_3 0x40FC
358
359/* hardware versioning */
360#define FW_VER 0x5010
361#define SROM_VER 0x5020
362#define FPGA_VER 0x5030
363#define FPGA_SEED 0x5040
364
365/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
366#define regISR regISR0
367#define regISR0 0x5100
368
369#define regIMR regIMR0
370#define regIMR0 0x5110
371
372#define regRDINTCM0 0x5120
373#define regRDINTCM2 0x5128
374
375#define regTDINTCM0 0x5130
376
377#define regISR_MSK0 0x5140
378
379#define regINIT_SEMAPHORE 0x5170
380#define regINIT_STATUS 0x5180
381
382#define regMAC_LNK_STAT 0x0200
383#define MAC_LINK_STAT 0x4 /* Link state */
384
385#define regGMAC_RXF_A 0x1240
386
387#define regUNC_MAC0_A 0x1250
388#define regUNC_MAC1_A 0x1260
389#define regUNC_MAC2_A 0x1270
390
391#define regVLAN_0 0x1800
392
393#define regMAX_FRAME_A 0x12C0
394
395#define regRX_MAC_MCST0 0x1A80
396#define regRX_MAC_MCST1 0x1A84
397#define MAC_MCST_NUM 15
398#define regRX_MCST_HASH0 0x1A00
399#define MAC_MCST_HASH_NUM 8
400
401#define regVPC 0x2300
402#define regVIC 0x2320
403#define regVGLB 0x2340
404
405#define regCLKPLL 0x5000
406
407/*for 10G only*/
408#define regREVISION 0x6000
409#define regSCRATCH 0x6004
410#define regCTRLST 0x6008
411#define regMAC_ADDR_0 0x600C
412#define regMAC_ADDR_1 0x6010
413#define regFRM_LENGTH 0x6014
414#define regPAUSE_QUANT 0x6018
415#define regRX_FIFO_SECTION 0x601C
416#define regTX_FIFO_SECTION 0x6020
417#define regRX_FULLNESS 0x6024
418#define regTX_FULLNESS 0x6028
419#define regHASHTABLE 0x602C
420#define regMDIO_ST 0x6030
421#define regMDIO_CTL 0x6034
422#define regMDIO_DATA 0x6038
423#define regMDIO_ADDR 0x603C
424
425#define regRST_PORT 0x7000
426#define regDIS_PORT 0x7010
427#define regRST_QU 0x7020
428#define regDIS_QU 0x7030
429
430#define regCTRLST_TX_ENA 0x0001
431#define regCTRLST_RX_ENA 0x0002
432#define regCTRLST_PRM_ENA 0x0010
433#define regCTRLST_PAD_ENA 0x0020
434
435#define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA)
436
437#define regRX_FLT 0x1400
438
439/* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/
440#define TX_RX_CFG1_BASE 0xffffffff /*0-31 */
441#define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */
442#define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */
443#define TX_RX_CFG0_SIZE 0x0003 /*1:0 */
444
445/* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */
446#define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */
447
448/* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */
449#define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */
450
451#define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped
452 * size is rounded to 16 */
453
454/* regISR 0x0100 */
455/* regIMR 0x0110 */
456#define IMR_INPROG 0x80000000 /*31 */
457#define IR_LNKCHG1 0x10000000 /*28 */
458#define IR_LNKCHG0 0x08000000 /*27 */
459#define IR_GPIO 0x04000000 /*26 */
460#define IR_RFRSH 0x02000000 /*25 */
461#define IR_RSVD 0x01000000 /*24 */
462#define IR_SWI 0x00800000 /*23 */
463#define IR_RX_FREE_3 0x00400000 /*22 */
464#define IR_RX_FREE_2 0x00200000 /*21 */
465#define IR_RX_FREE_1 0x00100000 /*20 */
466#define IR_RX_FREE_0 0x00080000 /*19 */
467#define IR_TX_FREE_3 0x00040000 /*18 */
468#define IR_TX_FREE_2 0x00020000 /*17 */
469#define IR_TX_FREE_1 0x00010000 /*16 */
470#define IR_TX_FREE_0 0x00008000 /*15 */
471#define IR_RX_DESC_3 0x00004000 /*14 */
472#define IR_RX_DESC_2 0x00002000 /*13 */
473#define IR_RX_DESC_1 0x00001000 /*12 */
474#define IR_RX_DESC_0 0x00000800 /*11 */
475#define IR_PSE 0x00000400 /*10 */
476#define IR_TMR3 0x00000200 /*9 */
477#define IR_TMR2 0x00000100 /*8 */
478#define IR_TMR1 0x00000080 /*7 */
479#define IR_TMR0 0x00000040 /*6 */
480#define IR_VNT 0x00000020 /*5 */
481#define IR_RxFL 0x00000010 /*4 */
482#define IR_SDPERR 0x00000008 /*3 */
483#define IR_TR 0x00000004 /*2 */
484#define IR_PCIE_LINK 0x00000002 /*1 */
485#define IR_PCIE_TOUT 0x00000001 /*0 */
486
487#define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \
488 IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT)
489#define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0)
490#define IR_ALL 0xfdfffff7
491
492#define IR_LNKCHG0_ofst 27
493
494#define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */
495#define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */
496#define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */
497#define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */
498#define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */
499#define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */
500#define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */
501#define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */
502#define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */
503#define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */
504#define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */
505
506#define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */
507
508#define CLKPLL_PLLLKD 0x0200 /*9 */
509#define CLKPLL_RSTEND 0x0100 /*8 */
510#define CLKPLL_SFTRST 0x0001 /*0 */
511
512#define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND)
513
514/*
515 * PCI-E Device Control Register (Offset 0x88)
516 * Source: Luxor Data Sheet, 7.1.3.3.3
517 */
518#define PCI_DEV_CTRL_REG 0x88
519#define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5)
520#define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12)
521
522/*
523 * PCI-E Link Status Register (Offset 0x92)
524 * Source: Luxor Data Sheet, 7.1.3.3.7
525 */
526#define PCI_LINK_STATUS_REG 0x92
527#define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4)
528
529/* Debugging Macros */
530
531#define DBG2(fmt, args...) \
532 pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args)
533
534#define BDX_ASSERT(x) BUG_ON(x)
535
536#ifdef DEBUG
537
538#define ENTER \
539do { \
540 pr_err("%s:%-5d: ENTER\n", __func__, __LINE__); \
541} while (0)
542
543#define RET(args...) \
544do { \
545 pr_err("%s:%-5d: RETURN\n", __func__, __LINE__); \
546 return args; \
547} while (0)
548
549#define DBG(fmt, args...) \
550 pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args)
551#else
552#define ENTER do { } while (0)
553#define RET(args...) return args
554#define DBG(fmt, args...) \
555do { \
556 if (0) \
557 pr_err(fmt, ##args); \
558} while (0)
559#endif
560
561#endif /* _BDX__H */