1/*
  2 * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
  3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  4 * Copyright (c) 2006, 2007 Cisco Systems.  All rights reserved.
  5 *
  6 * This software is available to you under a choice of one of two
  7 * licenses.  You may choose to be licensed under the terms of the GNU
  8 * General Public License (GPL) Version 2, available from the file
  9 * COPYING in the main directory of this source tree, or the
 10 * OpenIB.org BSD license below:
 11 *
 12 *     Redistribution and use in source and binary forms, with or
 13 *     without modification, are permitted provided that the following
 14 *     conditions are met:
 15 *
 16 *      - Redistributions of source code must retain the above
 17 *        copyright notice, this list of conditions and the following
 18 *        disclaimer.
 19 *
 20 *      - Redistributions in binary form must reproduce the above
 21 *        copyright notice, this list of conditions and the following
 22 *        disclaimer in the documentation and/or other materials
 23 *        provided with the distribution.
 24 *
 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 32 * SOFTWARE.
 33 */
 34
 35#ifndef MLX4_FW_H
 36#define MLX4_FW_H
 37
 38#include "mlx4.h"
 39#include "icm.h"
 40
 41struct mlx4_mod_stat_cfg {
 42	u8 log_pg_sz;
 43	u8 log_pg_sz_m;
 44};
 45
 46struct mlx4_dev_cap {
 47	int max_srq_sz;
 48	int max_qp_sz;
 49	int reserved_qps;
 50	int max_qps;
 51	int reserved_srqs;
 52	int max_srqs;
 53	int max_cq_sz;
 54	int reserved_cqs;
 55	int max_cqs;
 56	int max_mpts;
 57	int reserved_eqs;
 58	int max_eqs;
 59	int reserved_mtts;
 60	int max_mrw_sz;
 61	int reserved_mrws;
 62	int max_mtt_seg;
 63	int max_requester_per_qp;
 64	int max_responder_per_qp;
 65	int max_rdma_global;
 66	int local_ca_ack_delay;
 67	int num_ports;
 68	u32 max_msg_sz;
 69	int ib_mtu[MLX4_MAX_PORTS + 1];
 70	int max_port_width[MLX4_MAX_PORTS + 1];
 71	int max_vl[MLX4_MAX_PORTS + 1];
 72	int max_gids[MLX4_MAX_PORTS + 1];
 73	int max_pkeys[MLX4_MAX_PORTS + 1];
 74	u64 def_mac[MLX4_MAX_PORTS + 1];
 75	u16 eth_mtu[MLX4_MAX_PORTS + 1];
 76	int trans_type[MLX4_MAX_PORTS + 1];
 77	int vendor_oui[MLX4_MAX_PORTS + 1];
 78	u16 wavelength[MLX4_MAX_PORTS + 1];
 79	u64 trans_code[MLX4_MAX_PORTS + 1];
 80	u16 stat_rate_support;
 81	u64 flags;
 82	int reserved_uars;
 83	int uar_size;
 84	int min_page_sz;
 85	int bf_reg_size;
 86	int bf_regs_per_page;
 87	int max_sq_sg;
 88	int max_sq_desc_sz;
 89	int max_rq_sg;
 90	int max_rq_desc_sz;
 91	int max_qp_per_mcg;
 92	int reserved_mgms;
 93	int max_mcgs;
 94	int reserved_pds;
 95	int max_pds;
 96	int qpc_entry_sz;
 97	int rdmarc_entry_sz;
 98	int altc_entry_sz;
 99	int aux_entry_sz;
100	int srq_entry_sz;
101	int cqc_entry_sz;
102	int eqc_entry_sz;
103	int dmpt_entry_sz;
104	int cmpt_entry_sz;
105	int mtt_entry_sz;
106	int resize_srq;
107	u32 bmme_flags;
108	u32 reserved_lkey;
109	u64 max_icm_sz;
110	int max_gso_sz;
111	u8  supported_port_types[MLX4_MAX_PORTS + 1];
112	u8  log_max_macs[MLX4_MAX_PORTS + 1];
113	u8  log_max_vlans[MLX4_MAX_PORTS + 1];
114	u32 max_counters;
115};
116
117struct mlx4_adapter {
118	char board_id[MLX4_BOARD_ID_LEN];
119	u8   inta_pin;
120};
121
122struct mlx4_init_hca_param {
123	u64 qpc_base;
124	u64 rdmarc_base;
125	u64 auxc_base;
126	u64 altc_base;
127	u64 srqc_base;
128	u64 cqc_base;
129	u64 eqc_base;
130	u64 mc_base;
131	u64 dmpt_base;
132	u64 cmpt_base;
133	u64 mtt_base;
134	u16 log_mc_entry_sz;
135	u16 log_mc_hash_sz;
136	u8  log_num_qps;
137	u8  log_num_srqs;
138	u8  log_num_cqs;
139	u8  log_num_eqs;
140	u8  log_rd_per_qp;
141	u8  log_mc_table_sz;
142	u8  log_mpt_sz;
143	u8  log_uar_sz;
144};
145
146struct mlx4_init_ib_param {
147	int port_width;
148	int vl_cap;
149	int mtu_cap;
150	u16 gid_cap;
151	u16 pkey_cap;
152	int set_guid0;
153	u64 guid0;
154	int set_node_guid;
155	u64 node_guid;
156	int set_si_guid;
157	u64 si_guid;
158};
159
160struct mlx4_set_ib_param {
161	int set_si_guid;
162	int reset_qkey_viol;
163	u64 si_guid;
164	u32 cap_mask;
165};
166
167int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
168int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
169int mlx4_UNMAP_FA(struct mlx4_dev *dev);
170int mlx4_RUN_FW(struct mlx4_dev *dev);
171int mlx4_QUERY_FW(struct mlx4_dev *dev);
172int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
173int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
174int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
175int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
176int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
177int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
178int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
179int mlx4_NOP(struct mlx4_dev *dev);
180int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
181
182#endif /* MLX4_FW_H */