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1/*
2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/interrupt.h>
35#include <linux/slab.h>
36#include <linux/mm.h>
37#include <linux/dma-mapping.h>
38
39#include <linux/mlx4/cmd.h>
40
41#include "mlx4.h"
42#include "fw.h"
43
44enum {
45 MLX4_IRQNAME_SIZE = 32
46};
47
48enum {
49 MLX4_NUM_ASYNC_EQE = 0x100,
50 MLX4_NUM_SPARE_EQE = 0x80,
51 MLX4_EQ_ENTRY_SIZE = 0x20
52};
53
54/*
55 * Must be packed because start is 64 bits but only aligned to 32 bits.
56 */
57struct mlx4_eq_context {
58 __be32 flags;
59 u16 reserved1[3];
60 __be16 page_offset;
61 u8 log_eq_size;
62 u8 reserved2[4];
63 u8 eq_period;
64 u8 reserved3;
65 u8 eq_max_count;
66 u8 reserved4[3];
67 u8 intr;
68 u8 log_page_size;
69 u8 reserved5[2];
70 u8 mtt_base_addr_h;
71 __be32 mtt_base_addr_l;
72 u32 reserved6[2];
73 __be32 consumer_index;
74 __be32 producer_index;
75 u32 reserved7[4];
76};
77
78#define MLX4_EQ_STATUS_OK ( 0 << 28)
79#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
80#define MLX4_EQ_OWNER_SW ( 0 << 24)
81#define MLX4_EQ_OWNER_HW ( 1 << 24)
82#define MLX4_EQ_FLAG_EC ( 1 << 18)
83#define MLX4_EQ_FLAG_OI ( 1 << 17)
84#define MLX4_EQ_STATE_ARMED ( 9 << 8)
85#define MLX4_EQ_STATE_FIRED (10 << 8)
86#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
87
88#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
89 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
90 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
91 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
92 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
93 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
94 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
95 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
96 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
97 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
98 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
99 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
100 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
101 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
102 (1ull << MLX4_EVENT_TYPE_CMD))
103
104struct mlx4_eqe {
105 u8 reserved1;
106 u8 type;
107 u8 reserved2;
108 u8 subtype;
109 union {
110 u32 raw[6];
111 struct {
112 __be32 cqn;
113 } __packed comp;
114 struct {
115 u16 reserved1;
116 __be16 token;
117 u32 reserved2;
118 u8 reserved3[3];
119 u8 status;
120 __be64 out_param;
121 } __packed cmd;
122 struct {
123 __be32 qpn;
124 } __packed qp;
125 struct {
126 __be32 srqn;
127 } __packed srq;
128 struct {
129 __be32 cqn;
130 u32 reserved1;
131 u8 reserved2[3];
132 u8 syndrome;
133 } __packed cq_err;
134 struct {
135 u32 reserved1[2];
136 __be32 port;
137 } __packed port_change;
138 } event;
139 u8 reserved3[3];
140 u8 owner;
141} __packed;
142
143static void eq_set_ci(struct mlx4_eq *eq, int req_not)
144{
145 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
146 req_not << 31),
147 eq->doorbell);
148 /* We still want ordering, just not swabbing, so add a barrier */
149 mb();
150}
151
152static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
153{
154 unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
155 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
156}
157
158static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
159{
160 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
161 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
162}
163
164static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
165{
166 struct mlx4_eqe *eqe;
167 int cqn;
168 int eqes_found = 0;
169 int set_ci = 0;
170 int port;
171
172 while ((eqe = next_eqe_sw(eq))) {
173 /*
174 * Make sure we read EQ entry contents after we've
175 * checked the ownership bit.
176 */
177 rmb();
178
179 switch (eqe->type) {
180 case MLX4_EVENT_TYPE_COMP:
181 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
182 mlx4_cq_completion(dev, cqn);
183 break;
184
185 case MLX4_EVENT_TYPE_PATH_MIG:
186 case MLX4_EVENT_TYPE_COMM_EST:
187 case MLX4_EVENT_TYPE_SQ_DRAINED:
188 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
189 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
190 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
191 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
192 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
193 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
194 eqe->type);
195 break;
196
197 case MLX4_EVENT_TYPE_SRQ_LIMIT:
198 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
199 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
200 eqe->type);
201 break;
202
203 case MLX4_EVENT_TYPE_CMD:
204 mlx4_cmd_event(dev,
205 be16_to_cpu(eqe->event.cmd.token),
206 eqe->event.cmd.status,
207 be64_to_cpu(eqe->event.cmd.out_param));
208 break;
209
210 case MLX4_EVENT_TYPE_PORT_CHANGE:
211 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
212 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
213 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
214 port);
215 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
216 } else {
217 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP,
218 port);
219 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
220 }
221 break;
222
223 case MLX4_EVENT_TYPE_CQ_ERROR:
224 mlx4_warn(dev, "CQ %s on CQN %06x\n",
225 eqe->event.cq_err.syndrome == 1 ?
226 "overrun" : "access violation",
227 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
228 mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
229 eqe->type);
230 break;
231
232 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
233 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
234 break;
235
236 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
237 case MLX4_EVENT_TYPE_ECC_DETECT:
238 default:
239 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
240 eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
241 break;
242 }
243
244 ++eq->cons_index;
245 eqes_found = 1;
246 ++set_ci;
247
248 /*
249 * The HCA will think the queue has overflowed if we
250 * don't tell it we've been processing events. We
251 * create our EQs with MLX4_NUM_SPARE_EQE extra
252 * entries, so we must update our consumer index at
253 * least that often.
254 */
255 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
256 eq_set_ci(eq, 0);
257 set_ci = 0;
258 }
259 }
260
261 eq_set_ci(eq, 1);
262
263 return eqes_found;
264}
265
266static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
267{
268 struct mlx4_dev *dev = dev_ptr;
269 struct mlx4_priv *priv = mlx4_priv(dev);
270 int work = 0;
271 int i;
272
273 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
274
275 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
276 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
277
278 return IRQ_RETVAL(work);
279}
280
281static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
282{
283 struct mlx4_eq *eq = eq_ptr;
284 struct mlx4_dev *dev = eq->dev;
285
286 mlx4_eq_int(dev, eq);
287
288 /* MSI-X vectors always belong to us */
289 return IRQ_HANDLED;
290}
291
292static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
293 int eq_num)
294{
295 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
296 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
297}
298
299static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
300 int eq_num)
301{
302 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
303 MLX4_CMD_TIME_CLASS_A);
304}
305
306static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
307 int eq_num)
308{
309 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
310 MLX4_CMD_TIME_CLASS_A);
311}
312
313static int mlx4_num_eq_uar(struct mlx4_dev *dev)
314{
315 /*
316 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
317 * we need to map, take the difference of highest index and
318 * the lowest index we'll use and add 1.
319 */
320 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
321 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
322}
323
324static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
325{
326 struct mlx4_priv *priv = mlx4_priv(dev);
327 int index;
328
329 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
330
331 if (!priv->eq_table.uar_map[index]) {
332 priv->eq_table.uar_map[index] =
333 ioremap(pci_resource_start(dev->pdev, 2) +
334 ((eq->eqn / 4) << PAGE_SHIFT),
335 PAGE_SIZE);
336 if (!priv->eq_table.uar_map[index]) {
337 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
338 eq->eqn);
339 return NULL;
340 }
341 }
342
343 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
344}
345
346static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
347 u8 intr, struct mlx4_eq *eq)
348{
349 struct mlx4_priv *priv = mlx4_priv(dev);
350 struct mlx4_cmd_mailbox *mailbox;
351 struct mlx4_eq_context *eq_context;
352 int npages;
353 u64 *dma_list = NULL;
354 dma_addr_t t;
355 u64 mtt_addr;
356 int err = -ENOMEM;
357 int i;
358
359 eq->dev = dev;
360 eq->nent = roundup_pow_of_two(max(nent, 2));
361 npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
362
363 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
364 GFP_KERNEL);
365 if (!eq->page_list)
366 goto err_out;
367
368 for (i = 0; i < npages; ++i)
369 eq->page_list[i].buf = NULL;
370
371 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
372 if (!dma_list)
373 goto err_out_free;
374
375 mailbox = mlx4_alloc_cmd_mailbox(dev);
376 if (IS_ERR(mailbox))
377 goto err_out_free;
378 eq_context = mailbox->buf;
379
380 for (i = 0; i < npages; ++i) {
381 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
382 PAGE_SIZE, &t, GFP_KERNEL);
383 if (!eq->page_list[i].buf)
384 goto err_out_free_pages;
385
386 dma_list[i] = t;
387 eq->page_list[i].map = t;
388
389 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
390 }
391
392 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
393 if (eq->eqn == -1)
394 goto err_out_free_pages;
395
396 eq->doorbell = mlx4_get_eq_uar(dev, eq);
397 if (!eq->doorbell) {
398 err = -ENOMEM;
399 goto err_out_free_eq;
400 }
401
402 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
403 if (err)
404 goto err_out_free_eq;
405
406 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
407 if (err)
408 goto err_out_free_mtt;
409
410 memset(eq_context, 0, sizeof *eq_context);
411 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
412 MLX4_EQ_STATE_ARMED);
413 eq_context->log_eq_size = ilog2(eq->nent);
414 eq_context->intr = intr;
415 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
416
417 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
418 eq_context->mtt_base_addr_h = mtt_addr >> 32;
419 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
420
421 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
422 if (err) {
423 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
424 goto err_out_free_mtt;
425 }
426
427 kfree(dma_list);
428 mlx4_free_cmd_mailbox(dev, mailbox);
429
430 eq->cons_index = 0;
431
432 return err;
433
434err_out_free_mtt:
435 mlx4_mtt_cleanup(dev, &eq->mtt);
436
437err_out_free_eq:
438 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
439
440err_out_free_pages:
441 for (i = 0; i < npages; ++i)
442 if (eq->page_list[i].buf)
443 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
444 eq->page_list[i].buf,
445 eq->page_list[i].map);
446
447 mlx4_free_cmd_mailbox(dev, mailbox);
448
449err_out_free:
450 kfree(eq->page_list);
451 kfree(dma_list);
452
453err_out:
454 return err;
455}
456
457static void mlx4_free_eq(struct mlx4_dev *dev,
458 struct mlx4_eq *eq)
459{
460 struct mlx4_priv *priv = mlx4_priv(dev);
461 struct mlx4_cmd_mailbox *mailbox;
462 int err;
463 int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
464 int i;
465
466 mailbox = mlx4_alloc_cmd_mailbox(dev);
467 if (IS_ERR(mailbox))
468 return;
469
470 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
471 if (err)
472 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
473
474 if (0) {
475 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
476 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
477 if (i % 4 == 0)
478 pr_cont("[%02x] ", i * 4);
479 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
480 if ((i + 1) % 4 == 0)
481 pr_cont("\n");
482 }
483 }
484
485 mlx4_mtt_cleanup(dev, &eq->mtt);
486 for (i = 0; i < npages; ++i)
487 pci_free_consistent(dev->pdev, PAGE_SIZE,
488 eq->page_list[i].buf,
489 eq->page_list[i].map);
490
491 kfree(eq->page_list);
492 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
493 mlx4_free_cmd_mailbox(dev, mailbox);
494}
495
496static void mlx4_free_irqs(struct mlx4_dev *dev)
497{
498 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
499 struct mlx4_priv *priv = mlx4_priv(dev);
500 int i, vec;
501
502 if (eq_table->have_irq)
503 free_irq(dev->pdev->irq, dev);
504
505 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
506 if (eq_table->eq[i].have_irq) {
507 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
508 eq_table->eq[i].have_irq = 0;
509 }
510
511 for (i = 0; i < dev->caps.comp_pool; i++) {
512 /*
513 * Freeing the assigned irq's
514 * all bits should be 0, but we need to validate
515 */
516 if (priv->msix_ctl.pool_bm & 1ULL << i) {
517 /* NO need protecting*/
518 vec = dev->caps.num_comp_vectors + 1 + i;
519 free_irq(priv->eq_table.eq[vec].irq,
520 &priv->eq_table.eq[vec]);
521 }
522 }
523
524
525 kfree(eq_table->irq_names);
526}
527
528static int mlx4_map_clr_int(struct mlx4_dev *dev)
529{
530 struct mlx4_priv *priv = mlx4_priv(dev);
531
532 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
533 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
534 if (!priv->clr_base) {
535 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
536 return -ENOMEM;
537 }
538
539 return 0;
540}
541
542static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
543{
544 struct mlx4_priv *priv = mlx4_priv(dev);
545
546 iounmap(priv->clr_base);
547}
548
549int mlx4_alloc_eq_table(struct mlx4_dev *dev)
550{
551 struct mlx4_priv *priv = mlx4_priv(dev);
552
553 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
554 sizeof *priv->eq_table.eq, GFP_KERNEL);
555 if (!priv->eq_table.eq)
556 return -ENOMEM;
557
558 return 0;
559}
560
561void mlx4_free_eq_table(struct mlx4_dev *dev)
562{
563 kfree(mlx4_priv(dev)->eq_table.eq);
564}
565
566int mlx4_init_eq_table(struct mlx4_dev *dev)
567{
568 struct mlx4_priv *priv = mlx4_priv(dev);
569 int err;
570 int i;
571
572 priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
573 mlx4_num_eq_uar(dev), GFP_KERNEL);
574 if (!priv->eq_table.uar_map) {
575 err = -ENOMEM;
576 goto err_out_free;
577 }
578
579 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
580 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
581 if (err)
582 goto err_out_free;
583
584 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
585 priv->eq_table.uar_map[i] = NULL;
586
587 err = mlx4_map_clr_int(dev);
588 if (err)
589 goto err_out_bitmap;
590
591 priv->eq_table.clr_mask =
592 swab32(1 << (priv->eq_table.inta_pin & 31));
593 priv->eq_table.clr_int = priv->clr_base +
594 (priv->eq_table.inta_pin < 32 ? 4 : 0);
595
596 priv->eq_table.irq_names =
597 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
598 dev->caps.comp_pool),
599 GFP_KERNEL);
600 if (!priv->eq_table.irq_names) {
601 err = -ENOMEM;
602 goto err_out_bitmap;
603 }
604
605 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
606 err = mlx4_create_eq(dev, dev->caps.num_cqs -
607 dev->caps.reserved_cqs +
608 MLX4_NUM_SPARE_EQE,
609 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
610 &priv->eq_table.eq[i]);
611 if (err) {
612 --i;
613 goto err_out_unmap;
614 }
615 }
616
617 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
618 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
619 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
620 if (err)
621 goto err_out_comp;
622
623 /*if additional completion vectors poolsize is 0 this loop will not run*/
624 for (i = dev->caps.num_comp_vectors + 1;
625 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
626
627 err = mlx4_create_eq(dev, dev->caps.num_cqs -
628 dev->caps.reserved_cqs +
629 MLX4_NUM_SPARE_EQE,
630 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
631 &priv->eq_table.eq[i]);
632 if (err) {
633 --i;
634 goto err_out_unmap;
635 }
636 }
637
638
639 if (dev->flags & MLX4_FLAG_MSI_X) {
640 const char *eq_name;
641
642 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
643 if (i < dev->caps.num_comp_vectors) {
644 snprintf(priv->eq_table.irq_names +
645 i * MLX4_IRQNAME_SIZE,
646 MLX4_IRQNAME_SIZE,
647 "mlx4-comp-%d@pci:%s", i,
648 pci_name(dev->pdev));
649 } else {
650 snprintf(priv->eq_table.irq_names +
651 i * MLX4_IRQNAME_SIZE,
652 MLX4_IRQNAME_SIZE,
653 "mlx4-async@pci:%s",
654 pci_name(dev->pdev));
655 }
656
657 eq_name = priv->eq_table.irq_names +
658 i * MLX4_IRQNAME_SIZE;
659 err = request_irq(priv->eq_table.eq[i].irq,
660 mlx4_msi_x_interrupt, 0, eq_name,
661 priv->eq_table.eq + i);
662 if (err)
663 goto err_out_async;
664
665 priv->eq_table.eq[i].have_irq = 1;
666 }
667 } else {
668 snprintf(priv->eq_table.irq_names,
669 MLX4_IRQNAME_SIZE,
670 DRV_NAME "@pci:%s",
671 pci_name(dev->pdev));
672 err = request_irq(dev->pdev->irq, mlx4_interrupt,
673 IRQF_SHARED, priv->eq_table.irq_names, dev);
674 if (err)
675 goto err_out_async;
676
677 priv->eq_table.have_irq = 1;
678 }
679
680 err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
681 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
682 if (err)
683 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
684 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
685
686 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
687 eq_set_ci(&priv->eq_table.eq[i], 1);
688
689 return 0;
690
691err_out_async:
692 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
693
694err_out_comp:
695 i = dev->caps.num_comp_vectors - 1;
696
697err_out_unmap:
698 while (i >= 0) {
699 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
700 --i;
701 }
702 mlx4_unmap_clr_int(dev);
703 mlx4_free_irqs(dev);
704
705err_out_bitmap:
706 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
707
708err_out_free:
709 kfree(priv->eq_table.uar_map);
710
711 return err;
712}
713
714void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
715{
716 struct mlx4_priv *priv = mlx4_priv(dev);
717 int i;
718
719 mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
720 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
721
722 mlx4_free_irqs(dev);
723
724 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
725 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
726
727 mlx4_unmap_clr_int(dev);
728
729 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
730 if (priv->eq_table.uar_map[i])
731 iounmap(priv->eq_table.uar_map[i]);
732
733 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
734
735 kfree(priv->eq_table.uar_map);
736}
737
738/* A test that verifies that we can accept interrupts on all
739 * the irq vectors of the device.
740 * Interrupts are checked using the NOP command.
741 */
742int mlx4_test_interrupts(struct mlx4_dev *dev)
743{
744 struct mlx4_priv *priv = mlx4_priv(dev);
745 int i;
746 int err;
747
748 err = mlx4_NOP(dev);
749 /* When not in MSI_X, there is only one irq to check */
750 if (!(dev->flags & MLX4_FLAG_MSI_X))
751 return err;
752
753 /* A loop over all completion vectors, for each vector we will check
754 * whether it works by mapping command completions to that vector
755 * and performing a NOP command
756 */
757 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
758 /* Temporary use polling for command completions */
759 mlx4_cmd_use_polling(dev);
760
761 /* Map the new eq to handle all asyncronous events */
762 err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
763 priv->eq_table.eq[i].eqn);
764 if (err) {
765 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
766 mlx4_cmd_use_events(dev);
767 break;
768 }
769
770 /* Go back to using events */
771 mlx4_cmd_use_events(dev);
772 err = mlx4_NOP(dev);
773 }
774
775 /* Return to default */
776 mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
777 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
778 return err;
779}
780EXPORT_SYMBOL(mlx4_test_interrupts);
781
782int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector)
783{
784
785 struct mlx4_priv *priv = mlx4_priv(dev);
786 int vec = 0, err = 0, i;
787
788 spin_lock(&priv->msix_ctl.pool_lock);
789 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
790 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
791 priv->msix_ctl.pool_bm |= 1ULL << i;
792 vec = dev->caps.num_comp_vectors + 1 + i;
793 snprintf(priv->eq_table.irq_names +
794 vec * MLX4_IRQNAME_SIZE,
795 MLX4_IRQNAME_SIZE, "%s", name);
796 err = request_irq(priv->eq_table.eq[vec].irq,
797 mlx4_msi_x_interrupt, 0,
798 &priv->eq_table.irq_names[vec<<5],
799 priv->eq_table.eq + vec);
800 if (err) {
801 /*zero out bit by fliping it*/
802 priv->msix_ctl.pool_bm ^= 1 << i;
803 vec = 0;
804 continue;
805 /*we dont want to break here*/
806 }
807 eq_set_ci(&priv->eq_table.eq[vec], 1);
808 }
809 }
810 spin_unlock(&priv->msix_ctl.pool_lock);
811
812 if (vec) {
813 *vector = vec;
814 } else {
815 *vector = 0;
816 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
817 }
818 return err;
819}
820EXPORT_SYMBOL(mlx4_assign_eq);
821
822void mlx4_release_eq(struct mlx4_dev *dev, int vec)
823{
824 struct mlx4_priv *priv = mlx4_priv(dev);
825 /*bm index*/
826 int i = vec - dev->caps.num_comp_vectors - 1;
827
828 if (likely(i >= 0)) {
829 /*sanity check , making sure were not trying to free irq's
830 Belonging to a legacy EQ*/
831 spin_lock(&priv->msix_ctl.pool_lock);
832 if (priv->msix_ctl.pool_bm & 1ULL << i) {
833 free_irq(priv->eq_table.eq[vec].irq,
834 &priv->eq_table.eq[vec]);
835 priv->msix_ctl.pool_bm &= ~(1ULL << i);
836 }
837 spin_unlock(&priv->msix_ctl.pool_lock);
838 }
839
840}
841EXPORT_SYMBOL(mlx4_release_eq);
842