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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _E1000_82575_H_
29#define _E1000_82575_H_
30
31extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
32extern void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
33extern void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
34extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
35
36#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
37 (ID_LED_DEF1_DEF2 << 8) | \
38 (ID_LED_DEF1_DEF2 << 4) | \
39 (ID_LED_OFF1_ON2))
40
41#define E1000_RAR_ENTRIES_82575 16
42#define E1000_RAR_ENTRIES_82576 24
43#define E1000_RAR_ENTRIES_82580 24
44#define E1000_RAR_ENTRIES_I350 32
45
46#define E1000_SW_SYNCH_MB 0x00000100
47#define E1000_STAT_DEV_RST_SET 0x00100000
48#define E1000_CTRL_DEV_RST 0x20000000
49
50/* SRRCTL bit definitions */
51#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
52#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
53#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
54#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
55#define E1000_SRRCTL_DROP_EN 0x80000000
56#define E1000_SRRCTL_TIMESTAMP 0x40000000
57
58#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
59#define E1000_MRQC_ENABLE_VMDQ 0x00000003
60#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
61#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
62#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
63#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
64
65#define E1000_EICR_TX_QUEUE ( \
66 E1000_EICR_TX_QUEUE0 | \
67 E1000_EICR_TX_QUEUE1 | \
68 E1000_EICR_TX_QUEUE2 | \
69 E1000_EICR_TX_QUEUE3)
70
71#define E1000_EICR_RX_QUEUE ( \
72 E1000_EICR_RX_QUEUE0 | \
73 E1000_EICR_RX_QUEUE1 | \
74 E1000_EICR_RX_QUEUE2 | \
75 E1000_EICR_RX_QUEUE3)
76
77/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
78#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
79#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
80
81/* Receive Descriptor - Advanced */
82union e1000_adv_rx_desc {
83 struct {
84 __le64 pkt_addr; /* Packet buffer address */
85 __le64 hdr_addr; /* Header buffer address */
86 } read;
87 struct {
88 struct {
89 struct {
90 __le16 pkt_info; /* RSS type, Packet type */
91 __le16 hdr_info; /* Split Header,
92 * header buffer length */
93 } lo_dword;
94 union {
95 __le32 rss; /* RSS Hash */
96 struct {
97 __le16 ip_id; /* IP id */
98 __le16 csum; /* Packet Checksum */
99 } csum_ip;
100 } hi_dword;
101 } lower;
102 struct {
103 __le32 status_error; /* ext status/error */
104 __le16 length; /* Packet length */
105 __le16 vlan; /* VLAN tag */
106 } upper;
107 } wb; /* writeback */
108};
109
110#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
111#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
112#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
113#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
114
115/* Transmit Descriptor - Advanced */
116union e1000_adv_tx_desc {
117 struct {
118 __le64 buffer_addr; /* Address of descriptor's data buf */
119 __le32 cmd_type_len;
120 __le32 olinfo_status;
121 } read;
122 struct {
123 __le64 rsvd; /* Reserved */
124 __le32 nxtseq_seed;
125 __le32 status;
126 } wb;
127};
128
129/* Adv Transmit Descriptor Config Masks */
130#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
131#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
132#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
133#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
134#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
135#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
136#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
137#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
138
139/* Context descriptors */
140struct e1000_adv_tx_context_desc {
141 __le32 vlan_macip_lens;
142 __le32 seqnum_seed;
143 __le32 type_tucmd_mlhl;
144 __le32 mss_l4len_idx;
145};
146
147#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
148#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
149#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
150#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
151/* IPSec Encrypt Enable for ESP */
152#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
153#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
154/* Adv ctxt IPSec SA IDX mask */
155/* Adv ctxt IPSec ESP len mask */
156
157/* Additional Transmit Descriptor Control definitions */
158#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
159/* Tx Queue Arbitration Priority 0=low, 1=high */
160
161/* Additional Receive Descriptor Control definitions */
162#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
163
164/* Direct Cache Access (DCA) definitions */
165#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
166#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
167
168#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
169#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
170#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
171#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
172
173#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
174#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
175#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
176
177/* Additional DCA related definitions, note change in position of CPUID */
178#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
179#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
180#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
181#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
182
183/* ETQF register bit definitions */
184#define E1000_ETQF_FILTER_ENABLE (1 << 26)
185#define E1000_ETQF_1588 (1 << 30)
186
187/* FTQF register bit definitions */
188#define E1000_FTQF_VF_BP 0x00008000
189#define E1000_FTQF_1588_TIME_STAMP 0x08000000
190#define E1000_FTQF_MASK 0xF0000000
191#define E1000_FTQF_MASK_PROTO_BP 0x10000000
192#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
193
194#define E1000_NVM_APME_82575 0x0400
195#define MAX_NUM_VFS 8
196
197#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
198#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
199#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
200#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
201#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
202
203/* Easy defines for setting default pool, would normally be left a zero */
204#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
205#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
206
207/* Other useful VMD_CTL register defines */
208#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
209#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
210#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
211
212/* Per VM Offload register setup */
213#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
214#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
215#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
216#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
217#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
218#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
219#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
220#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
221#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
222#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
223
224#define E1000_VLVF_ARRAY_SIZE 32
225#define E1000_VLVF_VLANID_MASK 0x00000FFF
226#define E1000_VLVF_POOLSEL_SHIFT 12
227#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
228#define E1000_VLVF_LVLAN 0x00100000
229#define E1000_VLVF_VLANID_ENABLE 0x80000000
230
231#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
232#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
233
234#define E1000_IOVCTL 0x05BBC
235#define E1000_IOVCTL_REUSE_VFQ 0x00000001
236
237#define E1000_RPLOLR_STRVLAN 0x40000000
238#define E1000_RPLOLR_STRCRC 0x80000000
239
240#define E1000_DTXCTL_8023LL 0x0004
241#define E1000_DTXCTL_VLAN_ADDED 0x0008
242#define E1000_DTXCTL_OOS_ENABLE 0x0010
243#define E1000_DTXCTL_MDP_EN 0x0020
244#define E1000_DTXCTL_SPOOF_INT 0x0040
245
246#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
247
248#define ALL_QUEUES 0xFFFF
249
250/* RX packet buffer size defines */
251#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
252void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
253void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
254void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
255u16 igb_rxpbs_adjust_82580(u32 data);
256s32 igb_set_eee_i350(struct e1000_hw *);
257
258#endif