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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9#ifndef MTK_ETH_H
10#define MTK_ETH_H
11
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/of_net.h>
15#include <linux/u64_stats_sync.h>
16#include <linux/refcount.h>
17#include <linux/phylink.h>
18#include <linux/rhashtable.h>
19#include <linux/dim.h>
20#include <linux/bitfield.h>
21#include <net/page_pool/types.h>
22#include <linux/bpf_trace.h>
23#include "mtk_ppe.h"
24
25#define MTK_MAX_DSA_PORTS 7
26#define MTK_DSA_PORT_MASK GENMASK(2, 0)
27
28#define MTK_QDMA_NUM_QUEUES 16
29#define MTK_QDMA_PAGE_SIZE 2048
30#define MTK_MAX_RX_LENGTH 1536
31#define MTK_MAX_RX_LENGTH_2K 2048
32#define MTK_TX_DMA_BUF_LEN 0x3fff
33#define MTK_TX_DMA_BUF_LEN_V2 0xffff
34#define MTK_QDMA_RING_SIZE 2048
35#define MTK_DMA_SIZE(x) (SZ_##x)
36#define MTK_FQ_DMA_HEAD 32
37#define MTK_FQ_DMA_LENGTH 2048
38#define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
39#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
40#define MTK_DMA_DUMMY_DESC 0xffffffff
41#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
42 NETIF_MSG_PROBE | \
43 NETIF_MSG_LINK | \
44 NETIF_MSG_TIMER | \
45 NETIF_MSG_IFDOWN | \
46 NETIF_MSG_IFUP | \
47 NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR)
49#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
50 NETIF_F_RXCSUM | \
51 NETIF_F_HW_VLAN_CTAG_TX | \
52 NETIF_F_SG | NETIF_F_TSO | \
53 NETIF_F_TSO6 | \
54 NETIF_F_IPV6_CSUM |\
55 NETIF_F_HW_TC)
56#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
57#define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
58
59#define MTK_PP_HEADROOM XDP_PACKET_HEADROOM
60#define MTK_PP_PAD (MTK_PP_HEADROOM + \
61 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
62#define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
63
64#define MTK_QRX_OFFSET 0x10
65
66#define MTK_MAX_RX_RING_NUM 4
67#define MTK_HW_LRO_DMA_SIZE 8
68
69#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
70#define MTK_MAX_LRO_IP_CNT 2
71#define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
72#define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
73#define MTK_HW_LRO_AGG_TIME 10 /* 200us */
74#define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
75#define MTK_HW_LRO_MAX_AGG_CNT 64
76#define MTK_HW_LRO_BW_THRE 3000
77#define MTK_HW_LRO_REPLACE_DELTA 1000
78#define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
79
80/* Frame Engine Global Configuration */
81#define MTK_FE_GLO_CFG(x) (((x) == MTK_GMAC3_ID) ? 0x24 : 0x00)
82#define MTK_FE_LINK_DOWN_P(x) BIT(((x) + 8) % 16)
83
84/* Frame Engine Global Reset Register */
85#define MTK_RST_GL 0x04
86#define RST_GL_PSE BIT(0)
87
88/* Frame Engine Interrupt Status Register */
89#define MTK_INT_STATUS2 0x08
90#define MTK_FE_INT_ENABLE 0x0c
91#define MTK_FE_INT_FQ_EMPTY BIT(8)
92#define MTK_FE_INT_TSO_FAIL BIT(12)
93#define MTK_FE_INT_TSO_ILLEGAL BIT(13)
94#define MTK_FE_INT_TSO_ALIGN BIT(14)
95#define MTK_FE_INT_RFIFO_OV BIT(18)
96#define MTK_FE_INT_RFIFO_UF BIT(19)
97#define MTK_GDM1_AF BIT(28)
98#define MTK_GDM2_AF BIT(29)
99
100/* PDMA HW LRO Alter Flow Timer Register */
101#define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
102
103/* Frame Engine Interrupt Grouping Register */
104#define MTK_FE_INT_GRP 0x20
105
106/* CDMP Ingress Control Register */
107#define MTK_CDMQ_IG_CTRL 0x1400
108#define MTK_CDMQ_STAG_EN BIT(0)
109
110/* CDMQ Exgress Control Register */
111#define MTK_CDMQ_EG_CTRL 0x1404
112
113/* CDMP Ingress Control Register */
114#define MTK_CDMP_IG_CTRL 0x400
115#define MTK_CDMP_STAG_EN BIT(0)
116
117/* CDMP Exgress Control Register */
118#define MTK_CDMP_EG_CTRL 0x404
119
120/* GDM Exgress Control Register */
121#define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
122 0x540 : 0x500 + (_x * 0x1000); })
123#define MTK_GDMA_SPECIAL_TAG BIT(24)
124#define MTK_GDMA_ICS_EN BIT(22)
125#define MTK_GDMA_TCS_EN BIT(21)
126#define MTK_GDMA_UCS_EN BIT(20)
127#define MTK_GDMA_STRP_CRC BIT(16)
128#define MTK_GDMA_TO_PDMA 0x0
129#define MTK_GDMA_DROP_ALL 0x7777
130
131/* GDM Egress Control Register */
132#define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
133 0x544 : 0x504 + (_x * 0x1000); })
134#define MTK_GDMA_XGDM_SEL BIT(31)
135
136/* Unicast Filter MAC Address Register - Low */
137#define MTK_GDMA_MAC_ADRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
138 0x548 : 0x508 + (_x * 0x1000); })
139
140/* Unicast Filter MAC Address Register - High */
141#define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
142 0x54C : 0x50C + (_x * 0x1000); })
143
144/* Internal SRAM offset */
145#define MTK_ETH_SRAM_OFFSET 0x40000
146
147/* FE global misc reg*/
148#define MTK_FE_GLO_MISC 0x124
149
150/* PSE Free Queue Flow Control */
151#define PSE_FQFC_CFG1 0x100
152#define PSE_FQFC_CFG2 0x104
153#define PSE_DROP_CFG 0x108
154#define PSE_PPE0_DROP 0x110
155
156/* PSE Input Queue Reservation Register*/
157#define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
158
159/* PSE Output Queue Threshold Register*/
160#define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
161
162/* GDM and CDM Threshold */
163#define MTK_GDM2_THRES 0x1530
164#define MTK_CDMW0_THRES 0x164c
165#define MTK_CDMW1_THRES 0x1650
166#define MTK_CDME0_THRES 0x1654
167#define MTK_CDME1_THRES 0x1658
168#define MTK_CDMM_THRES 0x165c
169
170/* PDMA HW LRO Control Registers */
171#define MTK_PDMA_LRO_CTRL_DW0 0x980
172#define MTK_LRO_EN BIT(0)
173#define MTK_L3_CKS_UPD_EN BIT(7)
174#define MTK_L3_CKS_UPD_EN_V2 BIT(19)
175#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
176#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
177#define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
178#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
179#define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
180
181#define MTK_PDMA_LRO_CTRL_DW1 0x984
182#define MTK_PDMA_LRO_CTRL_DW2 0x988
183#define MTK_PDMA_LRO_CTRL_DW3 0x98c
184#define MTK_ADMA_MODE BIT(15)
185#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
186
187#define MTK_RX_DMA_LRO_EN BIT(8)
188#define MTK_MULTI_EN BIT(10)
189#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
190
191/* PDMA Global Configuration Register */
192#define MTK_PDMA_LRO_SDL 0x3000
193#define MTK_RX_CFG_SDL_OFFSET 16
194
195/* PDMA Reset Index Register */
196#define MTK_PST_DRX_IDX0 BIT(16)
197#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
198
199/* PDMA Delay Interrupt Register */
200#define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
201#define MTK_PDMA_DELAY_RX_EN BIT(15)
202#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
203#define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
204
205#define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)
206#define MTK_PDMA_DELAY_TX_EN BIT(31)
207#define MTK_PDMA_DELAY_TX_PINT_SHIFT 24
208#define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16
209
210#define MTK_PDMA_DELAY_PINT_MASK 0x7f
211#define MTK_PDMA_DELAY_PTIME_MASK 0xff
212
213/* PDMA HW LRO Alter Flow Delta Register */
214#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
215
216/* PDMA HW LRO IP Setting Registers */
217#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
218#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
219#define MTK_RING_MYIP_VLD BIT(9)
220
221/* PDMA HW LRO Ring Control Registers */
222#define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
223#define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
224#define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
225#define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
226#define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
227#define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
228#define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
229#define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
230#define MTK_RING_AUTO_LERAN_MODE (3 << 6)
231#define MTK_RING_VLD BIT(8)
232#define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
233#define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
234#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
235
236/* QDMA TX Queue Configuration Registers */
237#define MTK_QTX_OFFSET 0x10
238#define QDMA_RES_THRES 4
239
240/* QDMA Tx Queue Scheduler Configuration Registers */
241#define MTK_QTX_SCH_TX_SEL BIT(31)
242#define MTK_QTX_SCH_TX_SEL_V2 GENMASK(31, 30)
243
244#define MTK_QTX_SCH_LEAKY_BUCKET_EN BIT(30)
245#define MTK_QTX_SCH_LEAKY_BUCKET_SIZE GENMASK(29, 28)
246#define MTK_QTX_SCH_MIN_RATE_EN BIT(27)
247#define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20)
248#define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16)
249#define MTK_QTX_SCH_MAX_RATE_WEIGHT GENMASK(15, 12)
250#define MTK_QTX_SCH_MAX_RATE_EN BIT(11)
251#define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4)
252#define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0)
253
254/* QDMA TX Scheduler Rate Control Register */
255#define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15)
256
257/* QDMA Global Configuration Register */
258#define MTK_RX_2B_OFFSET BIT(31)
259#define MTK_RX_BT_32DWORDS (3 << 11)
260#define MTK_NDP_CO_PRO BIT(10)
261#define MTK_TX_WB_DDONE BIT(6)
262#define MTK_TX_BT_32DWORDS (3 << 4)
263#define MTK_RX_DMA_BUSY BIT(3)
264#define MTK_TX_DMA_BUSY BIT(1)
265#define MTK_RX_DMA_EN BIT(2)
266#define MTK_TX_DMA_EN BIT(0)
267#define MTK_DMA_BUSY_TIMEOUT_US 1000000
268
269/* QDMA V2 Global Configuration Register */
270#define MTK_CHK_DDONE_EN BIT(28)
271#define MTK_DMAD_WR_WDONE BIT(26)
272#define MTK_WCOMP_EN BIT(24)
273#define MTK_RESV_BUF (0x40 << 16)
274#define MTK_MUTLI_CNT (0x4 << 12)
275#define MTK_LEAKY_BUCKET_EN BIT(11)
276
277/* QDMA Flow Control Register */
278#define FC_THRES_DROP_MODE BIT(20)
279#define FC_THRES_DROP_EN (7 << 16)
280#define FC_THRES_MIN 0x4444
281
282/* QDMA Interrupt Status Register */
283#define MTK_RX_DONE_DLY BIT(30)
284#define MTK_TX_DONE_DLY BIT(28)
285#define MTK_RX_DONE_INT3 BIT(19)
286#define MTK_RX_DONE_INT2 BIT(18)
287#define MTK_RX_DONE_INT1 BIT(17)
288#define MTK_RX_DONE_INT0 BIT(16)
289#define MTK_TX_DONE_INT3 BIT(3)
290#define MTK_TX_DONE_INT2 BIT(2)
291#define MTK_TX_DONE_INT1 BIT(1)
292#define MTK_TX_DONE_INT0 BIT(0)
293#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
294#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
295
296#define MTK_RX_DONE_INT_V2 BIT(14)
297
298#define MTK_CDM_TXFIFO_RDY BIT(7)
299
300/* QDMA Interrupt grouping registers */
301#define MTK_RLS_DONE_INT BIT(0)
302
303/* QDMA TX NUM */
304#define QID_BITS_V2(x) (((x) & 0x3f) << 16)
305#define MTK_QDMA_GMAC2_QID 8
306
307#define MTK_TX_DMA_BUF_SHIFT 8
308
309/* QDMA V2 descriptor txd6 */
310#define TX_DMA_INS_VLAN_V2 BIT(16)
311/* QDMA V2 descriptor txd5 */
312#define TX_DMA_CHKSUM_V2 (0x7 << 28)
313#define TX_DMA_TSO_V2 BIT(31)
314
315#define TX_DMA_SPTAG_V3 BIT(27)
316
317/* QDMA V2 descriptor txd4 */
318#define TX_DMA_FPORT_SHIFT_V2 8
319#define TX_DMA_FPORT_MASK_V2 0xf
320#define TX_DMA_SWC_V2 BIT(30)
321
322/* QDMA descriptor txd4 */
323#define TX_DMA_CHKSUM (0x7 << 29)
324#define TX_DMA_TSO BIT(28)
325#define TX_DMA_FPORT_SHIFT 25
326#define TX_DMA_FPORT_MASK 0x7
327#define TX_DMA_INS_VLAN BIT(16)
328
329/* QDMA descriptor txd3 */
330#define TX_DMA_OWNER_CPU BIT(31)
331#define TX_DMA_LS0 BIT(30)
332#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
333#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
334#define TX_DMA_SWC BIT(14)
335#define TX_DMA_PQID GENMASK(3, 0)
336#define TX_DMA_ADDR64_MASK GENMASK(3, 0)
337#if IS_ENABLED(CONFIG_64BIT)
338# define TX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(TX_DMA_ADDR64_MASK, (x))) << 32)
339# define TX_DMA_PREP_ADDR64(x) FIELD_PREP(TX_DMA_ADDR64_MASK, ((x) >> 32))
340#else
341# define TX_DMA_GET_ADDR64(x) (0)
342# define TX_DMA_PREP_ADDR64(x) (0)
343#endif
344
345/* PDMA on MT7628 */
346#define TX_DMA_DONE BIT(31)
347#define TX_DMA_LS1 BIT(14)
348#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
349
350/* QDMA descriptor rxd2 */
351#define RX_DMA_DONE BIT(31)
352#define RX_DMA_LSO BIT(30)
353#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
354#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
355#define RX_DMA_VTAG BIT(15)
356#define RX_DMA_ADDR64_MASK GENMASK(3, 0)
357#if IS_ENABLED(CONFIG_64BIT)
358# define RX_DMA_GET_ADDR64(x) (((u64)FIELD_GET(RX_DMA_ADDR64_MASK, (x))) << 32)
359# define RX_DMA_PREP_ADDR64(x) FIELD_PREP(RX_DMA_ADDR64_MASK, ((x) >> 32))
360#else
361# define RX_DMA_GET_ADDR64(x) (0)
362# define RX_DMA_PREP_ADDR64(x) (0)
363#endif
364
365/* QDMA descriptor rxd3 */
366#define RX_DMA_VID(x) ((x) & VLAN_VID_MASK)
367#define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
368#define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
369
370/* QDMA descriptor rxd4 */
371#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
372#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
373#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
374#define MTK_RXD4_ALG GENMASK(31, 22)
375
376/* QDMA descriptor rxd4 */
377#define RX_DMA_L4_VALID BIT(24)
378#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
379#define RX_DMA_SPECIAL_TAG BIT(22)
380
381/* PDMA descriptor rxd5 */
382#define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)
383#define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18)
384#define MTK_RXD5_SRC_PORT GENMASK(29, 26)
385
386#define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7)
387#define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf)
388
389/* PDMA V2 descriptor rxd3 */
390#define RX_DMA_VTAG_V2 BIT(0)
391#define RX_DMA_L4_VALID_V2 BIT(2)
392
393/* PHY Polling and SMI Master Control registers */
394#define MTK_PPSC 0x10000
395#define PPSC_MDC_CFG GENMASK(29, 24)
396#define PPSC_MDC_TURBO BIT(20)
397#define MDC_MAX_FREQ 25000000
398#define MDC_MAX_DIVIDER 63
399
400/* PHY Indirect Access Control registers */
401#define MTK_PHY_IAC 0x10004
402#define PHY_IAC_ACCESS BIT(31)
403#define PHY_IAC_REG_MASK GENMASK(29, 25)
404#define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x))
405#define PHY_IAC_ADDR_MASK GENMASK(24, 20)
406#define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
407#define PHY_IAC_CMD_MASK GENMASK(19, 18)
408#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
409#define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
410#define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
411#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
412#define PHY_IAC_START_MASK GENMASK(17, 16)
413#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
414#define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
415#define PHY_IAC_DATA_MASK GENMASK(15, 0)
416#define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
417#define PHY_IAC_TIMEOUT HZ
418
419#define MTK_MAC_MISC 0x1000c
420#define MTK_MAC_MISC_V3 0x10010
421#define MTK_MUX_TO_ESW BIT(0)
422#define MISC_MDC_TURBO BIT(4)
423
424/* XMAC status registers */
425#define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
426#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
427#define MTK_USXGMII_PCS_LINK BIT(8)
428#define MTK_XGMAC_RX_FC BIT(5)
429#define MTK_XGMAC_TX_FC BIT(4)
430#define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
431#define MTK_XGMAC_LINK_STS BIT(0)
432
433/* GSW bridge registers */
434#define MTK_GSW_CFG (0x10080)
435#define GSWTX_IPG_MASK GENMASK(19, 16)
436#define GSWTX_IPG_SHIFT 16
437#define GSWRX_IPG_MASK GENMASK(3, 0)
438#define GSWRX_IPG_SHIFT 0
439#define GSW_IPG_11 11
440
441/* Mac control registers */
442#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
443#define MAC_MCR_MAX_RX_MASK GENMASK(25, 24)
444#define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24))
445#define MAC_MCR_MAX_RX_1518 0x0
446#define MAC_MCR_MAX_RX_1536 0x1
447#define MAC_MCR_MAX_RX_1552 0x2
448#define MAC_MCR_MAX_RX_2048 0x3
449#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
450#define MAC_MCR_FORCE_MODE BIT(15)
451#define MAC_MCR_TX_EN BIT(14)
452#define MAC_MCR_RX_EN BIT(13)
453#define MAC_MCR_RX_FIFO_CLR_DIS BIT(12)
454#define MAC_MCR_BACKOFF_EN BIT(9)
455#define MAC_MCR_BACKPR_EN BIT(8)
456#define MAC_MCR_FORCE_RX_FC BIT(5)
457#define MAC_MCR_FORCE_TX_FC BIT(4)
458#define MAC_MCR_SPEED_1000 BIT(3)
459#define MAC_MCR_SPEED_100 BIT(2)
460#define MAC_MCR_FORCE_DPX BIT(1)
461#define MAC_MCR_FORCE_LINK BIT(0)
462#define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
463
464/* Mac status registers */
465#define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
466#define MAC_MSR_EEE1G BIT(7)
467#define MAC_MSR_EEE100M BIT(6)
468#define MAC_MSR_RX_FC BIT(5)
469#define MAC_MSR_TX_FC BIT(4)
470#define MAC_MSR_SPEED_1000 BIT(3)
471#define MAC_MSR_SPEED_100 BIT(2)
472#define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
473#define MAC_MSR_DPX BIT(1)
474#define MAC_MSR_LINK BIT(0)
475
476/* TRGMII RXC control register */
477#define TRGMII_RCK_CTRL 0x10300
478#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
479#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
480#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
481#define RXC_RST BIT(31)
482#define RXC_DQSISEL BIT(30)
483#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
484#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
485
486#define NUM_TRGMII_CTRL 5
487
488/* TRGMII RXC control register */
489#define TRGMII_TCK_CTRL 0x10340
490#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
491#define TXC_INV BIT(30)
492#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
493#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
494
495/* TRGMII TX Drive Strength */
496#define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
497#define TD_DM_DRVP(x) ((x) & 0xf)
498#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
499
500/* TRGMII Interface mode register */
501#define INTF_MODE 0x10390
502#define TRGMII_INTF_DIS BIT(0)
503#define TRGMII_MODE BIT(1)
504#define TRGMII_CENTRAL_ALIGNED BIT(2)
505#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
506#define INTF_MODE_RGMII_10_100 0
507
508/* GPIO port control registers for GMAC 2*/
509#define GPIO_OD33_CTRL8 0x4c0
510#define GPIO_BIAS_CTRL 0xed0
511#define GPIO_DRV_SEL10 0xf00
512
513/* ethernet subsystem chip id register */
514#define ETHSYS_CHIPID0_3 0x0
515#define ETHSYS_CHIPID4_7 0x4
516#define MT7623_ETH 7623
517#define MT7622_ETH 7622
518#define MT7621_ETH 7621
519
520/* ethernet system control register */
521#define ETHSYS_SYSCFG 0x10
522#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
523
524/* ethernet subsystem config register */
525#define ETHSYS_SYSCFG0 0x14
526#define SYSCFG0_GE_MASK 0x3
527#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
528#define SYSCFG0_SGMII_MASK GENMASK(9, 7)
529#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
530#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
531#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
532#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
533
534
535/* ethernet subsystem clock register */
536#define ETHSYS_CLKCFG0 0x2c
537#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
538#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
539#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
540#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
541
542/* ethernet reset control register */
543#define ETHSYS_RSTCTRL 0x34
544#define RSTCTRL_FE BIT(6)
545#define RSTCTRL_WDMA0 BIT(24)
546#define RSTCTRL_WDMA1 BIT(25)
547#define RSTCTRL_WDMA2 BIT(26)
548#define RSTCTRL_PPE0 BIT(31)
549#define RSTCTRL_PPE0_V2 BIT(30)
550#define RSTCTRL_PPE1 BIT(31)
551#define RSTCTRL_PPE0_V3 BIT(29)
552#define RSTCTRL_PPE1_V3 BIT(30)
553#define RSTCTRL_PPE2 BIT(31)
554#define RSTCTRL_ETH BIT(23)
555
556/* ethernet reset check idle register */
557#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
558
559/* ethernet dma channel agent map */
560#define ETHSYS_DMA_AG_MAP 0x408
561#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
562#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
563#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
564
565/* Infrasys subsystem config registers */
566#define INFRA_MISC2 0x70c
567#define CO_QPHY_SEL BIT(0)
568#define GEPHY_MAC_SEL BIT(1)
569
570/* Top misc registers */
571#define USB_PHY_SWITCH_REG 0x218
572#define QPHY_SEL_MASK GENMASK(1, 0)
573#define SGMII_QPHY_SEL 0x2
574
575/* MT7628/88 specific stuff */
576#define MT7628_PDMA_OFFSET 0x0800
577#define MT7628_SDM_OFFSET 0x0c00
578
579#define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
580#define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
581#define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
582#define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
583#define MT7628_PST_DTX_IDX0 BIT(0)
584
585#define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
586#define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
587
588/* Counter / stat register */
589#define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
590#define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
591#define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
592#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
593#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
594
595#define MTK_FE_CDM1_FSM 0x220
596#define MTK_FE_CDM2_FSM 0x224
597#define MTK_FE_CDM3_FSM 0x238
598#define MTK_FE_CDM4_FSM 0x298
599#define MTK_FE_CDM5_FSM 0x318
600#define MTK_FE_CDM6_FSM 0x328
601#define MTK_FE_GDM1_FSM 0x228
602#define MTK_FE_GDM2_FSM 0x22C
603
604#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
605
606struct mtk_rx_dma {
607 unsigned int rxd1;
608 unsigned int rxd2;
609 unsigned int rxd3;
610 unsigned int rxd4;
611} __packed __aligned(4);
612
613struct mtk_rx_dma_v2 {
614 unsigned int rxd1;
615 unsigned int rxd2;
616 unsigned int rxd3;
617 unsigned int rxd4;
618 unsigned int rxd5;
619 unsigned int rxd6;
620 unsigned int rxd7;
621 unsigned int rxd8;
622} __packed __aligned(4);
623
624struct mtk_tx_dma {
625 unsigned int txd1;
626 unsigned int txd2;
627 unsigned int txd3;
628 unsigned int txd4;
629} __packed __aligned(4);
630
631struct mtk_tx_dma_v2 {
632 unsigned int txd1;
633 unsigned int txd2;
634 unsigned int txd3;
635 unsigned int txd4;
636 unsigned int txd5;
637 unsigned int txd6;
638 unsigned int txd7;
639 unsigned int txd8;
640} __packed __aligned(4);
641
642struct mtk_eth;
643struct mtk_mac;
644
645struct mtk_xdp_stats {
646 u64 rx_xdp_redirect;
647 u64 rx_xdp_pass;
648 u64 rx_xdp_drop;
649 u64 rx_xdp_tx;
650 u64 rx_xdp_tx_errors;
651 u64 tx_xdp_xmit;
652 u64 tx_xdp_xmit_errors;
653};
654
655/* struct mtk_hw_stats - the structure that holds the traffic statistics.
656 * @stats_lock: make sure that stats operations are atomic
657 * @reg_offset: the status register offset of the SoC
658 * @syncp: the refcount
659 *
660 * All of the supported SoCs have hardware counters for traffic statistics.
661 * Whenever the status IRQ triggers we can read the latest stats from these
662 * counters and store them in this struct.
663 */
664struct mtk_hw_stats {
665 u64 tx_bytes;
666 u64 tx_packets;
667 u64 tx_skip;
668 u64 tx_collisions;
669 u64 rx_bytes;
670 u64 rx_packets;
671 u64 rx_overflow;
672 u64 rx_fcs_errors;
673 u64 rx_short_errors;
674 u64 rx_long_errors;
675 u64 rx_checksum_errors;
676 u64 rx_flow_control_packets;
677
678 struct mtk_xdp_stats xdp_stats;
679
680 spinlock_t stats_lock;
681 u32 reg_offset;
682 struct u64_stats_sync syncp;
683};
684
685enum mtk_tx_flags {
686 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
687 * track how memory was allocated so that it can be freed properly.
688 */
689 MTK_TX_FLAGS_SINGLE0 = 0x01,
690 MTK_TX_FLAGS_PAGE0 = 0x02,
691};
692
693/* This enum allows us to identify how the clock is defined on the array of the
694 * clock in the order
695 */
696enum mtk_clks_map {
697 MTK_CLK_ETHIF,
698 MTK_CLK_SGMIITOP,
699 MTK_CLK_ESW,
700 MTK_CLK_GP0,
701 MTK_CLK_GP1,
702 MTK_CLK_GP2,
703 MTK_CLK_GP3,
704 MTK_CLK_XGP1,
705 MTK_CLK_XGP2,
706 MTK_CLK_XGP3,
707 MTK_CLK_CRYPTO,
708 MTK_CLK_FE,
709 MTK_CLK_TRGPLL,
710 MTK_CLK_SGMII_TX_250M,
711 MTK_CLK_SGMII_RX_250M,
712 MTK_CLK_SGMII_CDR_REF,
713 MTK_CLK_SGMII_CDR_FB,
714 MTK_CLK_SGMII2_TX_250M,
715 MTK_CLK_SGMII2_RX_250M,
716 MTK_CLK_SGMII2_CDR_REF,
717 MTK_CLK_SGMII2_CDR_FB,
718 MTK_CLK_SGMII_CK,
719 MTK_CLK_ETH2PLL,
720 MTK_CLK_WOCPU0,
721 MTK_CLK_WOCPU1,
722 MTK_CLK_NETSYS0,
723 MTK_CLK_NETSYS1,
724 MTK_CLK_ETHWARP_WOCPU2,
725 MTK_CLK_ETHWARP_WOCPU1,
726 MTK_CLK_ETHWARP_WOCPU0,
727 MTK_CLK_TOP_SGM_0_SEL,
728 MTK_CLK_TOP_SGM_1_SEL,
729 MTK_CLK_TOP_ETH_GMII_SEL,
730 MTK_CLK_TOP_ETH_REFCK_50M_SEL,
731 MTK_CLK_TOP_ETH_SYS_200M_SEL,
732 MTK_CLK_TOP_ETH_SYS_SEL,
733 MTK_CLK_TOP_ETH_XGMII_SEL,
734 MTK_CLK_TOP_ETH_MII_SEL,
735 MTK_CLK_TOP_NETSYS_SEL,
736 MTK_CLK_TOP_NETSYS_500M_SEL,
737 MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
738 MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
739 MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
740 MTK_CLK_TOP_NETSYS_WARP_SEL,
741 MTK_CLK_MAX
742};
743
744#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
745 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
746 BIT_ULL(MTK_CLK_TRGPLL))
747#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
748 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
749 BIT_ULL(MTK_CLK_GP2) | \
750 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
751 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
752 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
753 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
754 BIT_ULL(MTK_CLK_SGMII_CK) | \
755 BIT_ULL(MTK_CLK_ETH2PLL))
756#define MT7621_CLKS_BITMAP (0)
757#define MT7628_CLKS_BITMAP (0)
758#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
759 BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
760 BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
761 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
762 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
763 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
764 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
765 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
766 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
767 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
768 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
769 BIT_ULL(MTK_CLK_SGMII_CK) | \
770 BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
771#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
772 BIT_ULL(MTK_CLK_GP1) | \
773 BIT_ULL(MTK_CLK_WOCPU0) | \
774 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
775 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
776 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
777 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
778 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
779 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
780 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
781 BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
782 BIT_ULL(MTK_CLK_SGMII_CK))
783#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \
784 BIT_ULL(MTK_CLK_GP1) | \
785 BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
786 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
787 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
788 BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
789 BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
790 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
791 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
792 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
793 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
794#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
795 BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
796 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
797 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
798 BIT_ULL(MTK_CLK_CRYPTO) | \
799 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
800 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
801 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
802 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
803 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
804 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
805 BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
806 BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
807 BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
808 BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
809 BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
810 BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
811 BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
812 BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
813 BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
814
815enum mtk_dev_state {
816 MTK_HW_INIT,
817 MTK_RESETTING
818};
819
820/* PSE Port Definition */
821enum mtk_pse_port {
822 PSE_ADMA_PORT = 0,
823 PSE_GDM1_PORT,
824 PSE_GDM2_PORT,
825 PSE_PPE0_PORT,
826 PSE_PPE1_PORT,
827 PSE_QDMA_TX_PORT,
828 PSE_QDMA_RX_PORT,
829 PSE_DROP_PORT,
830 PSE_WDMA0_PORT,
831 PSE_WDMA1_PORT,
832 PSE_TDMA_PORT,
833 PSE_NONE_PORT,
834 PSE_PPE2_PORT,
835 PSE_WDMA2_PORT,
836 PSE_EIP197_PORT,
837 PSE_GDM3_PORT,
838 PSE_PORT_MAX
839};
840
841/* GMAC Identifier */
842enum mtk_gmac_id {
843 MTK_GMAC1_ID = 0,
844 MTK_GMAC2_ID,
845 MTK_GMAC3_ID,
846 MTK_GMAC_ID_MAX
847};
848
849enum mtk_tx_buf_type {
850 MTK_TYPE_SKB,
851 MTK_TYPE_XDP_TX,
852 MTK_TYPE_XDP_NDO,
853};
854
855/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
856 * by the TX descriptor s
857 * @skb: The SKB pointer of the packet being sent
858 * @dma_addr0: The base addr of the first segment
859 * @dma_len0: The length of the first segment
860 * @dma_addr1: The base addr of the second segment
861 * @dma_len1: The length of the second segment
862 */
863struct mtk_tx_buf {
864 enum mtk_tx_buf_type type;
865 void *data;
866
867 u16 mac_id;
868 u16 flags;
869 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
870 DEFINE_DMA_UNMAP_LEN(dma_len0);
871 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
872 DEFINE_DMA_UNMAP_LEN(dma_len1);
873};
874
875/* struct mtk_tx_ring - This struct holds info describing a TX ring
876 * @dma: The descriptor ring
877 * @buf: The memory pointed at by the ring
878 * @phys: The physical addr of tx_buf
879 * @next_free: Pointer to the next free descriptor
880 * @last_free: Pointer to the last free descriptor
881 * @last_free_ptr: Hardware pointer value of the last free descriptor
882 * @thresh: The threshold of minimum amount of free descriptors
883 * @free_count: QDMA uses a linked list. Track how many free descriptors
884 * are present
885 */
886struct mtk_tx_ring {
887 void *dma;
888 struct mtk_tx_buf *buf;
889 dma_addr_t phys;
890 struct mtk_tx_dma *next_free;
891 struct mtk_tx_dma *last_free;
892 u32 last_free_ptr;
893 u16 thresh;
894 atomic_t free_count;
895 int dma_size;
896 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
897 dma_addr_t phys_pdma;
898 int cpu_idx;
899};
900
901/* PDMA rx ring mode */
902enum mtk_rx_flags {
903 MTK_RX_FLAGS_NORMAL = 0,
904 MTK_RX_FLAGS_HWLRO,
905 MTK_RX_FLAGS_QDMA,
906};
907
908/* struct mtk_rx_ring - This struct holds info describing a RX ring
909 * @dma: The descriptor ring
910 * @data: The memory pointed at by the ring
911 * @phys: The physical addr of rx_buf
912 * @frag_size: How big can each fragment be
913 * @buf_size: The size of each packet buffer
914 * @calc_idx: The current head of ring
915 */
916struct mtk_rx_ring {
917 void *dma;
918 u8 **data;
919 dma_addr_t phys;
920 u16 frag_size;
921 u16 buf_size;
922 u16 dma_size;
923 bool calc_idx_update;
924 u16 calc_idx;
925 u32 crx_idx_reg;
926 /* page_pool */
927 struct page_pool *page_pool;
928 struct xdp_rxq_info xdp_q;
929};
930
931enum mkt_eth_capabilities {
932 MTK_RGMII_BIT = 0,
933 MTK_TRGMII_BIT,
934 MTK_SGMII_BIT,
935 MTK_ESW_BIT,
936 MTK_GEPHY_BIT,
937 MTK_MUX_BIT,
938 MTK_INFRA_BIT,
939 MTK_SHARED_SGMII_BIT,
940 MTK_HWLRO_BIT,
941 MTK_SHARED_INT_BIT,
942 MTK_TRGMII_MT7621_CLK_BIT,
943 MTK_QDMA_BIT,
944 MTK_SOC_MT7628_BIT,
945 MTK_RSTCTRL_PPE1_BIT,
946 MTK_RSTCTRL_PPE2_BIT,
947 MTK_U3_COPHY_V2_BIT,
948 MTK_SRAM_BIT,
949 MTK_36BIT_DMA_BIT,
950
951 /* MUX BITS*/
952 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
953 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
954 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
955 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
956 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
957
958 /* PATH BITS */
959 MTK_ETH_PATH_GMAC1_RGMII_BIT,
960 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
961 MTK_ETH_PATH_GMAC1_SGMII_BIT,
962 MTK_ETH_PATH_GMAC2_RGMII_BIT,
963 MTK_ETH_PATH_GMAC2_SGMII_BIT,
964 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
965 MTK_ETH_PATH_GDM1_ESW_BIT,
966};
967
968/* Supported hardware group on SoCs */
969#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
970#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
971#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
972#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
973#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
974#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
975#define MTK_INFRA BIT_ULL(MTK_INFRA_BIT)
976#define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT)
977#define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT)
978#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT)
979#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT)
980#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT)
981#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT)
982#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT)
983#define MTK_RSTCTRL_PPE2 BIT_ULL(MTK_RSTCTRL_PPE2_BIT)
984#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT)
985#define MTK_SRAM BIT_ULL(MTK_SRAM_BIT)
986#define MTK_36BIT_DMA BIT_ULL(MTK_36BIT_DMA_BIT)
987
988#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
989 BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
990#define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
991 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
992#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
993 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
994#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
995 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
996#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
997 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
998
999/* Supported path present on SoCs */
1000#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
1001#define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
1002#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
1003#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
1004#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
1005#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
1006#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
1007
1008#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
1009#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
1010#define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
1011#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
1012#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
1013#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
1014#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
1015
1016/* MUXes present on SoCs */
1017/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1018#define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
1019
1020/* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
1021#define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
1022 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
1023
1024/* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1025#define MTK_MUX_U3_GMAC2_TO_QPHY \
1026 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
1027
1028/* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
1029#define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
1030 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
1031 MTK_SHARED_SGMII)
1032
1033/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
1034#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
1035 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
1036
1037#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
1038
1039#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
1040 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
1041 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
1042
1043#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
1044 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
1045 MTK_MUX_GDM1_TO_GMAC1_ESW | \
1046 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
1047
1048#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
1049 MTK_QDMA)
1050
1051#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
1052
1053#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1054 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
1055 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
1056 MTK_MUX_U3_GMAC2_TO_QPHY | \
1057 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
1058
1059#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
1060 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1061 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
1062 MTK_RSTCTRL_PPE1 | MTK_SRAM)
1063
1064#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
1065 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
1066 MTK_RSTCTRL_PPE1 | MTK_SRAM)
1067
1068#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
1069 MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
1070
1071struct mtk_tx_dma_desc_info {
1072 dma_addr_t addr;
1073 u32 size;
1074 u16 vlan_tci;
1075 u16 qid;
1076 u8 gso:1;
1077 u8 csum:1;
1078 u8 vlan:1;
1079 u8 first:1;
1080 u8 last:1;
1081};
1082
1083struct mtk_reg_map {
1084 u32 tx_irq_mask;
1085 u32 tx_irq_status;
1086 struct {
1087 u32 rx_ptr; /* rx base pointer */
1088 u32 rx_cnt_cfg; /* rx max count configuration */
1089 u32 pcrx_ptr; /* rx cpu pointer */
1090 u32 glo_cfg; /* global configuration */
1091 u32 rst_idx; /* reset index */
1092 u32 delay_irq; /* delay interrupt */
1093 u32 irq_status; /* interrupt status */
1094 u32 irq_mask; /* interrupt mask */
1095 u32 adma_rx_dbg0;
1096 u32 int_grp;
1097 } pdma;
1098 struct {
1099 u32 qtx_cfg; /* tx queue configuration */
1100 u32 qtx_sch; /* tx queue scheduler configuration */
1101 u32 rx_ptr; /* rx base pointer */
1102 u32 rx_cnt_cfg; /* rx max count configuration */
1103 u32 qcrx_ptr; /* rx cpu pointer */
1104 u32 glo_cfg; /* global configuration */
1105 u32 rst_idx; /* reset index */
1106 u32 delay_irq; /* delay interrupt */
1107 u32 fc_th; /* flow control */
1108 u32 int_grp;
1109 u32 hred; /* interrupt mask */
1110 u32 ctx_ptr; /* tx acquire cpu pointer */
1111 u32 dtx_ptr; /* tx acquire dma pointer */
1112 u32 crx_ptr; /* tx release cpu pointer */
1113 u32 drx_ptr; /* tx release dma pointer */
1114 u32 fq_head; /* fq head pointer */
1115 u32 fq_tail; /* fq tail pointer */
1116 u32 fq_count; /* fq free page count */
1117 u32 fq_blen; /* fq free page buffer length */
1118 u32 tx_sch_rate; /* tx scheduler rate control registers */
1119 } qdma;
1120 u32 gdm1_cnt;
1121 u32 gdma_to_ppe[3];
1122 u32 ppe_base;
1123 u32 wdma_base[3];
1124 u32 pse_iq_sta;
1125 u32 pse_oq_sta;
1126};
1127
1128/* struct mtk_eth_data - This is the structure holding all differences
1129 * among various plaforms
1130 * @reg_map Soc register map.
1131 * @ana_rgc3: The offset for register ANA_RGC3 related to
1132 * sgmiisys syscon
1133 * @caps Flags shown the extra capability for the SoC
1134 * @hw_features Flags shown HW features
1135 * @required_clks Flags shown the bitmap for required clocks on
1136 * the target SoC
1137 * @required_pctl A bool value to show whether the SoC requires
1138 * the extra setup for those pins used by GMAC.
1139 * @hash_offset Flow table hash offset.
1140 * @version SoC version.
1141 * @foe_entry_size Foe table entry size.
1142 * @has_accounting Bool indicating support for accounting of
1143 * offloaded flows.
1144 * @desc_size Tx/Rx DMA descriptor size.
1145 * @irq_done_mask Rx irq done register mask.
1146 * @dma_l4_valid Rx DMA valid register mask.
1147 * @dma_max_len Max DMA tx/rx buffer length.
1148 * @dma_len_offset Tx/Rx DMA length field offset.
1149 */
1150struct mtk_soc_data {
1151 const struct mtk_reg_map *reg_map;
1152 u32 ana_rgc3;
1153 u64 caps;
1154 u64 required_clks;
1155 bool required_pctl;
1156 u8 offload_version;
1157 u8 hash_offset;
1158 u8 version;
1159 u8 ppe_num;
1160 u16 foe_entry_size;
1161 netdev_features_t hw_features;
1162 bool has_accounting;
1163 bool disable_pll_modes;
1164 struct {
1165 u32 desc_size;
1166 u32 dma_max_len;
1167 u32 dma_len_offset;
1168 u32 dma_size;
1169 u32 fq_dma_size;
1170 } tx;
1171 struct {
1172 u32 desc_size;
1173 u32 irq_done_mask;
1174 u32 dma_l4_valid;
1175 u32 dma_max_len;
1176 u32 dma_len_offset;
1177 u32 dma_size;
1178 } rx;
1179};
1180
1181#define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
1182
1183/* currently no SoC has more than 3 macs */
1184#define MTK_MAX_DEVS 3
1185
1186/* struct mtk_eth - This is the main datasructure for holding the state
1187 * of the driver
1188 * @dev: The device pointer
1189 * @dev: The device pointer used for dma mapping/alloc
1190 * @base: The mapped register i/o base
1191 * @page_lock: Make sure that register operations are atomic
1192 * @tx_irq__lock: Make sure that IRQ register operations are atomic
1193 * @rx_irq__lock: Make sure that IRQ register operations are atomic
1194 * @dim_lock: Make sure that Net DIM operations are atomic
1195 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1196 * dummy for NAPI to work
1197 * @netdev: The netdev instances
1198 * @mac: Each netdev is linked to a physical MAC
1199 * @irq: The IRQ that we are using
1200 * @msg_enable: Ethtool msg level
1201 * @ethsys: The register map pointing at the range used to setup
1202 * MII modes
1203 * @infra: The register map pointing at the range used to setup
1204 * SGMII and GePHY path
1205 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
1206 * @pctl: The register map pointing at the range used to setup
1207 * GMAC port drive/slew values
1208 * @dma_refcnt: track how many netdevs are using the DMA engine
1209 * @tx_ring: Pointer to the memory holding info about the TX ring
1210 * @rx_ring: Pointer to the memory holding info about the RX ring
1211 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
1212 * @tx_napi: The TX NAPI struct
1213 * @rx_napi: The RX NAPI struct
1214 * @rx_events: Net DIM RX event counter
1215 * @rx_packets: Net DIM RX packet counter
1216 * @rx_bytes: Net DIM RX byte counter
1217 * @rx_dim: Net DIM RX context
1218 * @tx_events: Net DIM TX event counter
1219 * @tx_packets: Net DIM TX packet counter
1220 * @tx_bytes: Net DIM TX byte counter
1221 * @tx_dim: Net DIM TX context
1222 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
1223 * @phy_scratch_ring: physical address of scratch_ring
1224 * @scratch_head: The scratch memory that scratch_ring points to.
1225 * @clks: clock array for all clocks required
1226 * @mii_bus: If there is a bus we need to create an instance for it
1227 * @pending_work: The workqueue used to reset the dma ring
1228 * @state: Initialization and runtime state of the device
1229 * @soc: Holding specific data among vaious SoCs
1230 */
1231
1232struct mtk_eth {
1233 struct device *dev;
1234 struct device *dma_dev;
1235 void __iomem *base;
1236 void *sram_base;
1237 spinlock_t page_lock;
1238 spinlock_t tx_irq_lock;
1239 spinlock_t rx_irq_lock;
1240 struct net_device *dummy_dev;
1241 struct net_device *netdev[MTK_MAX_DEVS];
1242 struct mtk_mac *mac[MTK_MAX_DEVS];
1243 int irq[3];
1244 u32 msg_enable;
1245 unsigned long sysclk;
1246 struct regmap *ethsys;
1247 struct regmap *infra;
1248 struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
1249 struct regmap *pctl;
1250 bool hwlro;
1251 refcount_t dma_refcnt;
1252 struct mtk_tx_ring tx_ring;
1253 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
1254 struct mtk_rx_ring rx_ring_qdma;
1255 struct napi_struct tx_napi;
1256 struct napi_struct rx_napi;
1257 void *scratch_ring;
1258 dma_addr_t phy_scratch_ring;
1259 void *scratch_head[MTK_FQ_DMA_HEAD];
1260 struct clk *clks[MTK_CLK_MAX];
1261
1262 struct mii_bus *mii_bus;
1263 struct work_struct pending_work;
1264 unsigned long state;
1265
1266 const struct mtk_soc_data *soc;
1267
1268 spinlock_t dim_lock;
1269
1270 u32 rx_events;
1271 u32 rx_packets;
1272 u32 rx_bytes;
1273 struct dim rx_dim;
1274
1275 u32 tx_events;
1276 u32 tx_packets;
1277 u32 tx_bytes;
1278 struct dim tx_dim;
1279
1280 int ip_align;
1281
1282 struct metadata_dst *dsa_meta[MTK_MAX_DSA_PORTS];
1283
1284 struct mtk_ppe *ppe[3];
1285 struct rhashtable flow_table;
1286
1287 struct bpf_prog __rcu *prog;
1288
1289 struct {
1290 struct delayed_work monitor_work;
1291 u32 wdidx;
1292 u8 wdma_hang_count;
1293 u8 qdma_hang_count;
1294 u8 adma_hang_count;
1295 } reset;
1296};
1297
1298/* struct mtk_mac - the structure that holds the info about the MACs of the
1299 * SoC
1300 * @id: The number of the MAC
1301 * @interface: Interface mode kept for detecting change in hw settings
1302 * @of_node: Our devicetree node
1303 * @hw: Backpointer to our main datastruture
1304 * @hw_stats: Packet statistics counter
1305 */
1306struct mtk_mac {
1307 int id;
1308 phy_interface_t interface;
1309 u8 ppe_idx;
1310 int speed;
1311 struct device_node *of_node;
1312 struct phylink *phylink;
1313 struct phylink_config phylink_config;
1314 struct mtk_eth *hw;
1315 struct mtk_hw_stats *hw_stats;
1316 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1317 int hwlro_ip_cnt;
1318 unsigned int syscfg0;
1319 struct notifier_block device_notifier;
1320};
1321
1322/* the struct describing the SoC. these are declared in the soc_xyz.c files */
1323extern const struct of_device_id of_mtk_match[];
1324
1325static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
1326{
1327 return eth->soc->version == 1;
1328}
1329
1330static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
1331{
1332 return eth->soc->version > 1;
1333}
1334
1335static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth)
1336{
1337 return eth->soc->version > 2;
1338}
1339
1340static inline struct mtk_foe_entry *
1341mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
1342{
1343 const struct mtk_soc_data *soc = ppe->eth->soc;
1344
1345 return ppe->foe_table + hash * soc->foe_entry_size;
1346}
1347
1348static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
1349{
1350 if (mtk_is_netsys_v2_or_greater(eth))
1351 return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
1352
1353 return MTK_FOE_IB1_BIND_TIMESTAMP;
1354}
1355
1356static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
1357{
1358 if (mtk_is_netsys_v2_or_greater(eth))
1359 return MTK_FOE_IB1_BIND_PPPOE_V2;
1360
1361 return MTK_FOE_IB1_BIND_PPPOE;
1362}
1363
1364static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
1365{
1366 if (mtk_is_netsys_v2_or_greater(eth))
1367 return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
1368
1369 return MTK_FOE_IB1_BIND_VLAN_TAG;
1370}
1371
1372static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
1373{
1374 if (mtk_is_netsys_v2_or_greater(eth))
1375 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
1376
1377 return MTK_FOE_IB1_BIND_VLAN_LAYER;
1378}
1379
1380static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
1381{
1382 if (mtk_is_netsys_v2_or_greater(eth))
1383 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
1384
1385 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
1386}
1387
1388static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
1389{
1390 if (mtk_is_netsys_v2_or_greater(eth))
1391 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
1392
1393 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
1394}
1395
1396static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
1397{
1398 if (mtk_is_netsys_v2_or_greater(eth))
1399 return MTK_FOE_IB1_PACKET_TYPE_V2;
1400
1401 return MTK_FOE_IB1_PACKET_TYPE;
1402}
1403
1404static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
1405{
1406 if (mtk_is_netsys_v2_or_greater(eth))
1407 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
1408
1409 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
1410}
1411
1412static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
1413{
1414 if (mtk_is_netsys_v2_or_greater(eth))
1415 return MTK_FOE_IB2_MULTICAST_V2;
1416
1417 return MTK_FOE_IB2_MULTICAST;
1418}
1419
1420/* read the hardware status register */
1421void mtk_stats_update_mac(struct mtk_mac *mac);
1422
1423void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1424u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1425u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
1426
1427int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1428int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1429int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
1430
1431int mtk_eth_offload_init(struct mtk_eth *eth, u8 id);
1432int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
1433 void *type_data);
1434int mtk_flow_offload_cmd(struct mtk_eth *eth, struct flow_cls_offload *cls,
1435 int ppe_index);
1436void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
1437void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
1438
1439
1440#endif /* MTK_ETH_H */