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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/bitfield.h>
5#include <linux/net/intel/libie/rx.h>
6#include <linux/prefetch.h>
7
8#include "iavf.h"
9#include "iavf_trace.h"
10#include "iavf_prototype.h"
11
12static __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
13 u32 td_tag)
14{
15 return cpu_to_le64(IAVF_TX_DESC_DTYPE_DATA |
16 ((u64)td_cmd << IAVF_TXD_QW1_CMD_SHIFT) |
17 ((u64)td_offset << IAVF_TXD_QW1_OFFSET_SHIFT) |
18 ((u64)size << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
19 ((u64)td_tag << IAVF_TXD_QW1_L2TAG1_SHIFT));
20}
21
22#define IAVF_TXD_CMD (IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_RS)
23
24/**
25 * iavf_unmap_and_free_tx_resource - Release a Tx buffer
26 * @ring: the ring that owns the buffer
27 * @tx_buffer: the buffer to free
28 **/
29static void iavf_unmap_and_free_tx_resource(struct iavf_ring *ring,
30 struct iavf_tx_buffer *tx_buffer)
31{
32 if (tx_buffer->skb) {
33 if (tx_buffer->tx_flags & IAVF_TX_FLAGS_FD_SB)
34 kfree(tx_buffer->raw_buf);
35 else
36 dev_kfree_skb_any(tx_buffer->skb);
37 if (dma_unmap_len(tx_buffer, len))
38 dma_unmap_single(ring->dev,
39 dma_unmap_addr(tx_buffer, dma),
40 dma_unmap_len(tx_buffer, len),
41 DMA_TO_DEVICE);
42 } else if (dma_unmap_len(tx_buffer, len)) {
43 dma_unmap_page(ring->dev,
44 dma_unmap_addr(tx_buffer, dma),
45 dma_unmap_len(tx_buffer, len),
46 DMA_TO_DEVICE);
47 }
48
49 tx_buffer->next_to_watch = NULL;
50 tx_buffer->skb = NULL;
51 dma_unmap_len_set(tx_buffer, len, 0);
52 /* tx_buffer must be completely set up in the transmit path */
53}
54
55/**
56 * iavf_clean_tx_ring - Free any empty Tx buffers
57 * @tx_ring: ring to be cleaned
58 **/
59static void iavf_clean_tx_ring(struct iavf_ring *tx_ring)
60{
61 unsigned long bi_size;
62 u16 i;
63
64 /* ring already cleared, nothing to do */
65 if (!tx_ring->tx_bi)
66 return;
67
68 /* Free all the Tx ring sk_buffs */
69 for (i = 0; i < tx_ring->count; i++)
70 iavf_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
71
72 bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count;
73 memset(tx_ring->tx_bi, 0, bi_size);
74
75 /* Zero out the descriptor ring */
76 memset(tx_ring->desc, 0, tx_ring->size);
77
78 tx_ring->next_to_use = 0;
79 tx_ring->next_to_clean = 0;
80
81 if (!tx_ring->netdev)
82 return;
83
84 /* cleanup Tx queue statistics */
85 netdev_tx_reset_queue(txring_txq(tx_ring));
86}
87
88/**
89 * iavf_free_tx_resources - Free Tx resources per queue
90 * @tx_ring: Tx descriptor ring for a specific queue
91 *
92 * Free all transmit software resources
93 **/
94void iavf_free_tx_resources(struct iavf_ring *tx_ring)
95{
96 iavf_clean_tx_ring(tx_ring);
97 kfree(tx_ring->tx_bi);
98 tx_ring->tx_bi = NULL;
99
100 if (tx_ring->desc) {
101 dma_free_coherent(tx_ring->dev, tx_ring->size,
102 tx_ring->desc, tx_ring->dma);
103 tx_ring->desc = NULL;
104 }
105}
106
107/**
108 * iavf_get_tx_pending - how many Tx descriptors not processed
109 * @ring: the ring of descriptors
110 * @in_sw: is tx_pending being checked in SW or HW
111 *
112 * Since there is no access to the ring head register
113 * in XL710, we need to use our local copies
114 **/
115static u32 iavf_get_tx_pending(struct iavf_ring *ring, bool in_sw)
116{
117 u32 head, tail;
118
119 /* underlying hardware might not allow access and/or always return
120 * 0 for the head/tail registers so just use the cached values
121 */
122 head = ring->next_to_clean;
123 tail = ring->next_to_use;
124
125 if (head != tail)
126 return (head < tail) ?
127 tail - head : (tail + ring->count - head);
128
129 return 0;
130}
131
132/**
133 * iavf_force_wb - Issue SW Interrupt so HW does a wb
134 * @vsi: the VSI we care about
135 * @q_vector: the vector on which to force writeback
136 **/
137static void iavf_force_wb(struct iavf_vsi *vsi, struct iavf_q_vector *q_vector)
138{
139 u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
140 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
141 IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
142 IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
143 /* allow 00 to be written to the index */;
144
145 wr32(&vsi->back->hw,
146 IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx),
147 val);
148}
149
150/**
151 * iavf_detect_recover_hung - Function to detect and recover hung_queues
152 * @vsi: pointer to vsi struct with tx queues
153 *
154 * VSI has netdev and netdev has TX queues. This function is to check each of
155 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
156 **/
157void iavf_detect_recover_hung(struct iavf_vsi *vsi)
158{
159 struct iavf_ring *tx_ring = NULL;
160 struct net_device *netdev;
161 unsigned int i;
162 int packets;
163
164 if (!vsi)
165 return;
166
167 if (test_bit(__IAVF_VSI_DOWN, vsi->state))
168 return;
169
170 netdev = vsi->netdev;
171 if (!netdev)
172 return;
173
174 if (!netif_carrier_ok(netdev))
175 return;
176
177 for (i = 0; i < vsi->back->num_active_queues; i++) {
178 tx_ring = &vsi->back->tx_rings[i];
179 if (tx_ring && tx_ring->desc) {
180 /* If packet counter has not changed the queue is
181 * likely stalled, so force an interrupt for this
182 * queue.
183 *
184 * prev_pkt_ctr would be negative if there was no
185 * pending work.
186 */
187 packets = tx_ring->stats.packets & INT_MAX;
188 if (tx_ring->prev_pkt_ctr == packets) {
189 iavf_force_wb(vsi, tx_ring->q_vector);
190 continue;
191 }
192
193 /* Memory barrier between read of packet count and call
194 * to iavf_get_tx_pending()
195 */
196 smp_rmb();
197 tx_ring->prev_pkt_ctr =
198 iavf_get_tx_pending(tx_ring, true) ? packets : -1;
199 }
200 }
201}
202
203#define WB_STRIDE 4
204
205/**
206 * iavf_clean_tx_irq - Reclaim resources after transmit completes
207 * @vsi: the VSI we care about
208 * @tx_ring: Tx ring to clean
209 * @napi_budget: Used to determine if we are in netpoll
210 *
211 * Returns true if there's any budget left (e.g. the clean is finished)
212 **/
213static bool iavf_clean_tx_irq(struct iavf_vsi *vsi,
214 struct iavf_ring *tx_ring, int napi_budget)
215{
216 int i = tx_ring->next_to_clean;
217 struct iavf_tx_buffer *tx_buf;
218 struct iavf_tx_desc *tx_desc;
219 unsigned int total_bytes = 0, total_packets = 0;
220 unsigned int budget = IAVF_DEFAULT_IRQ_WORK;
221
222 tx_buf = &tx_ring->tx_bi[i];
223 tx_desc = IAVF_TX_DESC(tx_ring, i);
224 i -= tx_ring->count;
225
226 do {
227 struct iavf_tx_desc *eop_desc = tx_buf->next_to_watch;
228
229 /* if next_to_watch is not set then there is no work pending */
230 if (!eop_desc)
231 break;
232
233 /* prevent any other reads prior to eop_desc */
234 smp_rmb();
235
236 iavf_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
237 /* if the descriptor isn't done, no work yet to do */
238 if (!(eop_desc->cmd_type_offset_bsz &
239 cpu_to_le64(IAVF_TX_DESC_DTYPE_DESC_DONE)))
240 break;
241
242 /* clear next_to_watch to prevent false hangs */
243 tx_buf->next_to_watch = NULL;
244
245 /* update the statistics for this packet */
246 total_bytes += tx_buf->bytecount;
247 total_packets += tx_buf->gso_segs;
248
249 /* free the skb */
250 napi_consume_skb(tx_buf->skb, napi_budget);
251
252 /* unmap skb header data */
253 dma_unmap_single(tx_ring->dev,
254 dma_unmap_addr(tx_buf, dma),
255 dma_unmap_len(tx_buf, len),
256 DMA_TO_DEVICE);
257
258 /* clear tx_buffer data */
259 tx_buf->skb = NULL;
260 dma_unmap_len_set(tx_buf, len, 0);
261
262 /* unmap remaining buffers */
263 while (tx_desc != eop_desc) {
264 iavf_trace(clean_tx_irq_unmap,
265 tx_ring, tx_desc, tx_buf);
266
267 tx_buf++;
268 tx_desc++;
269 i++;
270 if (unlikely(!i)) {
271 i -= tx_ring->count;
272 tx_buf = tx_ring->tx_bi;
273 tx_desc = IAVF_TX_DESC(tx_ring, 0);
274 }
275
276 /* unmap any remaining paged data */
277 if (dma_unmap_len(tx_buf, len)) {
278 dma_unmap_page(tx_ring->dev,
279 dma_unmap_addr(tx_buf, dma),
280 dma_unmap_len(tx_buf, len),
281 DMA_TO_DEVICE);
282 dma_unmap_len_set(tx_buf, len, 0);
283 }
284 }
285
286 /* move us one more past the eop_desc for start of next pkt */
287 tx_buf++;
288 tx_desc++;
289 i++;
290 if (unlikely(!i)) {
291 i -= tx_ring->count;
292 tx_buf = tx_ring->tx_bi;
293 tx_desc = IAVF_TX_DESC(tx_ring, 0);
294 }
295
296 prefetch(tx_desc);
297
298 /* update budget accounting */
299 budget--;
300 } while (likely(budget));
301
302 i += tx_ring->count;
303 tx_ring->next_to_clean = i;
304 u64_stats_update_begin(&tx_ring->syncp);
305 tx_ring->stats.bytes += total_bytes;
306 tx_ring->stats.packets += total_packets;
307 u64_stats_update_end(&tx_ring->syncp);
308 tx_ring->q_vector->tx.total_bytes += total_bytes;
309 tx_ring->q_vector->tx.total_packets += total_packets;
310
311 if (tx_ring->flags & IAVF_TXR_FLAGS_WB_ON_ITR) {
312 /* check to see if there are < 4 descriptors
313 * waiting to be written back, then kick the hardware to force
314 * them to be written back in case we stay in NAPI.
315 * In this mode on X722 we do not enable Interrupt.
316 */
317 unsigned int j = iavf_get_tx_pending(tx_ring, false);
318
319 if (budget &&
320 ((j / WB_STRIDE) == 0) && (j > 0) &&
321 !test_bit(__IAVF_VSI_DOWN, vsi->state) &&
322 (IAVF_DESC_UNUSED(tx_ring) != tx_ring->count))
323 tx_ring->flags |= IAVF_TXR_FLAGS_ARM_WB;
324 }
325
326 /* notify netdev of completed buffers */
327 netdev_tx_completed_queue(txring_txq(tx_ring),
328 total_packets, total_bytes);
329
330#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
331 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
332 (IAVF_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
333 /* Make sure that anybody stopping the queue after this
334 * sees the new next_to_clean.
335 */
336 smp_mb();
337 if (__netif_subqueue_stopped(tx_ring->netdev,
338 tx_ring->queue_index) &&
339 !test_bit(__IAVF_VSI_DOWN, vsi->state)) {
340 netif_wake_subqueue(tx_ring->netdev,
341 tx_ring->queue_index);
342 ++tx_ring->tx_stats.restart_queue;
343 }
344 }
345
346 return !!budget;
347}
348
349/**
350 * iavf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
351 * @vsi: the VSI we care about
352 * @q_vector: the vector on which to enable writeback
353 *
354 **/
355static void iavf_enable_wb_on_itr(struct iavf_vsi *vsi,
356 struct iavf_q_vector *q_vector)
357{
358 u16 flags = q_vector->tx.ring[0].flags;
359 u32 val;
360
361 if (!(flags & IAVF_TXR_FLAGS_WB_ON_ITR))
362 return;
363
364 if (q_vector->arm_wb_state)
365 return;
366
367 val = IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
368 IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
369
370 wr32(&vsi->back->hw,
371 IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), val);
372 q_vector->arm_wb_state = true;
373}
374
375static bool iavf_container_is_rx(struct iavf_q_vector *q_vector,
376 struct iavf_ring_container *rc)
377{
378 return &q_vector->rx == rc;
379}
380
381#define IAVF_AIM_MULTIPLIER_100G 2560
382#define IAVF_AIM_MULTIPLIER_50G 1280
383#define IAVF_AIM_MULTIPLIER_40G 1024
384#define IAVF_AIM_MULTIPLIER_20G 512
385#define IAVF_AIM_MULTIPLIER_10G 256
386#define IAVF_AIM_MULTIPLIER_1G 32
387
388static unsigned int iavf_mbps_itr_multiplier(u32 speed_mbps)
389{
390 switch (speed_mbps) {
391 case SPEED_100000:
392 return IAVF_AIM_MULTIPLIER_100G;
393 case SPEED_50000:
394 return IAVF_AIM_MULTIPLIER_50G;
395 case SPEED_40000:
396 return IAVF_AIM_MULTIPLIER_40G;
397 case SPEED_25000:
398 case SPEED_20000:
399 return IAVF_AIM_MULTIPLIER_20G;
400 case SPEED_10000:
401 default:
402 return IAVF_AIM_MULTIPLIER_10G;
403 case SPEED_1000:
404 case SPEED_100:
405 return IAVF_AIM_MULTIPLIER_1G;
406 }
407}
408
409static unsigned int
410iavf_virtchnl_itr_multiplier(enum virtchnl_link_speed speed_virtchnl)
411{
412 switch (speed_virtchnl) {
413 case VIRTCHNL_LINK_SPEED_40GB:
414 return IAVF_AIM_MULTIPLIER_40G;
415 case VIRTCHNL_LINK_SPEED_25GB:
416 case VIRTCHNL_LINK_SPEED_20GB:
417 return IAVF_AIM_MULTIPLIER_20G;
418 case VIRTCHNL_LINK_SPEED_10GB:
419 default:
420 return IAVF_AIM_MULTIPLIER_10G;
421 case VIRTCHNL_LINK_SPEED_1GB:
422 case VIRTCHNL_LINK_SPEED_100MB:
423 return IAVF_AIM_MULTIPLIER_1G;
424 }
425}
426
427static unsigned int iavf_itr_divisor(struct iavf_adapter *adapter)
428{
429 if (ADV_LINK_SUPPORT(adapter))
430 return IAVF_ITR_ADAPTIVE_MIN_INC *
431 iavf_mbps_itr_multiplier(adapter->link_speed_mbps);
432 else
433 return IAVF_ITR_ADAPTIVE_MIN_INC *
434 iavf_virtchnl_itr_multiplier(adapter->link_speed);
435}
436
437/**
438 * iavf_update_itr - update the dynamic ITR value based on statistics
439 * @q_vector: structure containing interrupt and ring information
440 * @rc: structure containing ring performance data
441 *
442 * Stores a new ITR value based on packets and byte
443 * counts during the last interrupt. The advantage of per interrupt
444 * computation is faster updates and more accurate ITR for the current
445 * traffic pattern. Constants in this function were computed
446 * based on theoretical maximum wire speed and thresholds were set based
447 * on testing data as well as attempting to minimize response time
448 * while increasing bulk throughput.
449 **/
450static void iavf_update_itr(struct iavf_q_vector *q_vector,
451 struct iavf_ring_container *rc)
452{
453 unsigned int avg_wire_size, packets, bytes, itr;
454 unsigned long next_update = jiffies;
455
456 /* If we don't have any rings just leave ourselves set for maximum
457 * possible latency so we take ourselves out of the equation.
458 */
459 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
460 return;
461
462 /* For Rx we want to push the delay up and default to low latency.
463 * for Tx we want to pull the delay down and default to high latency.
464 */
465 itr = iavf_container_is_rx(q_vector, rc) ?
466 IAVF_ITR_ADAPTIVE_MIN_USECS | IAVF_ITR_ADAPTIVE_LATENCY :
467 IAVF_ITR_ADAPTIVE_MAX_USECS | IAVF_ITR_ADAPTIVE_LATENCY;
468
469 /* If we didn't update within up to 1 - 2 jiffies we can assume
470 * that either packets are coming in so slow there hasn't been
471 * any work, or that there is so much work that NAPI is dealing
472 * with interrupt moderation and we don't need to do anything.
473 */
474 if (time_after(next_update, rc->next_update))
475 goto clear_counts;
476
477 /* If itr_countdown is set it means we programmed an ITR within
478 * the last 4 interrupt cycles. This has a side effect of us
479 * potentially firing an early interrupt. In order to work around
480 * this we need to throw out any data received for a few
481 * interrupts following the update.
482 */
483 if (q_vector->itr_countdown) {
484 itr = rc->target_itr;
485 goto clear_counts;
486 }
487
488 packets = rc->total_packets;
489 bytes = rc->total_bytes;
490
491 if (iavf_container_is_rx(q_vector, rc)) {
492 /* If Rx there are 1 to 4 packets and bytes are less than
493 * 9000 assume insufficient data to use bulk rate limiting
494 * approach unless Tx is already in bulk rate limiting. We
495 * are likely latency driven.
496 */
497 if (packets && packets < 4 && bytes < 9000 &&
498 (q_vector->tx.target_itr & IAVF_ITR_ADAPTIVE_LATENCY)) {
499 itr = IAVF_ITR_ADAPTIVE_LATENCY;
500 goto adjust_by_size;
501 }
502 } else if (packets < 4) {
503 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
504 * bulk mode and we are receiving 4 or fewer packets just
505 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
506 * that the Rx can relax.
507 */
508 if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS &&
509 (q_vector->rx.target_itr & IAVF_ITR_MASK) ==
510 IAVF_ITR_ADAPTIVE_MAX_USECS)
511 goto clear_counts;
512 } else if (packets > 32) {
513 /* If we have processed over 32 packets in a single interrupt
514 * for Tx assume we need to switch over to "bulk" mode.
515 */
516 rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY;
517 }
518
519 /* We have no packets to actually measure against. This means
520 * either one of the other queues on this vector is active or
521 * we are a Tx queue doing TSO with too high of an interrupt rate.
522 *
523 * Between 4 and 56 we can assume that our current interrupt delay
524 * is only slightly too low. As such we should increase it by a small
525 * fixed amount.
526 */
527 if (packets < 56) {
528 itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC;
529 if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) {
530 itr &= IAVF_ITR_ADAPTIVE_LATENCY;
531 itr += IAVF_ITR_ADAPTIVE_MAX_USECS;
532 }
533 goto clear_counts;
534 }
535
536 if (packets <= 256) {
537 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
538 itr &= IAVF_ITR_MASK;
539
540 /* Between 56 and 112 is our "goldilocks" zone where we are
541 * working out "just right". Just report that our current
542 * ITR is good for us.
543 */
544 if (packets <= 112)
545 goto clear_counts;
546
547 /* If packet count is 128 or greater we are likely looking
548 * at a slight overrun of the delay we want. Try halving
549 * our delay to see if that will cut the number of packets
550 * in half per interrupt.
551 */
552 itr /= 2;
553 itr &= IAVF_ITR_MASK;
554 if (itr < IAVF_ITR_ADAPTIVE_MIN_USECS)
555 itr = IAVF_ITR_ADAPTIVE_MIN_USECS;
556
557 goto clear_counts;
558 }
559
560 /* The paths below assume we are dealing with a bulk ITR since
561 * number of packets is greater than 256. We are just going to have
562 * to compute a value and try to bring the count under control,
563 * though for smaller packet sizes there isn't much we can do as
564 * NAPI polling will likely be kicking in sooner rather than later.
565 */
566 itr = IAVF_ITR_ADAPTIVE_BULK;
567
568adjust_by_size:
569 /* If packet counts are 256 or greater we can assume we have a gross
570 * overestimation of what the rate should be. Instead of trying to fine
571 * tune it just use the formula below to try and dial in an exact value
572 * give the current packet size of the frame.
573 */
574 avg_wire_size = bytes / packets;
575
576 /* The following is a crude approximation of:
577 * wmem_default / (size + overhead) = desired_pkts_per_int
578 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
579 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
580 *
581 * Assuming wmem_default is 212992 and overhead is 640 bytes per
582 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
583 * formula down to
584 *
585 * (170 * (size + 24)) / (size + 640) = ITR
586 *
587 * We first do some math on the packet size and then finally bitshift
588 * by 8 after rounding up. We also have to account for PCIe link speed
589 * difference as ITR scales based on this.
590 */
591 if (avg_wire_size <= 60) {
592 /* Start at 250k ints/sec */
593 avg_wire_size = 4096;
594 } else if (avg_wire_size <= 380) {
595 /* 250K ints/sec to 60K ints/sec */
596 avg_wire_size *= 40;
597 avg_wire_size += 1696;
598 } else if (avg_wire_size <= 1084) {
599 /* 60K ints/sec to 36K ints/sec */
600 avg_wire_size *= 15;
601 avg_wire_size += 11452;
602 } else if (avg_wire_size <= 1980) {
603 /* 36K ints/sec to 30K ints/sec */
604 avg_wire_size *= 5;
605 avg_wire_size += 22420;
606 } else {
607 /* plateau at a limit of 30K ints/sec */
608 avg_wire_size = 32256;
609 }
610
611 /* If we are in low latency mode halve our delay which doubles the
612 * rate to somewhere between 100K to 16K ints/sec
613 */
614 if (itr & IAVF_ITR_ADAPTIVE_LATENCY)
615 avg_wire_size /= 2;
616
617 /* Resultant value is 256 times larger than it needs to be. This
618 * gives us room to adjust the value as needed to either increase
619 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
620 *
621 * Use addition as we have already recorded the new latency flag
622 * for the ITR value.
623 */
624 itr += DIV_ROUND_UP(avg_wire_size,
625 iavf_itr_divisor(q_vector->adapter)) *
626 IAVF_ITR_ADAPTIVE_MIN_INC;
627
628 if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) {
629 itr &= IAVF_ITR_ADAPTIVE_LATENCY;
630 itr += IAVF_ITR_ADAPTIVE_MAX_USECS;
631 }
632
633clear_counts:
634 /* write back value */
635 rc->target_itr = itr;
636
637 /* next update should occur within next jiffy */
638 rc->next_update = next_update + 1;
639
640 rc->total_bytes = 0;
641 rc->total_packets = 0;
642}
643
644/**
645 * iavf_setup_tx_descriptors - Allocate the Tx descriptors
646 * @tx_ring: the tx ring to set up
647 *
648 * Return 0 on success, negative on error
649 **/
650int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring)
651{
652 struct device *dev = tx_ring->dev;
653 int bi_size;
654
655 if (!dev)
656 return -ENOMEM;
657
658 /* warn if we are about to overwrite the pointer */
659 WARN_ON(tx_ring->tx_bi);
660 bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count;
661 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
662 if (!tx_ring->tx_bi)
663 goto err;
664
665 /* round up to nearest 4K */
666 tx_ring->size = tx_ring->count * sizeof(struct iavf_tx_desc);
667 tx_ring->size = ALIGN(tx_ring->size, 4096);
668 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
669 &tx_ring->dma, GFP_KERNEL);
670 if (!tx_ring->desc) {
671 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
672 tx_ring->size);
673 goto err;
674 }
675
676 tx_ring->next_to_use = 0;
677 tx_ring->next_to_clean = 0;
678 tx_ring->prev_pkt_ctr = -1;
679 return 0;
680
681err:
682 kfree(tx_ring->tx_bi);
683 tx_ring->tx_bi = NULL;
684 return -ENOMEM;
685}
686
687/**
688 * iavf_clean_rx_ring - Free Rx buffers
689 * @rx_ring: ring to be cleaned
690 **/
691static void iavf_clean_rx_ring(struct iavf_ring *rx_ring)
692{
693 /* ring already cleared, nothing to do */
694 if (!rx_ring->rx_fqes)
695 return;
696
697 if (rx_ring->skb) {
698 dev_kfree_skb(rx_ring->skb);
699 rx_ring->skb = NULL;
700 }
701
702 /* Free all the Rx ring buffers */
703 for (u32 i = rx_ring->next_to_clean; i != rx_ring->next_to_use; ) {
704 const struct libeth_fqe *rx_fqes = &rx_ring->rx_fqes[i];
705
706 page_pool_put_full_page(rx_ring->pp, rx_fqes->page, false);
707
708 if (unlikely(++i == rx_ring->count))
709 i = 0;
710 }
711
712 rx_ring->next_to_clean = 0;
713 rx_ring->next_to_use = 0;
714}
715
716/**
717 * iavf_free_rx_resources - Free Rx resources
718 * @rx_ring: ring to clean the resources from
719 *
720 * Free all receive software resources
721 **/
722void iavf_free_rx_resources(struct iavf_ring *rx_ring)
723{
724 struct libeth_fq fq = {
725 .fqes = rx_ring->rx_fqes,
726 .pp = rx_ring->pp,
727 };
728
729 iavf_clean_rx_ring(rx_ring);
730
731 if (rx_ring->desc) {
732 dma_free_coherent(rx_ring->pp->p.dev, rx_ring->size,
733 rx_ring->desc, rx_ring->dma);
734 rx_ring->desc = NULL;
735 }
736
737 libeth_rx_fq_destroy(&fq);
738 rx_ring->rx_fqes = NULL;
739 rx_ring->pp = NULL;
740}
741
742/**
743 * iavf_setup_rx_descriptors - Allocate Rx descriptors
744 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
745 *
746 * Returns 0 on success, negative on failure
747 **/
748int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring)
749{
750 struct libeth_fq fq = {
751 .count = rx_ring->count,
752 .buf_len = LIBIE_MAX_RX_BUF_LEN,
753 .nid = NUMA_NO_NODE,
754 };
755 int ret;
756
757 ret = libeth_rx_fq_create(&fq, &rx_ring->q_vector->napi);
758 if (ret)
759 return ret;
760
761 rx_ring->pp = fq.pp;
762 rx_ring->rx_fqes = fq.fqes;
763 rx_ring->truesize = fq.truesize;
764 rx_ring->rx_buf_len = fq.buf_len;
765
766 u64_stats_init(&rx_ring->syncp);
767
768 /* Round up to nearest 4K */
769 rx_ring->size = rx_ring->count * sizeof(union iavf_32byte_rx_desc);
770 rx_ring->size = ALIGN(rx_ring->size, 4096);
771 rx_ring->desc = dma_alloc_coherent(fq.pp->p.dev, rx_ring->size,
772 &rx_ring->dma, GFP_KERNEL);
773
774 if (!rx_ring->desc) {
775 dev_info(fq.pp->p.dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
776 rx_ring->size);
777 goto err;
778 }
779
780 rx_ring->next_to_clean = 0;
781 rx_ring->next_to_use = 0;
782
783 return 0;
784
785err:
786 libeth_rx_fq_destroy(&fq);
787 rx_ring->rx_fqes = NULL;
788 rx_ring->pp = NULL;
789
790 return -ENOMEM;
791}
792
793/**
794 * iavf_release_rx_desc - Store the new tail and head values
795 * @rx_ring: ring to bump
796 * @val: new head index
797 **/
798static void iavf_release_rx_desc(struct iavf_ring *rx_ring, u32 val)
799{
800 rx_ring->next_to_use = val;
801
802 /* Force memory writes to complete before letting h/w
803 * know there are new descriptors to fetch. (Only
804 * applicable for weak-ordered memory model archs,
805 * such as IA-64).
806 */
807 wmb();
808 writel(val, rx_ring->tail);
809}
810
811/**
812 * iavf_receive_skb - Send a completed packet up the stack
813 * @rx_ring: rx ring in play
814 * @skb: packet to send up
815 * @vlan_tag: vlan tag for packet
816 **/
817static void iavf_receive_skb(struct iavf_ring *rx_ring,
818 struct sk_buff *skb, u16 vlan_tag)
819{
820 struct iavf_q_vector *q_vector = rx_ring->q_vector;
821
822 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
823 (vlan_tag & VLAN_VID_MASK))
824 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
825 else if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_STAG_RX) &&
826 vlan_tag & VLAN_VID_MASK)
827 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan_tag);
828
829 napi_gro_receive(&q_vector->napi, skb);
830}
831
832/**
833 * iavf_alloc_rx_buffers - Replace used receive buffers
834 * @rx_ring: ring to place buffers on
835 * @cleaned_count: number of buffers to replace
836 *
837 * Returns false if all allocations were successful, true if any fail
838 **/
839bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
840{
841 const struct libeth_fq_fp fq = {
842 .pp = rx_ring->pp,
843 .fqes = rx_ring->rx_fqes,
844 .truesize = rx_ring->truesize,
845 .count = rx_ring->count,
846 };
847 u16 ntu = rx_ring->next_to_use;
848 union iavf_rx_desc *rx_desc;
849
850 /* do nothing if no valid netdev defined */
851 if (!rx_ring->netdev || !cleaned_count)
852 return false;
853
854 rx_desc = IAVF_RX_DESC(rx_ring, ntu);
855
856 do {
857 dma_addr_t addr;
858
859 addr = libeth_rx_alloc(&fq, ntu);
860 if (addr == DMA_MAPPING_ERROR)
861 goto no_buffers;
862
863 /* Refresh the desc even if buffer_addrs didn't change
864 * because each write-back erases this info.
865 */
866 rx_desc->read.pkt_addr = cpu_to_le64(addr);
867
868 rx_desc++;
869 ntu++;
870 if (unlikely(ntu == rx_ring->count)) {
871 rx_desc = IAVF_RX_DESC(rx_ring, 0);
872 ntu = 0;
873 }
874
875 /* clear the status bits for the next_to_use descriptor */
876 rx_desc->wb.qword1.status_error_len = 0;
877
878 cleaned_count--;
879 } while (cleaned_count);
880
881 if (rx_ring->next_to_use != ntu)
882 iavf_release_rx_desc(rx_ring, ntu);
883
884 return false;
885
886no_buffers:
887 if (rx_ring->next_to_use != ntu)
888 iavf_release_rx_desc(rx_ring, ntu);
889
890 rx_ring->rx_stats.alloc_page_failed++;
891
892 /* make sure to come back via polling to try again after
893 * allocation failure
894 */
895 return true;
896}
897
898/**
899 * iavf_rx_checksum - Indicate in skb if hw indicated a good cksum
900 * @vsi: the VSI we care about
901 * @skb: skb currently being received and modified
902 * @rx_desc: the receive descriptor
903 **/
904static void iavf_rx_checksum(struct iavf_vsi *vsi,
905 struct sk_buff *skb,
906 union iavf_rx_desc *rx_desc)
907{
908 struct libeth_rx_pt decoded;
909 u32 rx_error, rx_status;
910 bool ipv4, ipv6;
911 u8 ptype;
912 u64 qword;
913
914 skb->ip_summed = CHECKSUM_NONE;
915
916 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
917 ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword);
918
919 decoded = libie_rx_pt_parse(ptype);
920 if (!libeth_rx_pt_has_checksum(vsi->netdev, decoded))
921 return;
922
923 rx_error = FIELD_GET(IAVF_RXD_QW1_ERROR_MASK, qword);
924 rx_status = FIELD_GET(IAVF_RXD_QW1_STATUS_MASK, qword);
925
926 /* did the hardware decode the packet and checksum? */
927 if (!(rx_status & BIT(IAVF_RX_DESC_STATUS_L3L4P_SHIFT)))
928 return;
929
930 ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4;
931 ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6;
932
933 if (ipv4 &&
934 (rx_error & (BIT(IAVF_RX_DESC_ERROR_IPE_SHIFT) |
935 BIT(IAVF_RX_DESC_ERROR_EIPE_SHIFT))))
936 goto checksum_fail;
937
938 /* likely incorrect csum if alternate IP extension headers found */
939 if (ipv6 &&
940 rx_status & BIT(IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT))
941 /* don't increment checksum err here, non-fatal err */
942 return;
943
944 /* there was some L4 error, count error and punt packet to the stack */
945 if (rx_error & BIT(IAVF_RX_DESC_ERROR_L4E_SHIFT))
946 goto checksum_fail;
947
948 /* handle packets that were not able to be checksummed due
949 * to arrival speed, in this case the stack can compute
950 * the csum.
951 */
952 if (rx_error & BIT(IAVF_RX_DESC_ERROR_PPRS_SHIFT))
953 return;
954
955 skb->ip_summed = CHECKSUM_UNNECESSARY;
956 return;
957
958checksum_fail:
959 vsi->back->hw_csum_rx_error++;
960}
961
962/**
963 * iavf_rx_hash - set the hash value in the skb
964 * @ring: descriptor ring
965 * @rx_desc: specific descriptor
966 * @skb: skb currently being received and modified
967 * @rx_ptype: Rx packet type
968 **/
969static void iavf_rx_hash(struct iavf_ring *ring,
970 union iavf_rx_desc *rx_desc,
971 struct sk_buff *skb,
972 u8 rx_ptype)
973{
974 struct libeth_rx_pt decoded;
975 u32 hash;
976 const __le64 rss_mask =
977 cpu_to_le64((u64)IAVF_RX_DESC_FLTSTAT_RSS_HASH <<
978 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT);
979
980 decoded = libie_rx_pt_parse(rx_ptype);
981 if (!libeth_rx_pt_has_hash(ring->netdev, decoded))
982 return;
983
984 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
985 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
986 libeth_rx_pt_set_hash(skb, hash, decoded);
987 }
988}
989
990/**
991 * iavf_process_skb_fields - Populate skb header fields from Rx descriptor
992 * @rx_ring: rx descriptor ring packet is being transacted on
993 * @rx_desc: pointer to the EOP Rx descriptor
994 * @skb: pointer to current skb being populated
995 * @rx_ptype: the packet type decoded by hardware
996 *
997 * This function checks the ring, descriptor, and packet information in
998 * order to populate the hash, checksum, VLAN, protocol, and
999 * other fields within the skb.
1000 **/
1001static void
1002iavf_process_skb_fields(struct iavf_ring *rx_ring,
1003 union iavf_rx_desc *rx_desc, struct sk_buff *skb,
1004 u8 rx_ptype)
1005{
1006 iavf_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1007
1008 iavf_rx_checksum(rx_ring->vsi, skb, rx_desc);
1009
1010 skb_record_rx_queue(skb, rx_ring->queue_index);
1011
1012 /* modifies the skb - consumes the enet header */
1013 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1014}
1015
1016/**
1017 * iavf_cleanup_headers - Correct empty headers
1018 * @rx_ring: rx descriptor ring packet is being transacted on
1019 * @skb: pointer to current skb being fixed
1020 *
1021 * Also address the case where we are pulling data in on pages only
1022 * and as such no data is present in the skb header.
1023 *
1024 * In addition if skb is not at least 60 bytes we need to pad it so that
1025 * it is large enough to qualify as a valid Ethernet frame.
1026 *
1027 * Returns true if an error was encountered and skb was freed.
1028 **/
1029static bool iavf_cleanup_headers(struct iavf_ring *rx_ring, struct sk_buff *skb)
1030{
1031 /* if eth_skb_pad returns an error the skb was freed */
1032 if (eth_skb_pad(skb))
1033 return true;
1034
1035 return false;
1036}
1037
1038/**
1039 * iavf_add_rx_frag - Add contents of Rx buffer to sk_buff
1040 * @skb: sk_buff to place the data into
1041 * @rx_buffer: buffer containing page to add
1042 * @size: packet length from rx_desc
1043 *
1044 * This function will add the data contained in rx_buffer->page to the skb.
1045 * It will just attach the page as a frag to the skb.
1046 *
1047 * The function will then update the page offset.
1048 **/
1049static void iavf_add_rx_frag(struct sk_buff *skb,
1050 const struct libeth_fqe *rx_buffer,
1051 unsigned int size)
1052{
1053 u32 hr = rx_buffer->page->pp->p.offset;
1054
1055 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1056 rx_buffer->offset + hr, size, rx_buffer->truesize);
1057}
1058
1059/**
1060 * iavf_build_skb - Build skb around an existing buffer
1061 * @rx_buffer: Rx buffer to pull data from
1062 * @size: size of buffer to add to skb
1063 *
1064 * This function builds an skb around an existing Rx buffer, taking care
1065 * to set up the skb correctly and avoid any memcpy overhead.
1066 */
1067static struct sk_buff *iavf_build_skb(const struct libeth_fqe *rx_buffer,
1068 unsigned int size)
1069{
1070 u32 hr = rx_buffer->page->pp->p.offset;
1071 struct sk_buff *skb;
1072 void *va;
1073
1074 /* prefetch first cache line of first page */
1075 va = page_address(rx_buffer->page) + rx_buffer->offset;
1076 net_prefetch(va + hr);
1077
1078 /* build an skb around the page buffer */
1079 skb = napi_build_skb(va, rx_buffer->truesize);
1080 if (unlikely(!skb))
1081 return NULL;
1082
1083 skb_mark_for_recycle(skb);
1084
1085 /* update pointers within the skb to store the data */
1086 skb_reserve(skb, hr);
1087 __skb_put(skb, size);
1088
1089 return skb;
1090}
1091
1092/**
1093 * iavf_is_non_eop - process handling of non-EOP buffers
1094 * @rx_ring: Rx ring being processed
1095 * @rx_desc: Rx descriptor for current buffer
1096 * @skb: Current socket buffer containing buffer in progress
1097 *
1098 * This function updates next to clean. If the buffer is an EOP buffer
1099 * this function exits returning false, otherwise it will place the
1100 * sk_buff in the next buffer to be chained and return true indicating
1101 * that this is in fact a non-EOP buffer.
1102 **/
1103static bool iavf_is_non_eop(struct iavf_ring *rx_ring,
1104 union iavf_rx_desc *rx_desc,
1105 struct sk_buff *skb)
1106{
1107 u32 ntc = rx_ring->next_to_clean + 1;
1108
1109 /* fetch, update, and store next to clean */
1110 ntc = (ntc < rx_ring->count) ? ntc : 0;
1111 rx_ring->next_to_clean = ntc;
1112
1113 prefetch(IAVF_RX_DESC(rx_ring, ntc));
1114
1115 /* if we are the last buffer then there is nothing else to do */
1116#define IAVF_RXD_EOF BIT(IAVF_RX_DESC_STATUS_EOF_SHIFT)
1117 if (likely(iavf_test_staterr(rx_desc, IAVF_RXD_EOF)))
1118 return false;
1119
1120 rx_ring->rx_stats.non_eop_descs++;
1121
1122 return true;
1123}
1124
1125/**
1126 * iavf_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1127 * @rx_ring: rx descriptor ring to transact packets on
1128 * @budget: Total limit on number of packets to process
1129 *
1130 * This function provides a "bounce buffer" approach to Rx interrupt
1131 * processing. The advantage to this is that on systems that have
1132 * expensive overhead for IOMMU access this provides a means of avoiding
1133 * it by maintaining the mapping of the page to the system.
1134 *
1135 * Returns amount of work completed
1136 **/
1137static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)
1138{
1139 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1140 struct sk_buff *skb = rx_ring->skb;
1141 u16 cleaned_count = IAVF_DESC_UNUSED(rx_ring);
1142 bool failure = false;
1143
1144 while (likely(total_rx_packets < (unsigned int)budget)) {
1145 struct libeth_fqe *rx_buffer;
1146 union iavf_rx_desc *rx_desc;
1147 unsigned int size;
1148 u16 vlan_tag = 0;
1149 u8 rx_ptype;
1150 u64 qword;
1151
1152 /* return some buffers to hardware, one at a time is too slow */
1153 if (cleaned_count >= IAVF_RX_BUFFER_WRITE) {
1154 failure = failure ||
1155 iavf_alloc_rx_buffers(rx_ring, cleaned_count);
1156 cleaned_count = 0;
1157 }
1158
1159 rx_desc = IAVF_RX_DESC(rx_ring, rx_ring->next_to_clean);
1160
1161 /* status_error_len will always be zero for unused descriptors
1162 * because it's cleared in cleanup, and overlaps with hdr_addr
1163 * which is always zero because packet split isn't used, if the
1164 * hardware wrote DD then the length will be non-zero
1165 */
1166 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1167
1168 /* This memory barrier is needed to keep us from reading
1169 * any other fields out of the rx_desc until we have
1170 * verified the descriptor has been written back.
1171 */
1172 dma_rmb();
1173#define IAVF_RXD_DD BIT(IAVF_RX_DESC_STATUS_DD_SHIFT)
1174 if (!iavf_test_staterr(rx_desc, IAVF_RXD_DD))
1175 break;
1176
1177 size = FIELD_GET(IAVF_RXD_QW1_LENGTH_PBUF_MASK, qword);
1178
1179 iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb);
1180
1181 rx_buffer = &rx_ring->rx_fqes[rx_ring->next_to_clean];
1182 if (!libeth_rx_sync_for_cpu(rx_buffer, size))
1183 goto skip_data;
1184
1185 /* retrieve a buffer from the ring */
1186 if (skb)
1187 iavf_add_rx_frag(skb, rx_buffer, size);
1188 else
1189 skb = iavf_build_skb(rx_buffer, size);
1190
1191 /* exit if we failed to retrieve a buffer */
1192 if (!skb) {
1193 rx_ring->rx_stats.alloc_buff_failed++;
1194 break;
1195 }
1196
1197skip_data:
1198 cleaned_count++;
1199
1200 if (iavf_is_non_eop(rx_ring, rx_desc, skb) || unlikely(!skb))
1201 continue;
1202
1203 /* ERR_MASK will only have valid bits if EOP set, and
1204 * what we are doing here is actually checking
1205 * IAVF_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1206 * the error field
1207 */
1208 if (unlikely(iavf_test_staterr(rx_desc, BIT(IAVF_RXD_QW1_ERROR_SHIFT)))) {
1209 dev_kfree_skb_any(skb);
1210 skb = NULL;
1211 continue;
1212 }
1213
1214 if (iavf_cleanup_headers(rx_ring, skb)) {
1215 skb = NULL;
1216 continue;
1217 }
1218
1219 /* probably a little skewed due to removing CRC */
1220 total_rx_bytes += skb->len;
1221
1222 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1223 rx_ptype = FIELD_GET(IAVF_RXD_QW1_PTYPE_MASK, qword);
1224
1225 /* populate checksum, VLAN, and protocol */
1226 iavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1227
1228 if (qword & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT) &&
1229 rx_ring->flags & IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1)
1230 vlan_tag = le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1);
1231 if (rx_desc->wb.qword2.ext_status &
1232 cpu_to_le16(BIT(IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) &&
1233 rx_ring->flags & IAVF_RXR_FLAGS_VLAN_TAG_LOC_L2TAG2_2)
1234 vlan_tag = le16_to_cpu(rx_desc->wb.qword2.l2tag2_2);
1235
1236 iavf_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
1237 iavf_receive_skb(rx_ring, skb, vlan_tag);
1238 skb = NULL;
1239
1240 /* update budget accounting */
1241 total_rx_packets++;
1242 }
1243
1244 rx_ring->skb = skb;
1245
1246 u64_stats_update_begin(&rx_ring->syncp);
1247 rx_ring->stats.packets += total_rx_packets;
1248 rx_ring->stats.bytes += total_rx_bytes;
1249 u64_stats_update_end(&rx_ring->syncp);
1250 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1251 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1252
1253 /* guarantee a trip back through this routine if there was a failure */
1254 return failure ? budget : (int)total_rx_packets;
1255}
1256
1257static inline u32 iavf_buildreg_itr(const int type, u16 itr)
1258{
1259 u32 val;
1260
1261 /* We don't bother with setting the CLEARPBA bit as the data sheet
1262 * points out doing so is "meaningless since it was already
1263 * auto-cleared". The auto-clearing happens when the interrupt is
1264 * asserted.
1265 *
1266 * Hardware errata 28 for also indicates that writing to a
1267 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
1268 * an event in the PBA anyway so we need to rely on the automask
1269 * to hold pending events for us until the interrupt is re-enabled
1270 *
1271 * The itr value is reported in microseconds, and the register
1272 * value is recorded in 2 microsecond units. For this reason we
1273 * only need to shift by the interval shift - 1 instead of the
1274 * full value.
1275 */
1276 itr &= IAVF_ITR_MASK;
1277
1278 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
1279 (type << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1280 (itr << (IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));
1281
1282 return val;
1283}
1284
1285/* a small macro to shorten up some long lines */
1286#define INTREG IAVF_VFINT_DYN_CTLN1
1287
1288/* The act of updating the ITR will cause it to immediately trigger. In order
1289 * to prevent this from throwing off adaptive update statistics we defer the
1290 * update so that it can only happen so often. So after either Tx or Rx are
1291 * updated we make the adaptive scheme wait until either the ITR completely
1292 * expires via the next_update expiration or we have been through at least
1293 * 3 interrupts.
1294 */
1295#define ITR_COUNTDOWN_START 3
1296
1297/**
1298 * iavf_update_enable_itr - Update itr and re-enable MSIX interrupt
1299 * @vsi: the VSI we care about
1300 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1301 *
1302 **/
1303static void iavf_update_enable_itr(struct iavf_vsi *vsi,
1304 struct iavf_q_vector *q_vector)
1305{
1306 struct iavf_hw *hw = &vsi->back->hw;
1307 u32 intval;
1308
1309 /* These will do nothing if dynamic updates are not enabled */
1310 iavf_update_itr(q_vector, &q_vector->tx);
1311 iavf_update_itr(q_vector, &q_vector->rx);
1312
1313 /* This block of logic allows us to get away with only updating
1314 * one ITR value with each interrupt. The idea is to perform a
1315 * pseudo-lazy update with the following criteria.
1316 *
1317 * 1. Rx is given higher priority than Tx if both are in same state
1318 * 2. If we must reduce an ITR that is given highest priority.
1319 * 3. We then give priority to increasing ITR based on amount.
1320 */
1321 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
1322 /* Rx ITR needs to be reduced, this is highest priority */
1323 intval = iavf_buildreg_itr(IAVF_RX_ITR,
1324 q_vector->rx.target_itr);
1325 q_vector->rx.current_itr = q_vector->rx.target_itr;
1326 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1327 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
1328 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
1329 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
1330 /* Tx ITR needs to be reduced, this is second priority
1331 * Tx ITR needs to be increased more than Rx, fourth priority
1332 */
1333 intval = iavf_buildreg_itr(IAVF_TX_ITR,
1334 q_vector->tx.target_itr);
1335 q_vector->tx.current_itr = q_vector->tx.target_itr;
1336 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1337 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
1338 /* Rx ITR needs to be increased, third priority */
1339 intval = iavf_buildreg_itr(IAVF_RX_ITR,
1340 q_vector->rx.target_itr);
1341 q_vector->rx.current_itr = q_vector->rx.target_itr;
1342 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1343 } else {
1344 /* No ITR update, lowest priority */
1345 intval = iavf_buildreg_itr(IAVF_ITR_NONE, 0);
1346 if (q_vector->itr_countdown)
1347 q_vector->itr_countdown--;
1348 }
1349
1350 if (!test_bit(__IAVF_VSI_DOWN, vsi->state))
1351 wr32(hw, INTREG(q_vector->reg_idx), intval);
1352}
1353
1354/**
1355 * iavf_napi_poll - NAPI polling Rx/Tx cleanup routine
1356 * @napi: napi struct with our devices info in it
1357 * @budget: amount of work driver is allowed to do this pass, in packets
1358 *
1359 * This function will clean all queues associated with a q_vector.
1360 *
1361 * Returns the amount of work done
1362 **/
1363int iavf_napi_poll(struct napi_struct *napi, int budget)
1364{
1365 struct iavf_q_vector *q_vector =
1366 container_of(napi, struct iavf_q_vector, napi);
1367 struct iavf_vsi *vsi = q_vector->vsi;
1368 struct iavf_ring *ring;
1369 bool clean_complete = true;
1370 bool arm_wb = false;
1371 int budget_per_ring;
1372 int work_done = 0;
1373
1374 if (test_bit(__IAVF_VSI_DOWN, vsi->state)) {
1375 napi_complete(napi);
1376 return 0;
1377 }
1378
1379 /* Since the actual Tx work is minimal, we can give the Tx a larger
1380 * budget and be more aggressive about cleaning up the Tx descriptors.
1381 */
1382 iavf_for_each_ring(ring, q_vector->tx) {
1383 if (!iavf_clean_tx_irq(vsi, ring, budget)) {
1384 clean_complete = false;
1385 continue;
1386 }
1387 arm_wb |= !!(ring->flags & IAVF_TXR_FLAGS_ARM_WB);
1388 ring->flags &= ~IAVF_TXR_FLAGS_ARM_WB;
1389 }
1390
1391 /* Handle case where we are called by netpoll with a budget of 0 */
1392 if (budget <= 0)
1393 goto tx_only;
1394
1395 /* We attempt to distribute budget to each Rx queue fairly, but don't
1396 * allow the budget to go below 1 because that would exit polling early.
1397 */
1398 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1399
1400 iavf_for_each_ring(ring, q_vector->rx) {
1401 int cleaned = iavf_clean_rx_irq(ring, budget_per_ring);
1402
1403 work_done += cleaned;
1404 /* if we clean as many as budgeted, we must not be done */
1405 if (cleaned >= budget_per_ring)
1406 clean_complete = false;
1407 }
1408
1409 /* If work not completed, return budget and polling will return */
1410 if (!clean_complete) {
1411 int cpu_id = smp_processor_id();
1412
1413 /* It is possible that the interrupt affinity has changed but,
1414 * if the cpu is pegged at 100%, polling will never exit while
1415 * traffic continues and the interrupt will be stuck on this
1416 * cpu. We check to make sure affinity is correct before we
1417 * continue to poll, otherwise we must stop polling so the
1418 * interrupt can move to the correct cpu.
1419 */
1420 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
1421 /* Tell napi that we are done polling */
1422 napi_complete_done(napi, work_done);
1423
1424 /* Force an interrupt */
1425 iavf_force_wb(vsi, q_vector);
1426
1427 /* Return budget-1 so that polling stops */
1428 return budget - 1;
1429 }
1430tx_only:
1431 if (arm_wb) {
1432 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1433 iavf_enable_wb_on_itr(vsi, q_vector);
1434 }
1435 return budget;
1436 }
1437
1438 if (vsi->back->flags & IAVF_TXR_FLAGS_WB_ON_ITR)
1439 q_vector->arm_wb_state = false;
1440
1441 /* Exit the polling mode, but don't re-enable interrupts if stack might
1442 * poll us due to busy-polling
1443 */
1444 if (likely(napi_complete_done(napi, work_done)))
1445 iavf_update_enable_itr(vsi, q_vector);
1446
1447 return min_t(int, work_done, budget - 1);
1448}
1449
1450/**
1451 * iavf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1452 * @skb: send buffer
1453 * @tx_ring: ring to send buffer on
1454 * @flags: the tx flags to be set
1455 *
1456 * Checks the skb and set up correspondingly several generic transmit flags
1457 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1458 *
1459 * Returns error code indicate the frame should be dropped upon error and the
1460 * otherwise returns 0 to indicate the flags has been set properly.
1461 **/
1462static void iavf_tx_prepare_vlan_flags(struct sk_buff *skb,
1463 struct iavf_ring *tx_ring, u32 *flags)
1464{
1465 u32 tx_flags = 0;
1466
1467
1468 /* stack will only request hardware VLAN insertion offload for protocols
1469 * that the driver supports and has enabled
1470 */
1471 if (!skb_vlan_tag_present(skb))
1472 return;
1473
1474 tx_flags |= skb_vlan_tag_get(skb) << IAVF_TX_FLAGS_VLAN_SHIFT;
1475 if (tx_ring->flags & IAVF_TXR_FLAGS_VLAN_TAG_LOC_L2TAG2) {
1476 tx_flags |= IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN;
1477 } else if (tx_ring->flags & IAVF_TXRX_FLAGS_VLAN_TAG_LOC_L2TAG1) {
1478 tx_flags |= IAVF_TX_FLAGS_HW_VLAN;
1479 } else {
1480 dev_dbg(tx_ring->dev, "Unsupported Tx VLAN tag location requested\n");
1481 return;
1482 }
1483
1484 *flags = tx_flags;
1485}
1486
1487/**
1488 * iavf_tso - set up the tso context descriptor
1489 * @first: pointer to first Tx buffer for xmit
1490 * @hdr_len: ptr to the size of the packet header
1491 * @cd_type_cmd_tso_mss: Quad Word 1
1492 *
1493 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1494 **/
1495static int iavf_tso(struct iavf_tx_buffer *first, u8 *hdr_len,
1496 u64 *cd_type_cmd_tso_mss)
1497{
1498 struct sk_buff *skb = first->skb;
1499 u64 cd_cmd, cd_tso_len, cd_mss;
1500 union {
1501 struct iphdr *v4;
1502 struct ipv6hdr *v6;
1503 unsigned char *hdr;
1504 } ip;
1505 union {
1506 struct tcphdr *tcp;
1507 struct udphdr *udp;
1508 unsigned char *hdr;
1509 } l4;
1510 u32 paylen, l4_offset;
1511 u16 gso_segs, gso_size;
1512 int err;
1513
1514 if (skb->ip_summed != CHECKSUM_PARTIAL)
1515 return 0;
1516
1517 if (!skb_is_gso(skb))
1518 return 0;
1519
1520 err = skb_cow_head(skb, 0);
1521 if (err < 0)
1522 return err;
1523
1524 ip.hdr = skb_network_header(skb);
1525 l4.hdr = skb_transport_header(skb);
1526
1527 /* initialize outer IP header fields */
1528 if (ip.v4->version == 4) {
1529 ip.v4->tot_len = 0;
1530 ip.v4->check = 0;
1531 } else {
1532 ip.v6->payload_len = 0;
1533 }
1534
1535 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1536 SKB_GSO_GRE_CSUM |
1537 SKB_GSO_IPXIP4 |
1538 SKB_GSO_IPXIP6 |
1539 SKB_GSO_UDP_TUNNEL |
1540 SKB_GSO_UDP_TUNNEL_CSUM)) {
1541 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1542 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
1543 l4.udp->len = 0;
1544
1545 /* determine offset of outer transport header */
1546 l4_offset = l4.hdr - skb->data;
1547
1548 /* remove payload length from outer checksum */
1549 paylen = skb->len - l4_offset;
1550 csum_replace_by_diff(&l4.udp->check,
1551 (__force __wsum)htonl(paylen));
1552 }
1553
1554 /* reset pointers to inner headers */
1555 ip.hdr = skb_inner_network_header(skb);
1556 l4.hdr = skb_inner_transport_header(skb);
1557
1558 /* initialize inner IP header fields */
1559 if (ip.v4->version == 4) {
1560 ip.v4->tot_len = 0;
1561 ip.v4->check = 0;
1562 } else {
1563 ip.v6->payload_len = 0;
1564 }
1565 }
1566
1567 /* determine offset of inner transport header */
1568 l4_offset = l4.hdr - skb->data;
1569 /* remove payload length from inner checksum */
1570 paylen = skb->len - l4_offset;
1571
1572 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1573 csum_replace_by_diff(&l4.udp->check,
1574 (__force __wsum)htonl(paylen));
1575 /* compute length of UDP segmentation header */
1576 *hdr_len = (u8)sizeof(l4.udp) + l4_offset;
1577 } else {
1578 csum_replace_by_diff(&l4.tcp->check,
1579 (__force __wsum)htonl(paylen));
1580 /* compute length of TCP segmentation header */
1581 *hdr_len = (u8)((l4.tcp->doff * 4) + l4_offset);
1582 }
1583
1584 /* pull values out of skb_shinfo */
1585 gso_size = skb_shinfo(skb)->gso_size;
1586 gso_segs = skb_shinfo(skb)->gso_segs;
1587
1588 /* update GSO size and bytecount with header size */
1589 first->gso_segs = gso_segs;
1590 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1591
1592 /* find the field values */
1593 cd_cmd = IAVF_TX_CTX_DESC_TSO;
1594 cd_tso_len = skb->len - *hdr_len;
1595 cd_mss = gso_size;
1596 *cd_type_cmd_tso_mss |= (cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1597 (cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1598 (cd_mss << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1599 return 1;
1600}
1601
1602/**
1603 * iavf_tx_enable_csum - Enable Tx checksum offloads
1604 * @skb: send buffer
1605 * @tx_flags: pointer to Tx flags currently set
1606 * @td_cmd: Tx descriptor command bits to set
1607 * @td_offset: Tx descriptor header offsets to set
1608 * @tx_ring: Tx descriptor ring
1609 * @cd_tunneling: ptr to context desc bits
1610 **/
1611static int iavf_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1612 u32 *td_cmd, u32 *td_offset,
1613 struct iavf_ring *tx_ring,
1614 u32 *cd_tunneling)
1615{
1616 union {
1617 struct iphdr *v4;
1618 struct ipv6hdr *v6;
1619 unsigned char *hdr;
1620 } ip;
1621 union {
1622 struct tcphdr *tcp;
1623 struct udphdr *udp;
1624 unsigned char *hdr;
1625 } l4;
1626 unsigned char *exthdr;
1627 u32 offset, cmd = 0;
1628 __be16 frag_off;
1629 u8 l4_proto = 0;
1630
1631 if (skb->ip_summed != CHECKSUM_PARTIAL)
1632 return 0;
1633
1634 ip.hdr = skb_network_header(skb);
1635 l4.hdr = skb_transport_header(skb);
1636
1637 /* compute outer L2 header size */
1638 offset = ((ip.hdr - skb->data) / 2) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1639
1640 if (skb->encapsulation) {
1641 u32 tunnel = 0;
1642 /* define outer network header type */
1643 if (*tx_flags & IAVF_TX_FLAGS_IPV4) {
1644 tunnel |= (*tx_flags & IAVF_TX_FLAGS_TSO) ?
1645 IAVF_TX_CTX_EXT_IP_IPV4 :
1646 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1647
1648 l4_proto = ip.v4->protocol;
1649 } else if (*tx_flags & IAVF_TX_FLAGS_IPV6) {
1650 tunnel |= IAVF_TX_CTX_EXT_IP_IPV6;
1651
1652 exthdr = ip.hdr + sizeof(*ip.v6);
1653 l4_proto = ip.v6->nexthdr;
1654 if (l4.hdr != exthdr)
1655 ipv6_skip_exthdr(skb, exthdr - skb->data,
1656 &l4_proto, &frag_off);
1657 }
1658
1659 /* define outer transport */
1660 switch (l4_proto) {
1661 case IPPROTO_UDP:
1662 tunnel |= IAVF_TXD_CTX_UDP_TUNNELING;
1663 *tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
1664 break;
1665 case IPPROTO_GRE:
1666 tunnel |= IAVF_TXD_CTX_GRE_TUNNELING;
1667 *tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
1668 break;
1669 case IPPROTO_IPIP:
1670 case IPPROTO_IPV6:
1671 *tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
1672 l4.hdr = skb_inner_network_header(skb);
1673 break;
1674 default:
1675 if (*tx_flags & IAVF_TX_FLAGS_TSO)
1676 return -1;
1677
1678 skb_checksum_help(skb);
1679 return 0;
1680 }
1681
1682 /* compute outer L3 header size */
1683 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1684 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1685
1686 /* switch IP header pointer from outer to inner header */
1687 ip.hdr = skb_inner_network_header(skb);
1688
1689 /* compute tunnel header size */
1690 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1691 IAVF_TXD_CTX_QW0_NATLEN_SHIFT;
1692
1693 /* indicate if we need to offload outer UDP header */
1694 if ((*tx_flags & IAVF_TX_FLAGS_TSO) &&
1695 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1696 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1697 tunnel |= IAVF_TXD_CTX_QW0_L4T_CS_MASK;
1698
1699 /* record tunnel offload values */
1700 *cd_tunneling |= tunnel;
1701
1702 /* switch L4 header pointer from outer to inner */
1703 l4.hdr = skb_inner_transport_header(skb);
1704 l4_proto = 0;
1705
1706 /* reset type as we transition from outer to inner headers */
1707 *tx_flags &= ~(IAVF_TX_FLAGS_IPV4 | IAVF_TX_FLAGS_IPV6);
1708 if (ip.v4->version == 4)
1709 *tx_flags |= IAVF_TX_FLAGS_IPV4;
1710 if (ip.v6->version == 6)
1711 *tx_flags |= IAVF_TX_FLAGS_IPV6;
1712 }
1713
1714 /* Enable IP checksum offloads */
1715 if (*tx_flags & IAVF_TX_FLAGS_IPV4) {
1716 l4_proto = ip.v4->protocol;
1717 /* the stack computes the IP header already, the only time we
1718 * need the hardware to recompute it is in the case of TSO.
1719 */
1720 cmd |= (*tx_flags & IAVF_TX_FLAGS_TSO) ?
1721 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM :
1722 IAVF_TX_DESC_CMD_IIPT_IPV4;
1723 } else if (*tx_flags & IAVF_TX_FLAGS_IPV6) {
1724 cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1725
1726 exthdr = ip.hdr + sizeof(*ip.v6);
1727 l4_proto = ip.v6->nexthdr;
1728 if (l4.hdr != exthdr)
1729 ipv6_skip_exthdr(skb, exthdr - skb->data,
1730 &l4_proto, &frag_off);
1731 }
1732
1733 /* compute inner L3 header size */
1734 offset |= ((l4.hdr - ip.hdr) / 4) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1735
1736 /* Enable L4 checksum offloads */
1737 switch (l4_proto) {
1738 case IPPROTO_TCP:
1739 /* enable checksum offloads */
1740 cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1741 offset |= l4.tcp->doff << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1742 break;
1743 case IPPROTO_SCTP:
1744 /* enable SCTP checksum offload */
1745 cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1746 offset |= (sizeof(struct sctphdr) >> 2) <<
1747 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1748 break;
1749 case IPPROTO_UDP:
1750 /* enable UDP checksum offload */
1751 cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1752 offset |= (sizeof(struct udphdr) >> 2) <<
1753 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1754 break;
1755 default:
1756 if (*tx_flags & IAVF_TX_FLAGS_TSO)
1757 return -1;
1758 skb_checksum_help(skb);
1759 return 0;
1760 }
1761
1762 *td_cmd |= cmd;
1763 *td_offset |= offset;
1764
1765 return 1;
1766}
1767
1768/**
1769 * iavf_create_tx_ctx - Build the Tx context descriptor
1770 * @tx_ring: ring to create the descriptor on
1771 * @cd_type_cmd_tso_mss: Quad Word 1
1772 * @cd_tunneling: Quad Word 0 - bits 0-31
1773 * @cd_l2tag2: Quad Word 0 - bits 32-63
1774 **/
1775static void iavf_create_tx_ctx(struct iavf_ring *tx_ring,
1776 const u64 cd_type_cmd_tso_mss,
1777 const u32 cd_tunneling, const u32 cd_l2tag2)
1778{
1779 struct iavf_tx_context_desc *context_desc;
1780 int i = tx_ring->next_to_use;
1781
1782 if ((cd_type_cmd_tso_mss == IAVF_TX_DESC_DTYPE_CONTEXT) &&
1783 !cd_tunneling && !cd_l2tag2)
1784 return;
1785
1786 /* grab the next descriptor */
1787 context_desc = IAVF_TX_CTXTDESC(tx_ring, i);
1788
1789 i++;
1790 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1791
1792 /* cpu_to_le32 and assign to struct fields */
1793 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1794 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1795 context_desc->rsvd = cpu_to_le16(0);
1796 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1797}
1798
1799/**
1800 * __iavf_chk_linearize - Check if there are more than 8 buffers per packet
1801 * @skb: send buffer
1802 *
1803 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1804 * and so we need to figure out the cases where we need to linearize the skb.
1805 *
1806 * For TSO we need to count the TSO header and segment payload separately.
1807 * As such we need to check cases where we have 7 fragments or more as we
1808 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1809 * the segment payload in the first descriptor, and another 7 for the
1810 * fragments.
1811 **/
1812bool __iavf_chk_linearize(struct sk_buff *skb)
1813{
1814 const skb_frag_t *frag, *stale;
1815 int nr_frags, sum;
1816
1817 /* no need to check if number of frags is less than 7 */
1818 nr_frags = skb_shinfo(skb)->nr_frags;
1819 if (nr_frags < (IAVF_MAX_BUFFER_TXD - 1))
1820 return false;
1821
1822 /* We need to walk through the list and validate that each group
1823 * of 6 fragments totals at least gso_size.
1824 */
1825 nr_frags -= IAVF_MAX_BUFFER_TXD - 2;
1826 frag = &skb_shinfo(skb)->frags[0];
1827
1828 /* Initialize size to the negative value of gso_size minus 1. We
1829 * use this as the worst case scenerio in which the frag ahead
1830 * of us only provides one byte which is why we are limited to 6
1831 * descriptors for a single transmit as the header and previous
1832 * fragment are already consuming 2 descriptors.
1833 */
1834 sum = 1 - skb_shinfo(skb)->gso_size;
1835
1836 /* Add size of frags 0 through 4 to create our initial sum */
1837 sum += skb_frag_size(frag++);
1838 sum += skb_frag_size(frag++);
1839 sum += skb_frag_size(frag++);
1840 sum += skb_frag_size(frag++);
1841 sum += skb_frag_size(frag++);
1842
1843 /* Walk through fragments adding latest fragment, testing it, and
1844 * then removing stale fragments from the sum.
1845 */
1846 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
1847 int stale_size = skb_frag_size(stale);
1848
1849 sum += skb_frag_size(frag++);
1850
1851 /* The stale fragment may present us with a smaller
1852 * descriptor than the actual fragment size. To account
1853 * for that we need to remove all the data on the front and
1854 * figure out what the remainder would be in the last
1855 * descriptor associated with the fragment.
1856 */
1857 if (stale_size > IAVF_MAX_DATA_PER_TXD) {
1858 int align_pad = -(skb_frag_off(stale)) &
1859 (IAVF_MAX_READ_REQ_SIZE - 1);
1860
1861 sum -= align_pad;
1862 stale_size -= align_pad;
1863
1864 do {
1865 sum -= IAVF_MAX_DATA_PER_TXD_ALIGNED;
1866 stale_size -= IAVF_MAX_DATA_PER_TXD_ALIGNED;
1867 } while (stale_size > IAVF_MAX_DATA_PER_TXD);
1868 }
1869
1870 /* if sum is negative we failed to make sufficient progress */
1871 if (sum < 0)
1872 return true;
1873
1874 if (!nr_frags--)
1875 break;
1876
1877 sum -= stale_size;
1878 }
1879
1880 return false;
1881}
1882
1883/**
1884 * __iavf_maybe_stop_tx - 2nd level check for tx stop conditions
1885 * @tx_ring: the ring to be checked
1886 * @size: the size buffer we want to assure is available
1887 *
1888 * Returns -EBUSY if a stop is needed, else 0
1889 **/
1890int __iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size)
1891{
1892 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1893 /* Memory barrier before checking head and tail */
1894 smp_mb();
1895
1896 /* Check again in a case another CPU has just made room available. */
1897 if (likely(IAVF_DESC_UNUSED(tx_ring) < size))
1898 return -EBUSY;
1899
1900 /* A reprieve! - use start_queue because it doesn't call schedule */
1901 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1902 ++tx_ring->tx_stats.restart_queue;
1903 return 0;
1904}
1905
1906/**
1907 * iavf_tx_map - Build the Tx descriptor
1908 * @tx_ring: ring to send buffer on
1909 * @skb: send buffer
1910 * @first: first buffer info buffer to use
1911 * @tx_flags: collected send information
1912 * @hdr_len: size of the packet header
1913 * @td_cmd: the command field in the descriptor
1914 * @td_offset: offset for checksum or crc
1915 **/
1916static void iavf_tx_map(struct iavf_ring *tx_ring, struct sk_buff *skb,
1917 struct iavf_tx_buffer *first, u32 tx_flags,
1918 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1919{
1920 unsigned int data_len = skb->data_len;
1921 unsigned int size = skb_headlen(skb);
1922 skb_frag_t *frag;
1923 struct iavf_tx_buffer *tx_bi;
1924 struct iavf_tx_desc *tx_desc;
1925 u16 i = tx_ring->next_to_use;
1926 u32 td_tag = 0;
1927 dma_addr_t dma;
1928
1929 if (tx_flags & IAVF_TX_FLAGS_HW_VLAN) {
1930 td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
1931 td_tag = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags);
1932 }
1933
1934 first->tx_flags = tx_flags;
1935
1936 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1937
1938 tx_desc = IAVF_TX_DESC(tx_ring, i);
1939 tx_bi = first;
1940
1941 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1942 unsigned int max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED;
1943
1944 if (dma_mapping_error(tx_ring->dev, dma))
1945 goto dma_error;
1946
1947 /* record length, and DMA address */
1948 dma_unmap_len_set(tx_bi, len, size);
1949 dma_unmap_addr_set(tx_bi, dma, dma);
1950
1951 /* align size to end of page */
1952 max_data += -dma & (IAVF_MAX_READ_REQ_SIZE - 1);
1953 tx_desc->buffer_addr = cpu_to_le64(dma);
1954
1955 while (unlikely(size > IAVF_MAX_DATA_PER_TXD)) {
1956 tx_desc->cmd_type_offset_bsz =
1957 build_ctob(td_cmd, td_offset,
1958 max_data, td_tag);
1959
1960 tx_desc++;
1961 i++;
1962
1963 if (i == tx_ring->count) {
1964 tx_desc = IAVF_TX_DESC(tx_ring, 0);
1965 i = 0;
1966 }
1967
1968 dma += max_data;
1969 size -= max_data;
1970
1971 max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED;
1972 tx_desc->buffer_addr = cpu_to_le64(dma);
1973 }
1974
1975 if (likely(!data_len))
1976 break;
1977
1978 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1979 size, td_tag);
1980
1981 tx_desc++;
1982 i++;
1983
1984 if (i == tx_ring->count) {
1985 tx_desc = IAVF_TX_DESC(tx_ring, 0);
1986 i = 0;
1987 }
1988
1989 size = skb_frag_size(frag);
1990 data_len -= size;
1991
1992 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1993 DMA_TO_DEVICE);
1994
1995 tx_bi = &tx_ring->tx_bi[i];
1996 }
1997
1998 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1999
2000 i++;
2001 if (i == tx_ring->count)
2002 i = 0;
2003
2004 tx_ring->next_to_use = i;
2005
2006 iavf_maybe_stop_tx(tx_ring, DESC_NEEDED);
2007
2008 /* write last descriptor with RS and EOP bits */
2009 td_cmd |= IAVF_TXD_CMD;
2010 tx_desc->cmd_type_offset_bsz =
2011 build_ctob(td_cmd, td_offset, size, td_tag);
2012
2013 skb_tx_timestamp(skb);
2014
2015 /* Force memory writes to complete before letting h/w know there
2016 * are new descriptors to fetch.
2017 *
2018 * We also use this memory barrier to make certain all of the
2019 * status bits have been updated before next_to_watch is written.
2020 */
2021 wmb();
2022
2023 /* set next_to_watch value indicating a packet is present */
2024 first->next_to_watch = tx_desc;
2025
2026 /* notify HW of packet */
2027 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
2028 writel(i, tx_ring->tail);
2029 }
2030
2031 return;
2032
2033dma_error:
2034 dev_info(tx_ring->dev, "TX DMA map failed\n");
2035
2036 /* clear dma mappings for failed tx_bi map */
2037 for (;;) {
2038 tx_bi = &tx_ring->tx_bi[i];
2039 iavf_unmap_and_free_tx_resource(tx_ring, tx_bi);
2040 if (tx_bi == first)
2041 break;
2042 if (i == 0)
2043 i = tx_ring->count;
2044 i--;
2045 }
2046
2047 tx_ring->next_to_use = i;
2048}
2049
2050/**
2051 * iavf_xmit_frame_ring - Sends buffer on Tx ring
2052 * @skb: send buffer
2053 * @tx_ring: ring to send buffer on
2054 *
2055 * Returns NETDEV_TX_OK if sent, else an error code
2056 **/
2057static netdev_tx_t iavf_xmit_frame_ring(struct sk_buff *skb,
2058 struct iavf_ring *tx_ring)
2059{
2060 u64 cd_type_cmd_tso_mss = IAVF_TX_DESC_DTYPE_CONTEXT;
2061 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2062 struct iavf_tx_buffer *first;
2063 u32 td_offset = 0;
2064 u32 tx_flags = 0;
2065 __be16 protocol;
2066 u32 td_cmd = 0;
2067 u8 hdr_len = 0;
2068 int tso, count;
2069
2070 /* prefetch the data, we'll need it later */
2071 prefetch(skb->data);
2072
2073 iavf_trace(xmit_frame_ring, skb, tx_ring);
2074
2075 count = iavf_xmit_descriptor_count(skb);
2076 if (iavf_chk_linearize(skb, count)) {
2077 if (__skb_linearize(skb)) {
2078 dev_kfree_skb_any(skb);
2079 return NETDEV_TX_OK;
2080 }
2081 count = iavf_txd_use_count(skb->len);
2082 tx_ring->tx_stats.tx_linearize++;
2083 }
2084
2085 /* need: 1 descriptor per page * PAGE_SIZE/IAVF_MAX_DATA_PER_TXD,
2086 * + 1 desc for skb_head_len/IAVF_MAX_DATA_PER_TXD,
2087 * + 4 desc gap to avoid the cache line where head is,
2088 * + 1 desc for context descriptor,
2089 * otherwise try next time
2090 */
2091 if (iavf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2092 tx_ring->tx_stats.tx_busy++;
2093 return NETDEV_TX_BUSY;
2094 }
2095
2096 /* record the location of the first descriptor for this packet */
2097 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2098 first->skb = skb;
2099 first->bytecount = skb->len;
2100 first->gso_segs = 1;
2101
2102 /* prepare the xmit flags */
2103 iavf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags);
2104 if (tx_flags & IAVF_TX_FLAGS_HW_OUTER_SINGLE_VLAN) {
2105 cd_type_cmd_tso_mss |= IAVF_TX_CTX_DESC_IL2TAG2 <<
2106 IAVF_TXD_CTX_QW1_CMD_SHIFT;
2107 cd_l2tag2 = FIELD_GET(IAVF_TX_FLAGS_VLAN_MASK, tx_flags);
2108 }
2109
2110 /* obtain protocol of skb */
2111 protocol = vlan_get_protocol(skb);
2112
2113 /* setup IPv4/IPv6 offloads */
2114 if (protocol == htons(ETH_P_IP))
2115 tx_flags |= IAVF_TX_FLAGS_IPV4;
2116 else if (protocol == htons(ETH_P_IPV6))
2117 tx_flags |= IAVF_TX_FLAGS_IPV6;
2118
2119 tso = iavf_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
2120
2121 if (tso < 0)
2122 goto out_drop;
2123 else if (tso)
2124 tx_flags |= IAVF_TX_FLAGS_TSO;
2125
2126 /* Always offload the checksum, since it's in the data descriptor */
2127 tso = iavf_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2128 tx_ring, &cd_tunneling);
2129 if (tso < 0)
2130 goto out_drop;
2131
2132 /* always enable CRC insertion offload */
2133 td_cmd |= IAVF_TX_DESC_CMD_ICRC;
2134
2135 iavf_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2136 cd_tunneling, cd_l2tag2);
2137
2138 iavf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2139 td_cmd, td_offset);
2140
2141 return NETDEV_TX_OK;
2142
2143out_drop:
2144 iavf_trace(xmit_frame_ring_drop, first->skb, tx_ring);
2145 dev_kfree_skb_any(first->skb);
2146 first->skb = NULL;
2147 return NETDEV_TX_OK;
2148}
2149
2150/**
2151 * iavf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2152 * @skb: send buffer
2153 * @netdev: network interface device structure
2154 *
2155 * Returns NETDEV_TX_OK if sent, else an error code
2156 **/
2157netdev_tx_t iavf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2158{
2159 struct iavf_adapter *adapter = netdev_priv(netdev);
2160 struct iavf_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2161
2162 /* hardware can't handle really short frames, hardware padding works
2163 * beyond this point
2164 */
2165 if (unlikely(skb->len < IAVF_MIN_TX_LEN)) {
2166 if (skb_pad(skb, IAVF_MIN_TX_LEN - skb->len))
2167 return NETDEV_TX_OK;
2168 skb->len = IAVF_MIN_TX_LEN;
2169 skb_set_tail_pointer(skb, IAVF_MIN_TX_LEN);
2170 }
2171
2172 return iavf_xmit_frame_ring(skb, tx_ring);
2173}