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1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */
2
3/*
4 * FPGA specific definitions
5 */
6
7#ifndef __CHELSIO_FPGA_DEFS_H__
8#define __CHELSIO_FPGA_DEFS_H__
9
10#define FPGA_PCIX_ADDR_VERSION 0xA08
11#define FPGA_PCIX_ADDR_STAT 0xA0C
12
13/* FPGA master interrupt Cause/Enable bits */
14#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1
15#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2
16#define FPGA_PCIX_INTERRUPT_TP 0x4
17#define FPGA_PCIX_INTERRUPT_MC3 0x8
18#define FPGA_PCIX_INTERRUPT_GMAC 0x10
19#define FPGA_PCIX_INTERRUPT_PCIX 0x20
20
21/* TP interrupt register addresses */
22#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10
23#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14
24#define FPGA_TP_ADDR_VERSION 0xA18
25
26/* TP interrupt Cause/Enable bits */
27#define FPGA_TP_INTERRUPT_MC4 0x1
28#define FPGA_TP_INTERRUPT_MC5 0x2
29
30/*
31 * PM interrupt register addresses
32 */
33#define FPGA_MC3_REG_INTRENABLE 0xA20
34#define FPGA_MC3_REG_INTRCAUSE 0xA24
35#define FPGA_MC3_REG_VERSION 0xA28
36
37/*
38 * GMAC interrupt register addresses
39 */
40#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30
41#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34
42#define FPGA_GMAC_ADDR_VERSION 0xA38
43
44/* GMAC Cause/Enable bits */
45#define FPGA_GMAC_INTERRUPT_PORT0 0x1
46#define FPGA_GMAC_INTERRUPT_PORT1 0x2
47#define FPGA_GMAC_INTERRUPT_PORT2 0x4
48#define FPGA_GMAC_INTERRUPT_PORT3 0x8
49
50/* MI0 registers */
51#define A_MI0_CLK 0xb00
52
53#define S_MI0_CLK_DIV 0
54#define M_MI0_CLK_DIV 0xff
55#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
56#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
57
58#define S_MI0_CLK_CNT 8
59#define M_MI0_CLK_CNT 0xff
60#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
61#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
62
63#define A_MI0_CSR 0xb04
64
65#define S_MI0_CSR_POLL 0
66#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
67#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)
68
69#define S_MI0_PREAMBLE 1
70#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
71#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)
72
73#define S_MI0_INTR_ENABLE 2
74#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
75#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)
76
77#define S_MI0_BUSY 3
78#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
79#define F_MI0_BUSY V_MI0_BUSY(1U)
80
81#define S_MI0_MDIO 4
82#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
83#define F_MI0_MDIO V_MI0_MDIO(1U)
84
85#define A_MI0_ADDR 0xb08
86
87#define S_MI0_PHY_REG_ADDR 0
88#define M_MI0_PHY_REG_ADDR 0x1f
89#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
90#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
91
92#define S_MI0_PHY_ADDR 5
93#define M_MI0_PHY_ADDR 0x1f
94#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
95#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
96
97#define A_MI0_DATA_EXT 0xb0c
98#define A_MI0_DATA_INT 0xb10
99
100/* GMAC registers */
101#define A_GMAC_MACID_LO 0x28
102#define A_GMAC_MACID_HI 0x2c
103#define A_GMAC_CSR 0x30
104
105#define S_INTERFACE 0
106#define M_INTERFACE 0x3
107#define V_INTERFACE(x) ((x) << S_INTERFACE)
108#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
109
110#define S_MAC_TX_ENABLE 2
111#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
112#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)
113
114#define S_MAC_RX_ENABLE 3
115#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
116#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)
117
118#define S_MAC_LB_ENABLE 4
119#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
120#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)
121
122#define S_MAC_SPEED 5
123#define M_MAC_SPEED 0x3
124#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
125#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
126
127#define S_MAC_HD_FC_ENABLE 7
128#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
129#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)
130
131#define S_MAC_HALF_DUPLEX 8
132#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
133#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)
134
135#define S_MAC_PROMISC 9
136#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
137#define F_MAC_PROMISC V_MAC_PROMISC(1U)
138
139#define S_MAC_MC_ENABLE 10
140#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
141#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)
142
143#define S_MAC_RESET 11
144#define V_MAC_RESET(x) ((x) << S_MAC_RESET)
145#define F_MAC_RESET V_MAC_RESET(1U)
146
147#define S_MAC_RX_PAUSE_ENABLE 12
148#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
149#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)
150
151#define S_MAC_TX_PAUSE_ENABLE 13
152#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
153#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)
154
155#define S_MAC_LWM_ENABLE 14
156#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
157#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)
158
159#define S_MAC_MAGIC_PKT_ENABLE 15
160#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
161#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)
162
163#define S_MAC_ISL_ENABLE 16
164#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
165#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)
166
167#define S_MAC_JUMBO_ENABLE 17
168#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
169#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)
170
171#define S_MAC_RX_PAD_ENABLE 18
172#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
173#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)
174
175#define S_MAC_RX_CRC_ENABLE 19
176#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
177#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)
178
179#define A_GMAC_IFS 0x34
180
181#define S_MAC_IFS2 0
182#define M_MAC_IFS2 0x3f
183#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
184#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
185
186#define S_MAC_IFS1 8
187#define M_MAC_IFS1 0x7f
188#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
189#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
190
191#define A_GMAC_JUMBO_FRAME_LEN 0x38
192#define A_GMAC_LNK_DLY 0x3c
193#define A_GMAC_PAUSETIME 0x40
194#define A_GMAC_MCAST_LO 0x44
195#define A_GMAC_MCAST_HI 0x48
196#define A_GMAC_MCAST_MASK_LO 0x4c
197#define A_GMAC_MCAST_MASK_HI 0x50
198#define A_GMAC_RMT_CNT 0x54
199#define A_GMAC_RMT_DATA 0x58
200#define A_GMAC_BACKOFF_SEED 0x5c
201#define A_GMAC_TXF_THRES 0x60
202
203#define S_TXF_READ_THRESHOLD 0
204#define M_TXF_READ_THRESHOLD 0xff
205#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
206#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
207
208#define S_TXF_WRITE_THRESHOLD 16
209#define M_TXF_WRITE_THRESHOLD 0xff
210#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
211#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
212
213#define MAC_REG_BASE 0x600
214#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
215
216#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
217#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
218#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)
219#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)
220#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
221#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
222#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
223#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
224#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
225#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
226#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
227#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
228#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
229#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
230#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
231
232#endif