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1/*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
13 * written by:
14 * Copyright
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
17 *
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
22 *
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/netdevice.h>
33#include <linux/if_arp.h>
34#include <linux/if_ether.h>
35#include <linux/list.h>
36#include <linux/io.h>
37
38#include <linux/can.h>
39#include <linux/can/dev.h>
40#include <linux/can/error.h>
41
42#include "c_can.h"
43
44/* control register */
45#define CONTROL_TEST BIT(7)
46#define CONTROL_CCE BIT(6)
47#define CONTROL_DISABLE_AR BIT(5)
48#define CONTROL_ENABLE_AR (0 << 5)
49#define CONTROL_EIE BIT(3)
50#define CONTROL_SIE BIT(2)
51#define CONTROL_IE BIT(1)
52#define CONTROL_INIT BIT(0)
53
54/* test register */
55#define TEST_RX BIT(7)
56#define TEST_TX1 BIT(6)
57#define TEST_TX2 BIT(5)
58#define TEST_LBACK BIT(4)
59#define TEST_SILENT BIT(3)
60#define TEST_BASIC BIT(2)
61
62/* status register */
63#define STATUS_BOFF BIT(7)
64#define STATUS_EWARN BIT(6)
65#define STATUS_EPASS BIT(5)
66#define STATUS_RXOK BIT(4)
67#define STATUS_TXOK BIT(3)
68
69/* error counter register */
70#define ERR_CNT_TEC_MASK 0xff
71#define ERR_CNT_TEC_SHIFT 0
72#define ERR_CNT_REC_SHIFT 8
73#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
74#define ERR_CNT_RP_SHIFT 15
75#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
76
77/* bit-timing register */
78#define BTR_BRP_MASK 0x3f
79#define BTR_BRP_SHIFT 0
80#define BTR_SJW_SHIFT 6
81#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
82#define BTR_TSEG1_SHIFT 8
83#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
84#define BTR_TSEG2_SHIFT 12
85#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
86
87/* brp extension register */
88#define BRP_EXT_BRPE_MASK 0x0f
89#define BRP_EXT_BRPE_SHIFT 0
90
91/* IFx command request */
92#define IF_COMR_BUSY BIT(15)
93
94/* IFx command mask */
95#define IF_COMM_WR BIT(7)
96#define IF_COMM_MASK BIT(6)
97#define IF_COMM_ARB BIT(5)
98#define IF_COMM_CONTROL BIT(4)
99#define IF_COMM_CLR_INT_PND BIT(3)
100#define IF_COMM_TXRQST BIT(2)
101#define IF_COMM_DATAA BIT(1)
102#define IF_COMM_DATAB BIT(0)
103#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
104 IF_COMM_CONTROL | IF_COMM_TXRQST | \
105 IF_COMM_DATAA | IF_COMM_DATAB)
106
107/* IFx arbitration */
108#define IF_ARB_MSGVAL BIT(15)
109#define IF_ARB_MSGXTD BIT(14)
110#define IF_ARB_TRANSMIT BIT(13)
111
112/* IFx message control */
113#define IF_MCONT_NEWDAT BIT(15)
114#define IF_MCONT_MSGLST BIT(14)
115#define IF_MCONT_CLR_MSGLST (0 << 14)
116#define IF_MCONT_INTPND BIT(13)
117#define IF_MCONT_UMASK BIT(12)
118#define IF_MCONT_TXIE BIT(11)
119#define IF_MCONT_RXIE BIT(10)
120#define IF_MCONT_RMTEN BIT(9)
121#define IF_MCONT_TXRQST BIT(8)
122#define IF_MCONT_EOB BIT(7)
123#define IF_MCONT_DLC_MASK 0xf
124
125/*
126 * IFx register masks:
127 * allow easy operation on 16-bit registers when the
128 * argument is 32-bit instead
129 */
130#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
131#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
132
133/* message object split */
134#define C_CAN_NO_OF_OBJECTS 32
135#define C_CAN_MSG_OBJ_RX_NUM 16
136#define C_CAN_MSG_OBJ_TX_NUM 16
137
138#define C_CAN_MSG_OBJ_RX_FIRST 1
139#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
140 C_CAN_MSG_OBJ_RX_NUM - 1)
141
142#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
143#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
144 C_CAN_MSG_OBJ_TX_NUM - 1)
145
146#define C_CAN_MSG_OBJ_RX_SPLIT 9
147#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
148
149#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
150#define RECEIVE_OBJECT_BITS 0x0000ffff
151
152/* status interrupt */
153#define STATUS_INTERRUPT 0x8000
154
155/* global interrupt masks */
156#define ENABLE_ALL_INTERRUPTS 1
157#define DISABLE_ALL_INTERRUPTS 0
158
159/* minimum timeout for checking BUSY status */
160#define MIN_TIMEOUT_VALUE 6
161
162/* napi related */
163#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
164
165/* c_can lec values */
166enum c_can_lec_type {
167 LEC_NO_ERROR = 0,
168 LEC_STUFF_ERROR,
169 LEC_FORM_ERROR,
170 LEC_ACK_ERROR,
171 LEC_BIT1_ERROR,
172 LEC_BIT0_ERROR,
173 LEC_CRC_ERROR,
174 LEC_UNUSED,
175};
176
177/*
178 * c_can error types:
179 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
180 */
181enum c_can_bus_error_types {
182 C_CAN_NO_ERROR = 0,
183 C_CAN_BUS_OFF,
184 C_CAN_ERROR_WARNING,
185 C_CAN_ERROR_PASSIVE,
186};
187
188static struct can_bittiming_const c_can_bittiming_const = {
189 .name = KBUILD_MODNAME,
190 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
191 .tseg1_max = 16,
192 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
193 .tseg2_max = 8,
194 .sjw_max = 4,
195 .brp_min = 1,
196 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
197 .brp_inc = 1,
198};
199
200static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
201{
202 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
203 C_CAN_MSG_OBJ_TX_FIRST;
204}
205
206static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
207{
208 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
209 C_CAN_MSG_OBJ_TX_FIRST;
210}
211
212static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
213{
214 u32 val = priv->read_reg(priv, reg);
215 val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
216 return val;
217}
218
219static void c_can_enable_all_interrupts(struct c_can_priv *priv,
220 int enable)
221{
222 unsigned int cntrl_save = priv->read_reg(priv,
223 &priv->regs->control);
224
225 if (enable)
226 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
227 else
228 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
229
230 priv->write_reg(priv, &priv->regs->control, cntrl_save);
231}
232
233static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
234{
235 int count = MIN_TIMEOUT_VALUE;
236
237 while (count && priv->read_reg(priv,
238 &priv->regs->ifregs[iface].com_req) &
239 IF_COMR_BUSY) {
240 count--;
241 udelay(1);
242 }
243
244 if (!count)
245 return 1;
246
247 return 0;
248}
249
250static inline void c_can_object_get(struct net_device *dev,
251 int iface, int objno, int mask)
252{
253 struct c_can_priv *priv = netdev_priv(dev);
254
255 /*
256 * As per specs, after writting the message object number in the
257 * IF command request register the transfer b/w interface
258 * register and message RAM must be complete in 6 CAN-CLK
259 * period.
260 */
261 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
262 IFX_WRITE_LOW_16BIT(mask));
263 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
264 IFX_WRITE_LOW_16BIT(objno));
265
266 if (c_can_msg_obj_is_busy(priv, iface))
267 netdev_err(dev, "timed out in object get\n");
268}
269
270static inline void c_can_object_put(struct net_device *dev,
271 int iface, int objno, int mask)
272{
273 struct c_can_priv *priv = netdev_priv(dev);
274
275 /*
276 * As per specs, after writting the message object number in the
277 * IF command request register the transfer b/w interface
278 * register and message RAM must be complete in 6 CAN-CLK
279 * period.
280 */
281 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
282 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
283 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
284 IFX_WRITE_LOW_16BIT(objno));
285
286 if (c_can_msg_obj_is_busy(priv, iface))
287 netdev_err(dev, "timed out in object put\n");
288}
289
290static void c_can_write_msg_object(struct net_device *dev,
291 int iface, struct can_frame *frame, int objno)
292{
293 int i;
294 u16 flags = 0;
295 unsigned int id;
296 struct c_can_priv *priv = netdev_priv(dev);
297
298 if (!(frame->can_id & CAN_RTR_FLAG))
299 flags |= IF_ARB_TRANSMIT;
300
301 if (frame->can_id & CAN_EFF_FLAG) {
302 id = frame->can_id & CAN_EFF_MASK;
303 flags |= IF_ARB_MSGXTD;
304 } else
305 id = ((frame->can_id & CAN_SFF_MASK) << 18);
306
307 flags |= IF_ARB_MSGVAL;
308
309 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
310 IFX_WRITE_LOW_16BIT(id));
311 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, flags |
312 IFX_WRITE_HIGH_16BIT(id));
313
314 for (i = 0; i < frame->can_dlc; i += 2) {
315 priv->write_reg(priv, &priv->regs->ifregs[iface].data[i / 2],
316 frame->data[i] | (frame->data[i + 1] << 8));
317 }
318
319 /* enable interrupt for this message object */
320 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
321 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
322 frame->can_dlc);
323 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
324}
325
326static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
327 int iface, int ctrl_mask,
328 int obj)
329{
330 struct c_can_priv *priv = netdev_priv(dev);
331
332 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
333 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
334 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
335
336}
337
338static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
339 int iface,
340 int ctrl_mask)
341{
342 int i;
343 struct c_can_priv *priv = netdev_priv(dev);
344
345 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
346 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
347 ctrl_mask & ~(IF_MCONT_MSGLST |
348 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
349 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
350 }
351}
352
353static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
354 int iface, int ctrl_mask,
355 int obj)
356{
357 struct c_can_priv *priv = netdev_priv(dev);
358
359 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
360 ctrl_mask & ~(IF_MCONT_MSGLST |
361 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
362 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
363}
364
365static void c_can_handle_lost_msg_obj(struct net_device *dev,
366 int iface, int objno)
367{
368 struct c_can_priv *priv = netdev_priv(dev);
369 struct net_device_stats *stats = &dev->stats;
370 struct sk_buff *skb;
371 struct can_frame *frame;
372
373 netdev_err(dev, "msg lost in buffer %d\n", objno);
374
375 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
376
377 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
378 IF_MCONT_CLR_MSGLST);
379
380 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
381
382 /* create an error msg */
383 skb = alloc_can_err_skb(dev, &frame);
384 if (unlikely(!skb))
385 return;
386
387 frame->can_id |= CAN_ERR_CRTL;
388 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
389 stats->rx_errors++;
390 stats->rx_over_errors++;
391
392 netif_receive_skb(skb);
393}
394
395static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
396{
397 u16 flags, data;
398 int i;
399 unsigned int val;
400 struct c_can_priv *priv = netdev_priv(dev);
401 struct net_device_stats *stats = &dev->stats;
402 struct sk_buff *skb;
403 struct can_frame *frame;
404
405 skb = alloc_can_skb(dev, &frame);
406 if (!skb) {
407 stats->rx_dropped++;
408 return -ENOMEM;
409 }
410
411 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
412
413 flags = priv->read_reg(priv, &priv->regs->ifregs[iface].arb2);
414 val = priv->read_reg(priv, &priv->regs->ifregs[iface].arb1) |
415 (flags << 16);
416
417 if (flags & IF_ARB_MSGXTD)
418 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
419 else
420 frame->can_id = (val >> 18) & CAN_SFF_MASK;
421
422 if (flags & IF_ARB_TRANSMIT)
423 frame->can_id |= CAN_RTR_FLAG;
424 else {
425 for (i = 0; i < frame->can_dlc; i += 2) {
426 data = priv->read_reg(priv,
427 &priv->regs->ifregs[iface].data[i / 2]);
428 frame->data[i] = data;
429 frame->data[i + 1] = data >> 8;
430 }
431 }
432
433 netif_receive_skb(skb);
434
435 stats->rx_packets++;
436 stats->rx_bytes += frame->can_dlc;
437
438 return 0;
439}
440
441static void c_can_setup_receive_object(struct net_device *dev, int iface,
442 int objno, unsigned int mask,
443 unsigned int id, unsigned int mcont)
444{
445 struct c_can_priv *priv = netdev_priv(dev);
446
447 priv->write_reg(priv, &priv->regs->ifregs[iface].mask1,
448 IFX_WRITE_LOW_16BIT(mask));
449 priv->write_reg(priv, &priv->regs->ifregs[iface].mask2,
450 IFX_WRITE_HIGH_16BIT(mask));
451
452 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
453 IFX_WRITE_LOW_16BIT(id));
454 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2,
455 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
456
457 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont);
458 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
459
460 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
461 c_can_read_reg32(priv, &priv->regs->msgval1));
462}
463
464static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
465{
466 struct c_can_priv *priv = netdev_priv(dev);
467
468 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 0);
469 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, 0);
470 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 0);
471
472 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
473
474 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
475 c_can_read_reg32(priv, &priv->regs->msgval1));
476}
477
478static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
479{
480 int val = c_can_read_reg32(priv, &priv->regs->txrqst1);
481
482 /*
483 * as transmission request register's bit n-1 corresponds to
484 * message object n, we need to handle the same properly.
485 */
486 if (val & (1 << (objno - 1)))
487 return 1;
488
489 return 0;
490}
491
492static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
493 struct net_device *dev)
494{
495 u32 msg_obj_no;
496 struct c_can_priv *priv = netdev_priv(dev);
497 struct can_frame *frame = (struct can_frame *)skb->data;
498
499 if (can_dropped_invalid_skb(dev, skb))
500 return NETDEV_TX_OK;
501
502 msg_obj_no = get_tx_next_msg_obj(priv);
503
504 /* prepare message object for transmission */
505 c_can_write_msg_object(dev, 0, frame, msg_obj_no);
506 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
507
508 /*
509 * we have to stop the queue in case of a wrap around or
510 * if the next TX message object is still in use
511 */
512 priv->tx_next++;
513 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
514 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
515 netif_stop_queue(dev);
516
517 return NETDEV_TX_OK;
518}
519
520static int c_can_set_bittiming(struct net_device *dev)
521{
522 unsigned int reg_btr, reg_brpe, ctrl_save;
523 u8 brp, brpe, sjw, tseg1, tseg2;
524 u32 ten_bit_brp;
525 struct c_can_priv *priv = netdev_priv(dev);
526 const struct can_bittiming *bt = &priv->can.bittiming;
527
528 /* c_can provides a 6-bit brp and 4-bit brpe fields */
529 ten_bit_brp = bt->brp - 1;
530 brp = ten_bit_brp & BTR_BRP_MASK;
531 brpe = ten_bit_brp >> 6;
532
533 sjw = bt->sjw - 1;
534 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
535 tseg2 = bt->phase_seg2 - 1;
536 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
537 (tseg2 << BTR_TSEG2_SHIFT);
538 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
539
540 netdev_info(dev,
541 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
542
543 ctrl_save = priv->read_reg(priv, &priv->regs->control);
544 priv->write_reg(priv, &priv->regs->control,
545 ctrl_save | CONTROL_CCE | CONTROL_INIT);
546 priv->write_reg(priv, &priv->regs->btr, reg_btr);
547 priv->write_reg(priv, &priv->regs->brp_ext, reg_brpe);
548 priv->write_reg(priv, &priv->regs->control, ctrl_save);
549
550 return 0;
551}
552
553/*
554 * Configure C_CAN message objects for Tx and Rx purposes:
555 * C_CAN provides a total of 32 message objects that can be configured
556 * either for Tx or Rx purposes. Here the first 16 message objects are used as
557 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
558 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
559 * See user guide document for further details on configuring message
560 * objects.
561 */
562static void c_can_configure_msg_objects(struct net_device *dev)
563{
564 int i;
565
566 /* first invalidate all message objects */
567 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
568 c_can_inval_msg_object(dev, 0, i);
569
570 /* setup receive message objects */
571 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
572 c_can_setup_receive_object(dev, 0, i, 0, 0,
573 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
574
575 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
576 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
577}
578
579/*
580 * Configure C_CAN chip:
581 * - enable/disable auto-retransmission
582 * - set operating mode
583 * - configure message objects
584 */
585static void c_can_chip_config(struct net_device *dev)
586{
587 struct c_can_priv *priv = netdev_priv(dev);
588
589 /* enable automatic retransmission */
590 priv->write_reg(priv, &priv->regs->control,
591 CONTROL_ENABLE_AR);
592
593 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY &
594 CAN_CTRLMODE_LOOPBACK)) {
595 /* loopback + silent mode : useful for hot self-test */
596 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
597 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
598 priv->write_reg(priv, &priv->regs->test,
599 TEST_LBACK | TEST_SILENT);
600 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
601 /* loopback mode : useful for self-test function */
602 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
603 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
604 priv->write_reg(priv, &priv->regs->test, TEST_LBACK);
605 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
606 /* silent mode : bus-monitoring mode */
607 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
608 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
609 priv->write_reg(priv, &priv->regs->test, TEST_SILENT);
610 } else
611 /* normal mode*/
612 priv->write_reg(priv, &priv->regs->control,
613 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
614
615 /* configure message objects */
616 c_can_configure_msg_objects(dev);
617
618 /* set a `lec` value so that we can check for updates later */
619 priv->write_reg(priv, &priv->regs->status, LEC_UNUSED);
620
621 /* set bittiming params */
622 c_can_set_bittiming(dev);
623}
624
625static void c_can_start(struct net_device *dev)
626{
627 struct c_can_priv *priv = netdev_priv(dev);
628
629 /* basic c_can configuration */
630 c_can_chip_config(dev);
631
632 priv->can.state = CAN_STATE_ERROR_ACTIVE;
633
634 /* reset tx helper pointers */
635 priv->tx_next = priv->tx_echo = 0;
636
637 /* enable status change, error and module interrupts */
638 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
639}
640
641static void c_can_stop(struct net_device *dev)
642{
643 struct c_can_priv *priv = netdev_priv(dev);
644
645 /* disable all interrupts */
646 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
647
648 /* set the state as STOPPED */
649 priv->can.state = CAN_STATE_STOPPED;
650}
651
652static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
653{
654 switch (mode) {
655 case CAN_MODE_START:
656 c_can_start(dev);
657 netif_wake_queue(dev);
658 break;
659 default:
660 return -EOPNOTSUPP;
661 }
662
663 return 0;
664}
665
666static int c_can_get_berr_counter(const struct net_device *dev,
667 struct can_berr_counter *bec)
668{
669 unsigned int reg_err_counter;
670 struct c_can_priv *priv = netdev_priv(dev);
671
672 reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
673 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
674 ERR_CNT_REC_SHIFT;
675 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
676
677 return 0;
678}
679
680/*
681 * theory of operation:
682 *
683 * priv->tx_echo holds the number of the oldest can_frame put for
684 * transmission into the hardware, but not yet ACKed by the CAN tx
685 * complete IRQ.
686 *
687 * We iterate from priv->tx_echo to priv->tx_next and check if the
688 * packet has been transmitted, echo it back to the CAN framework.
689 * If we discover a not yet transmitted package, stop looking for more.
690 */
691static void c_can_do_tx(struct net_device *dev)
692{
693 u32 val;
694 u32 msg_obj_no;
695 struct c_can_priv *priv = netdev_priv(dev);
696 struct net_device_stats *stats = &dev->stats;
697
698 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
699 msg_obj_no = get_tx_echo_msg_obj(priv);
700 val = c_can_read_reg32(priv, &priv->regs->txrqst1);
701 if (!(val & (1 << msg_obj_no))) {
702 can_get_echo_skb(dev,
703 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
704 stats->tx_bytes += priv->read_reg(priv,
705 &priv->regs->ifregs[0].msg_cntrl)
706 & IF_MCONT_DLC_MASK;
707 stats->tx_packets++;
708 c_can_inval_msg_object(dev, 0, msg_obj_no);
709 }
710 }
711
712 /* restart queue if wrap-up or if queue stalled on last pkt */
713 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
714 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
715 netif_wake_queue(dev);
716}
717
718/*
719 * theory of operation:
720 *
721 * c_can core saves a received CAN message into the first free message
722 * object it finds free (starting with the lowest). Bits NEWDAT and
723 * INTPND are set for this message object indicating that a new message
724 * has arrived. To work-around this issue, we keep two groups of message
725 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
726 *
727 * To ensure in-order frame reception we use the following
728 * approach while re-activating a message object to receive further
729 * frames:
730 * - if the current message object number is lower than
731 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
732 * the INTPND bit.
733 * - if the current message object number is equal to
734 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
735 * receive message objects.
736 * - if the current message object number is greater than
737 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
738 * only this message object.
739 */
740static int c_can_do_rx_poll(struct net_device *dev, int quota)
741{
742 u32 num_rx_pkts = 0;
743 unsigned int msg_obj, msg_ctrl_save;
744 struct c_can_priv *priv = netdev_priv(dev);
745 u32 val = c_can_read_reg32(priv, &priv->regs->intpnd1);
746
747 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
748 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
749 val = c_can_read_reg32(priv, &priv->regs->intpnd1),
750 msg_obj++) {
751 /*
752 * as interrupt pending register's bit n-1 corresponds to
753 * message object n, we need to handle the same properly.
754 */
755 if (val & (1 << (msg_obj - 1))) {
756 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
757 ~IF_COMM_TXRQST);
758 msg_ctrl_save = priv->read_reg(priv,
759 &priv->regs->ifregs[0].msg_cntrl);
760
761 if (msg_ctrl_save & IF_MCONT_EOB)
762 return num_rx_pkts;
763
764 if (msg_ctrl_save & IF_MCONT_MSGLST) {
765 c_can_handle_lost_msg_obj(dev, 0, msg_obj);
766 num_rx_pkts++;
767 quota--;
768 continue;
769 }
770
771 if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
772 continue;
773
774 /* read the data from the message object */
775 c_can_read_msg_object(dev, 0, msg_ctrl_save);
776
777 if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
778 c_can_mark_rx_msg_obj(dev, 0,
779 msg_ctrl_save, msg_obj);
780 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
781 /* activate this msg obj */
782 c_can_activate_rx_msg_obj(dev, 0,
783 msg_ctrl_save, msg_obj);
784 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
785 /* activate all lower message objects */
786 c_can_activate_all_lower_rx_msg_obj(dev,
787 0, msg_ctrl_save);
788
789 num_rx_pkts++;
790 quota--;
791 }
792 }
793
794 return num_rx_pkts;
795}
796
797static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
798{
799 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
800 (priv->current_status & LEC_UNUSED);
801}
802
803static int c_can_handle_state_change(struct net_device *dev,
804 enum c_can_bus_error_types error_type)
805{
806 unsigned int reg_err_counter;
807 unsigned int rx_err_passive;
808 struct c_can_priv *priv = netdev_priv(dev);
809 struct net_device_stats *stats = &dev->stats;
810 struct can_frame *cf;
811 struct sk_buff *skb;
812 struct can_berr_counter bec;
813
814 /* propagate the error condition to the CAN stack */
815 skb = alloc_can_err_skb(dev, &cf);
816 if (unlikely(!skb))
817 return 0;
818
819 c_can_get_berr_counter(dev, &bec);
820 reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
821 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
822 ERR_CNT_RP_SHIFT;
823
824 switch (error_type) {
825 case C_CAN_ERROR_WARNING:
826 /* error warning state */
827 priv->can.can_stats.error_warning++;
828 priv->can.state = CAN_STATE_ERROR_WARNING;
829 cf->can_id |= CAN_ERR_CRTL;
830 cf->data[1] = (bec.txerr > bec.rxerr) ?
831 CAN_ERR_CRTL_TX_WARNING :
832 CAN_ERR_CRTL_RX_WARNING;
833 cf->data[6] = bec.txerr;
834 cf->data[7] = bec.rxerr;
835
836 break;
837 case C_CAN_ERROR_PASSIVE:
838 /* error passive state */
839 priv->can.can_stats.error_passive++;
840 priv->can.state = CAN_STATE_ERROR_PASSIVE;
841 cf->can_id |= CAN_ERR_CRTL;
842 if (rx_err_passive)
843 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
844 if (bec.txerr > 127)
845 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
846
847 cf->data[6] = bec.txerr;
848 cf->data[7] = bec.rxerr;
849 break;
850 case C_CAN_BUS_OFF:
851 /* bus-off state */
852 priv->can.state = CAN_STATE_BUS_OFF;
853 cf->can_id |= CAN_ERR_BUSOFF;
854 /*
855 * disable all interrupts in bus-off mode to ensure that
856 * the CPU is not hogged down
857 */
858 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
859 can_bus_off(dev);
860 break;
861 default:
862 break;
863 }
864
865 netif_receive_skb(skb);
866 stats->rx_packets++;
867 stats->rx_bytes += cf->can_dlc;
868
869 return 1;
870}
871
872static int c_can_handle_bus_err(struct net_device *dev,
873 enum c_can_lec_type lec_type)
874{
875 struct c_can_priv *priv = netdev_priv(dev);
876 struct net_device_stats *stats = &dev->stats;
877 struct can_frame *cf;
878 struct sk_buff *skb;
879
880 /*
881 * early exit if no lec update or no error.
882 * no lec update means that no CAN bus event has been detected
883 * since CPU wrote 0x7 value to status reg.
884 */
885 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
886 return 0;
887
888 /* propagate the error condition to the CAN stack */
889 skb = alloc_can_err_skb(dev, &cf);
890 if (unlikely(!skb))
891 return 0;
892
893 /*
894 * check for 'last error code' which tells us the
895 * type of the last error to occur on the CAN bus
896 */
897
898 /* common for all type of bus errors */
899 priv->can.can_stats.bus_error++;
900 stats->rx_errors++;
901 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
902 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
903
904 switch (lec_type) {
905 case LEC_STUFF_ERROR:
906 netdev_dbg(dev, "stuff error\n");
907 cf->data[2] |= CAN_ERR_PROT_STUFF;
908 break;
909 case LEC_FORM_ERROR:
910 netdev_dbg(dev, "form error\n");
911 cf->data[2] |= CAN_ERR_PROT_FORM;
912 break;
913 case LEC_ACK_ERROR:
914 netdev_dbg(dev, "ack error\n");
915 cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
916 CAN_ERR_PROT_LOC_ACK_DEL);
917 break;
918 case LEC_BIT1_ERROR:
919 netdev_dbg(dev, "bit1 error\n");
920 cf->data[2] |= CAN_ERR_PROT_BIT1;
921 break;
922 case LEC_BIT0_ERROR:
923 netdev_dbg(dev, "bit0 error\n");
924 cf->data[2] |= CAN_ERR_PROT_BIT0;
925 break;
926 case LEC_CRC_ERROR:
927 netdev_dbg(dev, "CRC error\n");
928 cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
929 CAN_ERR_PROT_LOC_CRC_DEL);
930 break;
931 default:
932 break;
933 }
934
935 /* set a `lec` value so that we can check for updates later */
936 priv->write_reg(priv, &priv->regs->status, LEC_UNUSED);
937
938 netif_receive_skb(skb);
939 stats->rx_packets++;
940 stats->rx_bytes += cf->can_dlc;
941
942 return 1;
943}
944
945static int c_can_poll(struct napi_struct *napi, int quota)
946{
947 u16 irqstatus;
948 int lec_type = 0;
949 int work_done = 0;
950 struct net_device *dev = napi->dev;
951 struct c_can_priv *priv = netdev_priv(dev);
952
953 irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
954 if (!irqstatus)
955 goto end;
956
957 /* status events have the highest priority */
958 if (irqstatus == STATUS_INTERRUPT) {
959 priv->current_status = priv->read_reg(priv,
960 &priv->regs->status);
961
962 /* handle Tx/Rx events */
963 if (priv->current_status & STATUS_TXOK)
964 priv->write_reg(priv, &priv->regs->status,
965 priv->current_status & ~STATUS_TXOK);
966
967 if (priv->current_status & STATUS_RXOK)
968 priv->write_reg(priv, &priv->regs->status,
969 priv->current_status & ~STATUS_RXOK);
970
971 /* handle state changes */
972 if ((priv->current_status & STATUS_EWARN) &&
973 (!(priv->last_status & STATUS_EWARN))) {
974 netdev_dbg(dev, "entered error warning state\n");
975 work_done += c_can_handle_state_change(dev,
976 C_CAN_ERROR_WARNING);
977 }
978 if ((priv->current_status & STATUS_EPASS) &&
979 (!(priv->last_status & STATUS_EPASS))) {
980 netdev_dbg(dev, "entered error passive state\n");
981 work_done += c_can_handle_state_change(dev,
982 C_CAN_ERROR_PASSIVE);
983 }
984 if ((priv->current_status & STATUS_BOFF) &&
985 (!(priv->last_status & STATUS_BOFF))) {
986 netdev_dbg(dev, "entered bus off state\n");
987 work_done += c_can_handle_state_change(dev,
988 C_CAN_BUS_OFF);
989 }
990
991 /* handle bus recovery events */
992 if ((!(priv->current_status & STATUS_BOFF)) &&
993 (priv->last_status & STATUS_BOFF)) {
994 netdev_dbg(dev, "left bus off state\n");
995 priv->can.state = CAN_STATE_ERROR_ACTIVE;
996 }
997 if ((!(priv->current_status & STATUS_EPASS)) &&
998 (priv->last_status & STATUS_EPASS)) {
999 netdev_dbg(dev, "left error passive state\n");
1000 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1001 }
1002
1003 priv->last_status = priv->current_status;
1004
1005 /* handle lec errors on the bus */
1006 lec_type = c_can_has_and_handle_berr(priv);
1007 if (lec_type)
1008 work_done += c_can_handle_bus_err(dev, lec_type);
1009 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1010 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1011 /* handle events corresponding to receive message objects */
1012 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1013 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1014 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1015 /* handle events corresponding to transmit message objects */
1016 c_can_do_tx(dev);
1017 }
1018
1019end:
1020 if (work_done < quota) {
1021 napi_complete(napi);
1022 /* enable all IRQs */
1023 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1024 }
1025
1026 return work_done;
1027}
1028
1029static irqreturn_t c_can_isr(int irq, void *dev_id)
1030{
1031 u16 irqstatus;
1032 struct net_device *dev = (struct net_device *)dev_id;
1033 struct c_can_priv *priv = netdev_priv(dev);
1034
1035 irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
1036 if (!irqstatus)
1037 return IRQ_NONE;
1038
1039 /* disable all interrupts and schedule the NAPI */
1040 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1041 napi_schedule(&priv->napi);
1042
1043 return IRQ_HANDLED;
1044}
1045
1046static int c_can_open(struct net_device *dev)
1047{
1048 int err;
1049 struct c_can_priv *priv = netdev_priv(dev);
1050
1051 /* open the can device */
1052 err = open_candev(dev);
1053 if (err) {
1054 netdev_err(dev, "failed to open can device\n");
1055 return err;
1056 }
1057
1058 /* register interrupt handler */
1059 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1060 dev);
1061 if (err < 0) {
1062 netdev_err(dev, "failed to request interrupt\n");
1063 goto exit_irq_fail;
1064 }
1065
1066 /* start the c_can controller */
1067 c_can_start(dev);
1068
1069 napi_enable(&priv->napi);
1070 netif_start_queue(dev);
1071
1072 return 0;
1073
1074exit_irq_fail:
1075 close_candev(dev);
1076 return err;
1077}
1078
1079static int c_can_close(struct net_device *dev)
1080{
1081 struct c_can_priv *priv = netdev_priv(dev);
1082
1083 netif_stop_queue(dev);
1084 napi_disable(&priv->napi);
1085 c_can_stop(dev);
1086 free_irq(dev->irq, dev);
1087 close_candev(dev);
1088
1089 return 0;
1090}
1091
1092struct net_device *alloc_c_can_dev(void)
1093{
1094 struct net_device *dev;
1095 struct c_can_priv *priv;
1096
1097 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1098 if (!dev)
1099 return NULL;
1100
1101 priv = netdev_priv(dev);
1102 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1103
1104 priv->dev = dev;
1105 priv->can.bittiming_const = &c_can_bittiming_const;
1106 priv->can.do_set_mode = c_can_set_mode;
1107 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1108 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1109 CAN_CTRLMODE_LISTENONLY |
1110 CAN_CTRLMODE_BERR_REPORTING;
1111
1112 return dev;
1113}
1114EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1115
1116void free_c_can_dev(struct net_device *dev)
1117{
1118 free_candev(dev);
1119}
1120EXPORT_SYMBOL_GPL(free_c_can_dev);
1121
1122static const struct net_device_ops c_can_netdev_ops = {
1123 .ndo_open = c_can_open,
1124 .ndo_stop = c_can_close,
1125 .ndo_start_xmit = c_can_start_xmit,
1126};
1127
1128int register_c_can_dev(struct net_device *dev)
1129{
1130 dev->flags |= IFF_ECHO; /* we support local echo */
1131 dev->netdev_ops = &c_can_netdev_ops;
1132
1133 return register_candev(dev);
1134}
1135EXPORT_SYMBOL_GPL(register_c_can_dev);
1136
1137void unregister_c_can_dev(struct net_device *dev)
1138{
1139 struct c_can_priv *priv = netdev_priv(dev);
1140
1141 /* disable all interrupts */
1142 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1143
1144 unregister_candev(dev);
1145}
1146EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1147
1148MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1149MODULE_LICENSE("GPL v2");
1150MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");