1/*
  2 * Linux network driver for Brocade Converged Network Adapter.
  3 *
  4 * This program is free software; you can redistribute it and/or modify it
  5 * under the terms of the GNU General Public License (GPL) Version 2 as
  6 * published by the Free Software Foundation
  7 *
  8 * This program is distributed in the hope that it will be useful, but
  9 * WITHOUT ANY WARRANTY; without even the implied warranty of
 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 11 * General Public License for more details.
 12 */
 13/*
 14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
 15 * All rights reserved
 16 * www.brocade.com
 17 */
 18
 19#ifndef __BFA_IOC_H__
 20#define __BFA_IOC_H__
 21
 22#include "bfa_cs.h"
 23#include "bfi.h"
 24#include "cna.h"
 25
 26#define BFA_IOC_TOV		3000	/* msecs */
 27#define BFA_IOC_HWSEM_TOV	500	/* msecs */
 28#define BFA_IOC_HB_TOV		500	/* msecs */
 29#define BFA_IOC_HWINIT_MAX	5
 30
 31/**
 32 * PCI device information required by IOC
 33 */
 34struct bfa_pcidev {
 35	int	pci_slot;
 36	u8	pci_func;
 37	u16	device_id;
 38	void	__iomem *pci_bar_kva;
 39};
 40
 41/**
 42 * Structure used to remember the DMA-able memory block's KVA and Physical
 43 * Address
 44 */
 45struct bfa_dma {
 46	void	*kva;	/* ! Kernel virtual address	*/
 47	u64	pa;	/* ! Physical address		*/
 48};
 49
 50#define BFA_DMA_ALIGN_SZ	256
 51
 52/**
 53 * smem size for Crossbow and Catapult
 54 */
 55#define BFI_SMEM_CB_SIZE	0x200000U	/* ! 2MB for crossbow	*/
 56#define BFI_SMEM_CT_SIZE	0x280000U	/* ! 2.5MB for catapult	*/
 57
 58/**
 59 * @brief BFA dma address assignment macro. (big endian format)
 60 */
 61#define bfa_dma_be_addr_set(dma_addr, pa)	\
 62		__bfa_dma_be_addr_set(&dma_addr, (u64)pa)
 63static inline void
 64__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
 65{
 66	dma_addr->a32.addr_lo = (u32) htonl(pa);
 67	dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
 68}
 69
 70struct bfa_ioc_regs {
 71	void __iomem *hfn_mbox_cmd;
 72	void __iomem *hfn_mbox;
 73	void __iomem *lpu_mbox_cmd;
 74	void __iomem *lpu_mbox;
 75	void __iomem *pss_ctl_reg;
 76	void __iomem *pss_err_status_reg;
 77	void __iomem *app_pll_fast_ctl_reg;
 78	void __iomem *app_pll_slow_ctl_reg;
 79	void __iomem *ioc_sem_reg;
 80	void __iomem *ioc_usage_sem_reg;
 81	void __iomem *ioc_init_sem_reg;
 82	void __iomem *ioc_usage_reg;
 83	void __iomem *host_page_num_fn;
 84	void __iomem *heartbeat;
 85	void __iomem *ioc_fwstate;
 86	void __iomem *alt_ioc_fwstate;
 87	void __iomem *ll_halt;
 88	void __iomem *alt_ll_halt;
 89	void __iomem *err_set;
 90	void __iomem *ioc_fail_sync;
 91	void __iomem *shirq_isr_next;
 92	void __iomem *shirq_msk_next;
 93	void __iomem *smem_page_start;
 94	u32	smem_pg0;
 95};
 96
 97/**
 98 * IOC Mailbox structures
 99 */
100typedef void (*bfa_mbox_cmd_cbfn_t)(void *cbarg);
101struct bfa_mbox_cmd {
102	struct list_head	qe;
103	bfa_mbox_cmd_cbfn_t     cbfn;
104	void		    *cbarg;
105	u32     msg[BFI_IOC_MSGSZ];
106};
107
108/**
109 * IOC mailbox module
110 */
111typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
112struct bfa_ioc_mbox_mod {
113	struct list_head	cmd_q;		/*!< pending mbox queue	*/
114	int			nmclass;	/*!< number of handlers */
115	struct {
116		bfa_ioc_mbox_mcfunc_t	cbfn;	/*!< message handlers	*/
117		void			*cbarg;
118	} mbhdlr[BFI_MC_MAX];
119};
120
121/**
122 * IOC callback function interfaces
123 */
124typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
125typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
126typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
127typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
128struct bfa_ioc_cbfn {
129	bfa_ioc_enable_cbfn_t	enable_cbfn;
130	bfa_ioc_disable_cbfn_t	disable_cbfn;
131	bfa_ioc_hbfail_cbfn_t	hbfail_cbfn;
132	bfa_ioc_reset_cbfn_t	reset_cbfn;
133};
134
135/**
136 * IOC event notification mechanism.
137 */
138enum bfa_ioc_event {
139	BFA_IOC_E_ENABLED	= 1,
140	BFA_IOC_E_DISABLED	= 2,
141	BFA_IOC_E_FAILED	= 3,
142};
143
144typedef void (*bfa_ioc_notify_cbfn_t)(void *, enum bfa_ioc_event);
145
146struct bfa_ioc_notify {
147	struct list_head	qe;
148	bfa_ioc_notify_cbfn_t	cbfn;
149	void			*cbarg;
150};
151
152/**
153 * Heartbeat failure notification queue element.
154 */
155struct bfa_ioc_hbfail_notify {
156	struct list_head	qe;
157	bfa_ioc_hbfail_cbfn_t	cbfn;
158	void			*cbarg;
159};
160
161/**
162 * Initialize a heartbeat failure notification structure
163 */
164#define bfa_ioc_notify_init(__notify, __cbfn, __cbarg) do {	\
165	(__notify)->cbfn = (__cbfn);				\
166	(__notify)->cbarg = (__cbarg);				\
167} while (0)
168
169struct bfa_iocpf {
170	bfa_fsm_t		fsm;
171	struct bfa_ioc		*ioc;
172	u32			retry_count;
173	bool			auto_recover;
174};
175
176struct bfa_ioc {
177	bfa_fsm_t		fsm;
178	struct bfa		*bfa;
179	struct bfa_pcidev	pcidev;
180	struct timer_list	ioc_timer;
181	struct timer_list	iocpf_timer;
182	struct timer_list	sem_timer;
183	struct timer_list	hb_timer;
184	u32			hb_count;
185	struct list_head	notify_q;
186	void			*dbg_fwsave;
187	int			dbg_fwsave_len;
188	bool			dbg_fwsave_once;
189	enum bfi_mclass		ioc_mc;
190	struct bfa_ioc_regs	ioc_regs;
191	struct bfa_ioc_drv_stats stats;
192	bool			fcmode;
193	bool			ctdev;
194	bool			cna;
195	bool			pllinit;
196	bool			stats_busy;	/*!< outstanding stats */
197	u8			port_id;
198
199	struct bfa_dma		attr_dma;
200	struct bfi_ioc_attr	*attr;
201	struct bfa_ioc_cbfn	*cbfn;
202	struct bfa_ioc_mbox_mod	mbox_mod;
203	struct bfa_ioc_hwif	*ioc_hwif;
204	struct bfa_iocpf	iocpf;
205};
206
207struct bfa_ioc_hwif {
208	enum bfa_status (*ioc_pll_init) (void __iomem *rb, bool fcmode);
209	bool		(*ioc_firmware_lock)	(struct bfa_ioc *ioc);
210	void		(*ioc_firmware_unlock)	(struct bfa_ioc *ioc);
211	void		(*ioc_reg_init)	(struct bfa_ioc *ioc);
212	void		(*ioc_map_port)	(struct bfa_ioc *ioc);
213	void		(*ioc_isr_mode_set)	(struct bfa_ioc *ioc,
214					bool msix);
215	void		(*ioc_notify_fail)	(struct bfa_ioc *ioc);
216	void		(*ioc_ownership_reset)	(struct bfa_ioc *ioc);
217	bool		(*ioc_sync_start)       (struct bfa_ioc *ioc);
218	void		(*ioc_sync_join)	(struct bfa_ioc *ioc);
219	void		(*ioc_sync_leave)	(struct bfa_ioc *ioc);
220	void		(*ioc_sync_ack)		(struct bfa_ioc *ioc);
221	bool		(*ioc_sync_complete)	(struct bfa_ioc *ioc);
222};
223
224#define bfa_ioc_pcifn(__ioc)		((__ioc)->pcidev.pci_func)
225#define bfa_ioc_devid(__ioc)		((__ioc)->pcidev.device_id)
226#define bfa_ioc_bar0(__ioc)		((__ioc)->pcidev.pci_bar_kva)
227#define bfa_ioc_portid(__ioc)		((__ioc)->port_id)
228#define bfa_ioc_fetch_stats(__ioc, __stats) \
229		(((__stats)->drv_stats) = (__ioc)->stats)
230#define bfa_ioc_clr_stats(__ioc)	\
231		memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
232#define bfa_ioc_maxfrsize(__ioc)	((__ioc)->attr->maxfrsize)
233#define bfa_ioc_rx_bbcredit(__ioc)	((__ioc)->attr->rx_bbcredit)
234#define bfa_ioc_speed_sup(__ioc)	\
235	BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
236#define bfa_ioc_get_nports(__ioc)	\
237	BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
238
239#define bfa_ioc_stats(_ioc, _stats)	((_ioc)->stats._stats++)
240#define bfa_ioc_stats_hb_count(_ioc, _hb_count)	\
241	((_ioc)->stats.hb_count = (_hb_count))
242#define BFA_IOC_FWIMG_MINSZ	(16 * 1024)
243#define BFA_IOC_FWIMG_TYPE(__ioc)					\
244	(((__ioc)->ctdev) ?						\
245	 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) :	\
246	 BFI_IMAGE_CB_FC)
247#define BFA_IOC_FW_SMEM_SIZE(__ioc)					\
248	(((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
249#define BFA_IOC_FLASH_CHUNK_NO(off)		(off / BFI_FLASH_CHUNK_SZ_WORDS)
250#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off)	(off % BFI_FLASH_CHUNK_SZ_WORDS)
251#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno)  (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
252
253/**
254 * IOC mailbox interface
255 */
256void bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd);
257void bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc);
258void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
259		bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
260
261/**
262 * IOC interfaces
263 */
264
265#define bfa_ioc_pll_init_asic(__ioc) \
266	((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
267			   (__ioc)->fcmode))
268
269#define	bfa_ioc_isr_mode_set(__ioc, __msix)			\
270			((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
271#define	bfa_ioc_ownership_reset(__ioc)				\
272			((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
273
274void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
275
276void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,
277		struct bfa_ioc_cbfn *cbfn);
278void bfa_nw_ioc_auto_recover(bool auto_recover);
279void bfa_nw_ioc_detach(struct bfa_ioc *ioc);
280void bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
281		enum bfi_mclass mc);
282u32 bfa_nw_ioc_meminfo(void);
283void bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc,  u8 *dm_kva, u64 dm_pa);
284void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
285void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
286
287void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
288bool bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc);
289void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
290void bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
291	struct bfa_ioc_notify *notify);
292bool bfa_nw_ioc_sem_get(void __iomem *sem_reg);
293void bfa_nw_ioc_sem_release(void __iomem *sem_reg);
294void bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc);
295void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
296			struct bfi_ioc_image_hdr *fwhdr);
297bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
298			struct bfi_ioc_image_hdr *fwhdr);
299mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
300
301/*
302 * Timeout APIs
303 */
304void bfa_nw_ioc_timeout(void *ioc);
305void bfa_nw_ioc_hb_check(void *ioc);
306void bfa_nw_iocpf_timeout(void *ioc);
307void bfa_nw_iocpf_sem_timeout(void *ioc);
308
309/*
310 * F/W Image Size & Chunk
311 */
312u32 *bfa_cb_image_get_chunk(int type, u32 off);
313u32 bfa_cb_image_get_size(int type);
314
315#endif /* __BFA_IOC_H__ */