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1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef ATL1_H
25#define ATL1_H
26
27#include <linux/compiler.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
30#include <linux/mii.h>
31#include <linux/module.h>
32#include <linux/skbuff.h>
33#include <linux/spinlock.h>
34#include <linux/timer.h>
35#include <linux/types.h>
36#include <linux/workqueue.h>
37
38#include "atlx.h"
39
40#define ATLX_DRIVER_NAME "atl1"
41
42MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
43
44#define atlx_adapter atl1_adapter
45#define atlx_check_for_link atl1_check_for_link
46#define atlx_check_link atl1_check_link
47#define atlx_hash_mc_addr atl1_hash_mc_addr
48#define atlx_hash_set atl1_hash_set
49#define atlx_hw atl1_hw
50#define atlx_mii_ioctl atl1_mii_ioctl
51#define atlx_read_phy_reg atl1_read_phy_reg
52#define atlx_set_mac atl1_set_mac
53#define atlx_set_mac_addr atl1_set_mac_addr
54
55struct atl1_adapter;
56struct atl1_hw;
57
58/* function prototypes needed by multiple files */
59static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
60static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
61static void atl1_set_mac_addr(struct atl1_hw *hw);
62static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
63 int cmd);
64static u32 atl1_check_link(struct atl1_adapter *adapter);
65
66/* hardware definitions specific to L1 */
67
68/* Block IDLE Status Register */
69#define IDLE_STATUS_RXMAC 0x1
70#define IDLE_STATUS_TXMAC 0x2
71#define IDLE_STATUS_RXQ 0x4
72#define IDLE_STATUS_TXQ 0x8
73#define IDLE_STATUS_DMAR 0x10
74#define IDLE_STATUS_DMAW 0x20
75#define IDLE_STATUS_SMB 0x40
76#define IDLE_STATUS_CMB 0x80
77
78/* MDIO Control Register */
79#define MDIO_WAIT_TIMES 30
80
81/* MAC Control Register */
82#define MAC_CTRL_TX_PAUSE 0x10000
83#define MAC_CTRL_SCNT 0x20000
84#define MAC_CTRL_SRST_TX 0x40000
85#define MAC_CTRL_TX_SIMURST 0x80000
86#define MAC_CTRL_SPEED_SHIFT 20
87#define MAC_CTRL_SPEED_MASK 0x300000
88#define MAC_CTRL_SPEED_1000 0x2
89#define MAC_CTRL_SPEED_10_100 0x1
90#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
91#define MAC_CTRL_TX_HUGE 0x800000
92#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
93#define MAC_CTRL_DBG 0x8000000
94
95/* Wake-On-Lan control register */
96#define WOL_CLK_SWITCH_EN 0x8000
97#define WOL_PT5_EN 0x200000
98#define WOL_PT6_EN 0x400000
99#define WOL_PT5_MATCH 0x8000000
100#define WOL_PT6_MATCH 0x10000000
101
102/* WOL Length ( 2 DWORD ) */
103#define REG_WOL_PATTERN_LEN 0x14A4
104#define WOL_PT_LEN_MASK 0x7F
105#define WOL_PT0_LEN_SHIFT 0
106#define WOL_PT1_LEN_SHIFT 8
107#define WOL_PT2_LEN_SHIFT 16
108#define WOL_PT3_LEN_SHIFT 24
109#define WOL_PT4_LEN_SHIFT 0
110#define WOL_PT5_LEN_SHIFT 8
111#define WOL_PT6_LEN_SHIFT 16
112
113/* Internal SRAM Partition Registers, low 32 bits */
114#define REG_SRAM_RFD_LEN 0x1504
115#define REG_SRAM_RRD_ADDR 0x1508
116#define REG_SRAM_RRD_LEN 0x150C
117#define REG_SRAM_TPD_ADDR 0x1510
118#define REG_SRAM_TPD_LEN 0x1514
119#define REG_SRAM_TRD_ADDR 0x1518
120#define REG_SRAM_TRD_LEN 0x151C
121#define REG_SRAM_RXF_ADDR 0x1520
122#define REG_SRAM_RXF_LEN 0x1524
123#define REG_SRAM_TXF_ADDR 0x1528
124#define REG_SRAM_TXF_LEN 0x152C
125#define REG_SRAM_TCPH_PATH_ADDR 0x1530
126#define SRAM_TCPH_ADDR_MASK 0xFFF
127#define SRAM_TCPH_ADDR_SHIFT 0
128#define SRAM_PATH_ADDR_MASK 0xFFF
129#define SRAM_PATH_ADDR_SHIFT 16
130
131/* Load Ptr Register */
132#define REG_LOAD_PTR 0x1534
133
134/* Descriptor Control registers, low 32 bits */
135#define REG_DESC_RFD_ADDR_LO 0x1544
136#define REG_DESC_RRD_ADDR_LO 0x1548
137#define REG_DESC_TPD_ADDR_LO 0x154C
138#define REG_DESC_CMB_ADDR_LO 0x1550
139#define REG_DESC_SMB_ADDR_LO 0x1554
140#define REG_DESC_RFD_RRD_RING_SIZE 0x1558
141#define DESC_RFD_RING_SIZE_MASK 0x7FF
142#define DESC_RFD_RING_SIZE_SHIFT 0
143#define DESC_RRD_RING_SIZE_MASK 0x7FF
144#define DESC_RRD_RING_SIZE_SHIFT 16
145#define REG_DESC_TPD_RING_SIZE 0x155C
146#define DESC_TPD_RING_SIZE_MASK 0x3FF
147#define DESC_TPD_RING_SIZE_SHIFT 0
148
149/* TXQ Control Register */
150#define REG_TXQ_CTRL 0x1580
151#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
152#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
153#define TXQ_CTRL_EN 0x20
154#define TXQ_CTRL_ENH_MODE 0x40
155#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
156#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
157#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
158#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
159
160/* Jumbo packet Threshold for task offload */
161#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
162#define TX_JUMBO_TASK_TH_MASK 0x7FF
163#define TX_JUMBO_TASK_TH_SHIFT 0
164#define TX_TPD_MIN_IPG_MASK 0x1F
165#define TX_TPD_MIN_IPG_SHIFT 16
166
167/* RXQ Control Register */
168#define REG_RXQ_CTRL 0x15A0
169#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
170#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
171#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
172#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
173#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
174#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
175#define RXQ_CTRL_CUT_THRU_EN 0x40000000
176#define RXQ_CTRL_EN 0x80000000
177
178/* Rx jumbo packet threshold and rrd retirement timer */
179#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
180#define RXQ_JMBOSZ_TH_MASK 0x7FF
181#define RXQ_JMBOSZ_TH_SHIFT 0
182#define RXQ_JMBO_LKAH_MASK 0xF
183#define RXQ_JMBO_LKAH_SHIFT 11
184#define RXQ_RRD_TIMER_MASK 0xFFFF
185#define RXQ_RRD_TIMER_SHIFT 16
186
187/* RFD flow control register */
188#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
189#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
190#define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
191#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
192#define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
193
194/* RRD flow control register */
195#define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
196#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
197#define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
198#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
199#define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
200
201/* DMA Engine Control Register */
202#define REG_DMA_CTRL 0x15C0
203#define DMA_CTRL_DMAR_IN_ORDER 0x1
204#define DMA_CTRL_DMAR_ENH_ORDER 0x2
205#define DMA_CTRL_DMAR_OUT_ORDER 0x4
206#define DMA_CTRL_RCB_VALUE 0x8
207#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
208#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
209#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
210#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
211#define DMA_CTRL_DMAR_EN 0x400
212#define DMA_CTRL_DMAW_EN 0x800
213
214/* CMB/SMB Control Register */
215#define REG_CSMB_CTRL 0x15D0
216#define CSMB_CTRL_CMB_NOW 1
217#define CSMB_CTRL_SMB_NOW 2
218#define CSMB_CTRL_CMB_EN 4
219#define CSMB_CTRL_SMB_EN 8
220
221/* CMB DMA Write Threshold Register */
222#define REG_CMB_WRITE_TH 0x15D4
223#define CMB_RRD_TH_SHIFT 0
224#define CMB_RRD_TH_MASK 0x7FF
225#define CMB_TPD_TH_SHIFT 16
226#define CMB_TPD_TH_MASK 0x7FF
227
228/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
229#define REG_CMB_WRITE_TIMER 0x15D8
230#define CMB_RX_TM_SHIFT 0
231#define CMB_RX_TM_MASK 0xFFFF
232#define CMB_TX_TM_SHIFT 16
233#define CMB_TX_TM_MASK 0xFFFF
234
235/* Number of packet received since last CMB write */
236#define REG_CMB_RX_PKT_CNT 0x15DC
237
238/* Number of packet transmitted since last CMB write */
239#define REG_CMB_TX_PKT_CNT 0x15E0
240
241/* SMB auto DMA timer register */
242#define REG_SMB_TIMER 0x15E4
243
244/* Mailbox Register */
245#define REG_MAILBOX 0x15F0
246#define MB_RFD_PROD_INDX_SHIFT 0
247#define MB_RFD_PROD_INDX_MASK 0x7FF
248#define MB_RRD_CONS_INDX_SHIFT 11
249#define MB_RRD_CONS_INDX_MASK 0x7FF
250#define MB_TPD_PROD_INDX_SHIFT 22
251#define MB_TPD_PROD_INDX_MASK 0x3FF
252
253/* Interrupt Status Register */
254#define ISR_SMB 0x1
255#define ISR_TIMER 0x2
256#define ISR_MANUAL 0x4
257#define ISR_RXF_OV 0x8
258#define ISR_RFD_UNRUN 0x10
259#define ISR_RRD_OV 0x20
260#define ISR_TXF_UNRUN 0x40
261#define ISR_LINK 0x80
262#define ISR_HOST_RFD_UNRUN 0x100
263#define ISR_HOST_RRD_OV 0x200
264#define ISR_DMAR_TO_RST 0x400
265#define ISR_DMAW_TO_RST 0x800
266#define ISR_GPHY 0x1000
267#define ISR_RX_PKT 0x10000
268#define ISR_TX_PKT 0x20000
269#define ISR_TX_DMA 0x40000
270#define ISR_RX_DMA 0x80000
271#define ISR_CMB_RX 0x100000
272#define ISR_CMB_TX 0x200000
273#define ISR_MAC_RX 0x400000
274#define ISR_MAC_TX 0x800000
275#define ISR_DIS_SMB 0x20000000
276#define ISR_DIS_DMA 0x40000000
277
278/* Normal Interrupt mask */
279#define IMR_NORMAL_MASK (\
280 ISR_SMB |\
281 ISR_GPHY |\
282 ISR_PHY_LINKDOWN|\
283 ISR_DMAR_TO_RST |\
284 ISR_DMAW_TO_RST |\
285 ISR_CMB_TX |\
286 ISR_CMB_RX)
287
288/* Debug Interrupt Mask (enable all interrupt) */
289#define IMR_DEBUG_MASK (\
290 ISR_SMB |\
291 ISR_TIMER |\
292 ISR_MANUAL |\
293 ISR_RXF_OV |\
294 ISR_RFD_UNRUN |\
295 ISR_RRD_OV |\
296 ISR_TXF_UNRUN |\
297 ISR_LINK |\
298 ISR_CMB_TX |\
299 ISR_CMB_RX |\
300 ISR_RX_PKT |\
301 ISR_TX_PKT |\
302 ISR_MAC_RX |\
303 ISR_MAC_TX)
304
305#define MEDIA_TYPE_1000M_FULL 1
306#define MEDIA_TYPE_100M_FULL 2
307#define MEDIA_TYPE_100M_HALF 3
308#define MEDIA_TYPE_10M_FULL 4
309#define MEDIA_TYPE_10M_HALF 5
310
311#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
312
313#define MAX_JUMBO_FRAME_SIZE 10240
314
315#define ATL1_EEDUMP_LEN 48
316
317/* Statistics counters collected by the MAC */
318struct stats_msg_block {
319 /* rx */
320 u32 rx_ok; /* good RX packets */
321 u32 rx_bcast; /* good RX broadcast packets */
322 u32 rx_mcast; /* good RX multicast packets */
323 u32 rx_pause; /* RX pause frames */
324 u32 rx_ctrl; /* RX control packets other than pause frames */
325 u32 rx_fcs_err; /* RX packets with bad FCS */
326 u32 rx_len_err; /* RX packets with length != actual size */
327 u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
328 u32 rx_runt; /* RX packets < 64 bytes with good FCS */
329 u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
330 u32 rx_sz_64; /* 64 byte RX packets */
331 u32 rx_sz_65_127;
332 u32 rx_sz_128_255;
333 u32 rx_sz_256_511;
334 u32 rx_sz_512_1023;
335 u32 rx_sz_1024_1518;
336 u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
337 u32 rx_sz_ov; /* truncated RX packets > MTU */
338 u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
339 u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
340 u32 rx_align_err; /* alignment errors */
341 u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
342 u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
343 u32 rx_err_addr; /* packets dropped due to address filtering */
344
345 /* tx */
346 u32 tx_ok; /* good TX packets */
347 u32 tx_bcast; /* good TX broadcast packets */
348 u32 tx_mcast; /* good TX multicast packets */
349 u32 tx_pause; /* TX pause frames */
350 u32 tx_exc_defer; /* TX packets deferred excessively */
351 u32 tx_ctrl; /* TX control frames, excluding pause frames */
352 u32 tx_defer; /* TX packets deferred */
353 u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
354 u32 tx_sz_64; /* 64 byte TX packets */
355 u32 tx_sz_65_127;
356 u32 tx_sz_128_255;
357 u32 tx_sz_256_511;
358 u32 tx_sz_512_1023;
359 u32 tx_sz_1024_1518;
360 u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
361 u32 tx_1_col; /* packets TX after a single collision */
362 u32 tx_2_col; /* packets TX after multiple collisions */
363 u32 tx_late_col; /* TX packets with late collisions */
364 u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
365 u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
366 * or TRD FIFO underrun */
367 u32 tx_rd_eop; /* reads beyond the EOP into the next frame
368 * when TRD was not written timely */
369 u32 tx_len_err; /* TX packets where length != actual size */
370 u32 tx_trunc; /* TX packets truncated due to size > MTU */
371 u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
372 u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
373 u32 smb_updated; /* 1: SMB Updated. This is used by software to
374 * indicate the statistics update. Software
375 * should clear this bit after retrieving the
376 * statistics information. */
377};
378
379/* Coalescing Message Block */
380struct coals_msg_block {
381 u32 int_stats; /* interrupt status */
382 u16 rrd_prod_idx; /* TRD Producer Index. */
383 u16 rfd_cons_idx; /* RFD Consumer Index. */
384 u16 update; /* Selene sets this bit every time it DMAs the
385 * CMB to host memory. Software should clear
386 * this bit when CMB info is processed. */
387 u16 tpd_cons_idx; /* TPD Consumer Index. */
388};
389
390/* RRD descriptor */
391struct rx_return_desc {
392 u8 num_buf; /* Number of RFD buffers used by the received packet */
393 u8 resved;
394 u16 buf_indx; /* RFD Index of the first buffer */
395 union {
396 u32 valid;
397 struct {
398 u16 rx_chksum;
399 u16 pkt_size;
400 } xsum_sz;
401 } xsz;
402
403 u16 pkt_flg; /* Packet flags */
404 u16 err_flg; /* Error flags */
405 u16 resved2;
406 u16 vlan_tag; /* VLAN TAG */
407};
408
409#define PACKET_FLAG_ETH_TYPE 0x0080
410#define PACKET_FLAG_VLAN_INS 0x0100
411#define PACKET_FLAG_ERR 0x0200
412#define PACKET_FLAG_IPV4 0x0400
413#define PACKET_FLAG_UDP 0x0800
414#define PACKET_FLAG_TCP 0x1000
415#define PACKET_FLAG_BCAST 0x2000
416#define PACKET_FLAG_MCAST 0x4000
417#define PACKET_FLAG_PAUSE 0x8000
418
419#define ERR_FLAG_CRC 0x0001
420#define ERR_FLAG_CODE 0x0002
421#define ERR_FLAG_DRIBBLE 0x0004
422#define ERR_FLAG_RUNT 0x0008
423#define ERR_FLAG_OV 0x0010
424#define ERR_FLAG_TRUNC 0x0020
425#define ERR_FLAG_IP_CHKSUM 0x0040
426#define ERR_FLAG_L4_CHKSUM 0x0080
427#define ERR_FLAG_LEN 0x0100
428#define ERR_FLAG_DES_ADDR 0x0200
429
430/* RFD descriptor */
431struct rx_free_desc {
432 __le64 buffer_addr; /* Address of the descriptor's data buffer */
433 __le16 buf_len; /* Size of the receive buffer in host memory */
434 u16 coalese; /* Update consumer index to host after the
435 * reception of this frame */
436 /* __packed is required */
437} __packed;
438
439/*
440 * The L1 transmit packet descriptor is comprised of four 32-bit words.
441 *
442 * 31 0
443 * +---------------------------------------+
444 * | Word 0: Buffer addr lo |
445 * +---------------------------------------+
446 * | Word 1: Buffer addr hi |
447 * +---------------------------------------+
448 * | Word 2 |
449 * +---------------------------------------+
450 * | Word 3 |
451 * +---------------------------------------+
452 *
453 * Words 0 and 1 combine to form a 64-bit buffer address.
454 *
455 * Word 2 is self explanatory in the #define block below.
456 *
457 * Word 3 has two forms, depending upon the state of bits 3 and 4.
458 * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
459 * hardware. Otherwise, if either bit 3 or 4 is set, the definition
460 * of bits 14:31 vary according to the following depiction.
461 *
462 * 0 End of packet 0 End of packet
463 * 1 Coalesce 1 Coalesce
464 * 2 Insert VLAN tag 2 Insert VLAN tag
465 * 3 Custom csum enable = 0 3 Custom csum enable = 1
466 * 4 Segment enable = 1 4 Segment enable = 0
467 * 5 Generate IP checksum 5 Generate IP checksum
468 * 6 Generate TCP checksum 6 Generate TCP checksum
469 * 7 Generate UDP checksum 7 Generate UDP checksum
470 * 8 VLAN tagged 8 VLAN tagged
471 * 9 Ethernet frame type 9 Ethernet frame type
472 * 10-+ 10-+
473 * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
474 * 12 | (num 32-bit words) 12 | (num 32-bit words)
475 * 13-+ 13-+
476 * 14-+ 14 Unused
477 * 15 | TCP hdr length (14:17) 15 Unused
478 * 16 | (num 32-bit words) 16-+
479 * 17-+ 17 |
480 * 18 Header TPD flag 18 |
481 * 19-+ 19 | Payload offset
482 * 20 | 20 | (16:23)
483 * 21 | 21 |
484 * 22 | 22 |
485 * 23 | 23-+
486 * 24 | 24-+
487 * 25 | MSS (19:31) 25 |
488 * 26 | 26 |
489 * 27 | 27 | Custom csum offset
490 * 28 | 28 | (24:31)
491 * 29 | 29 |
492 * 30 | 30 |
493 * 31-+ 31-+
494 */
495
496/* tpd word 2 */
497#define TPD_BUFLEN_MASK 0x3FFF
498#define TPD_BUFLEN_SHIFT 0
499#define TPD_DMAINT_MASK 0x0001
500#define TPD_DMAINT_SHIFT 14
501#define TPD_PKTNT_MASK 0x0001
502#define TPD_PKTINT_SHIFT 15
503#define TPD_VLANTAG_MASK 0xFFFF
504#define TPD_VLANTAG_SHIFT 16
505
506/* tpd word 3 bits 0:13 */
507#define TPD_EOP_MASK 0x0001
508#define TPD_EOP_SHIFT 0
509#define TPD_COALESCE_MASK 0x0001
510#define TPD_COALESCE_SHIFT 1
511#define TPD_INS_VL_TAG_MASK 0x0001
512#define TPD_INS_VL_TAG_SHIFT 2
513#define TPD_CUST_CSUM_EN_MASK 0x0001
514#define TPD_CUST_CSUM_EN_SHIFT 3
515#define TPD_SEGMENT_EN_MASK 0x0001
516#define TPD_SEGMENT_EN_SHIFT 4
517#define TPD_IP_CSUM_MASK 0x0001
518#define TPD_IP_CSUM_SHIFT 5
519#define TPD_TCP_CSUM_MASK 0x0001
520#define TPD_TCP_CSUM_SHIFT 6
521#define TPD_UDP_CSUM_MASK 0x0001
522#define TPD_UDP_CSUM_SHIFT 7
523#define TPD_VL_TAGGED_MASK 0x0001
524#define TPD_VL_TAGGED_SHIFT 8
525#define TPD_ETHTYPE_MASK 0x0001
526#define TPD_ETHTYPE_SHIFT 9
527#define TPD_IPHL_MASK 0x000F
528#define TPD_IPHL_SHIFT 10
529
530/* tpd word 3 bits 14:31 if segment enabled */
531#define TPD_TCPHDRLEN_MASK 0x000F
532#define TPD_TCPHDRLEN_SHIFT 14
533#define TPD_HDRFLAG_MASK 0x0001
534#define TPD_HDRFLAG_SHIFT 18
535#define TPD_MSS_MASK 0x1FFF
536#define TPD_MSS_SHIFT 19
537
538/* tpd word 3 bits 16:31 if custom csum enabled */
539#define TPD_PLOADOFFSET_MASK 0x00FF
540#define TPD_PLOADOFFSET_SHIFT 16
541#define TPD_CCSUMOFFSET_MASK 0x00FF
542#define TPD_CCSUMOFFSET_SHIFT 24
543
544struct tx_packet_desc {
545 __le64 buffer_addr;
546 __le32 word2;
547 __le32 word3;
548};
549
550/* DMA Order Settings */
551enum atl1_dma_order {
552 atl1_dma_ord_in = 1,
553 atl1_dma_ord_enh = 2,
554 atl1_dma_ord_out = 4
555};
556
557enum atl1_dma_rcb {
558 atl1_rcb_64 = 0,
559 atl1_rcb_128 = 1
560};
561
562enum atl1_dma_req_block {
563 atl1_dma_req_128 = 0,
564 atl1_dma_req_256 = 1,
565 atl1_dma_req_512 = 2,
566 atl1_dma_req_1024 = 3,
567 atl1_dma_req_2048 = 4,
568 atl1_dma_req_4096 = 5
569};
570
571#define ATL1_MAX_INTR 3
572#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
573
574#define ATL1_DEFAULT_TPD 256
575#define ATL1_MAX_TPD 1024
576#define ATL1_MIN_TPD 64
577#define ATL1_DEFAULT_RFD 512
578#define ATL1_MIN_RFD 128
579#define ATL1_MAX_RFD 2048
580#define ATL1_REG_COUNT 1538
581
582#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
583#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
584#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
585#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
586
587/*
588 * atl1_ring_header represents a single, contiguous block of DMA space
589 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
590 * message blocks (cmb, smb) described below
591 */
592struct atl1_ring_header {
593 void *desc; /* virtual address */
594 dma_addr_t dma; /* physical address*/
595 unsigned int size; /* length in bytes */
596};
597
598/*
599 * atl1_buffer is wrapper around a pointer to a socket buffer
600 * so a DMA handle can be stored along with the skb
601 */
602struct atl1_buffer {
603 struct sk_buff *skb; /* socket buffer */
604 u16 length; /* rx buffer length */
605 u16 alloced; /* 1 if skb allocated */
606 dma_addr_t dma;
607};
608
609/* transmit packet descriptor (tpd) ring */
610struct atl1_tpd_ring {
611 void *desc; /* descriptor ring virtual address */
612 dma_addr_t dma; /* descriptor ring physical address */
613 u16 size; /* descriptor ring length in bytes */
614 u16 count; /* number of descriptors in the ring */
615 u16 hw_idx; /* hardware index */
616 atomic_t next_to_clean;
617 atomic_t next_to_use;
618 struct atl1_buffer *buffer_info;
619};
620
621/* receive free descriptor (rfd) ring */
622struct atl1_rfd_ring {
623 void *desc; /* descriptor ring virtual address */
624 dma_addr_t dma; /* descriptor ring physical address */
625 u16 size; /* descriptor ring length in bytes */
626 u16 count; /* number of descriptors in the ring */
627 atomic_t next_to_use;
628 u16 next_to_clean;
629 struct atl1_buffer *buffer_info;
630};
631
632/* receive return descriptor (rrd) ring */
633struct atl1_rrd_ring {
634 void *desc; /* descriptor ring virtual address */
635 dma_addr_t dma; /* descriptor ring physical address */
636 unsigned int size; /* descriptor ring length in bytes */
637 u16 count; /* number of descriptors in the ring */
638 u16 next_to_use;
639 atomic_t next_to_clean;
640};
641
642/* coalescing message block (cmb) */
643struct atl1_cmb {
644 struct coals_msg_block *cmb;
645 dma_addr_t dma;
646};
647
648/* statistics message block (smb) */
649struct atl1_smb {
650 struct stats_msg_block *smb;
651 dma_addr_t dma;
652};
653
654/* Statistics counters */
655struct atl1_sft_stats {
656 u64 rx_packets;
657 u64 tx_packets;
658 u64 rx_bytes;
659 u64 tx_bytes;
660 u64 multicast;
661 u64 collisions;
662 u64 rx_errors;
663 u64 rx_length_errors;
664 u64 rx_crc_errors;
665 u64 rx_frame_errors;
666 u64 rx_fifo_errors;
667 u64 rx_missed_errors;
668 u64 tx_errors;
669 u64 tx_fifo_errors;
670 u64 tx_aborted_errors;
671 u64 tx_window_errors;
672 u64 tx_carrier_errors;
673 u64 tx_pause; /* TX pause frames */
674 u64 excecol; /* TX packets w/ excessive collisions */
675 u64 deffer; /* TX packets deferred */
676 u64 scc; /* packets TX after a single collision */
677 u64 mcc; /* packets TX after multiple collisions */
678 u64 latecol; /* TX packets w/ late collisions */
679 u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
680 * or TRD FIFO underrun */
681 u64 tx_trunc; /* TX packets truncated due to size > MTU */
682 u64 rx_pause; /* num Pause packets received. */
683 u64 rx_rrd_ov;
684 u64 rx_trunc;
685};
686
687/* hardware structure */
688struct atl1_hw {
689 u8 __iomem *hw_addr;
690 struct atl1_adapter *back;
691 enum atl1_dma_order dma_ord;
692 enum atl1_dma_rcb rcb_value;
693 enum atl1_dma_req_block dmar_block;
694 enum atl1_dma_req_block dmaw_block;
695 u8 preamble_len;
696 u8 max_retry;
697 u8 jam_ipg; /* IPG to start JAM for collision based flow
698 * control in half-duplex mode. In units of
699 * 8-bit time */
700 u8 ipgt; /* Desired back to back inter-packet gap.
701 * The default is 96-bit time */
702 u8 min_ifg; /* Minimum number of IFG to enforce in between
703 * receive frames. Frame gap below such IFP
704 * is dropped */
705 u8 ipgr1; /* 64bit Carrier-Sense window */
706 u8 ipgr2; /* 96-bit IPG window */
707 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
708 * burst. Each TPD is 16 bytes long */
709 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
710 * burst. Each RFD is 12 bytes long */
711 u8 rfd_fetch_gap;
712 u8 rrd_burst; /* Threshold number of RRDs that can be retired
713 * in a burst. Each RRD is 16 bytes long */
714 u8 tpd_fetch_th;
715 u8 tpd_fetch_gap;
716 u16 tx_jumbo_task_th;
717 u16 txf_burst; /* Number of data bytes to read in a cache-
718 * aligned burst. Each SRAM entry is 8 bytes */
719 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
720 * packets should add 4 bytes */
721 u16 rx_jumbo_lkah;
722 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
723 * every 512ns passes. */
724 u16 lcol; /* Collision Window */
725
726 u16 cmb_tpd;
727 u16 cmb_rrd;
728 u16 cmb_rx_timer;
729 u16 cmb_tx_timer;
730 u32 smb_timer;
731 u16 media_type;
732 u16 autoneg_advertised;
733
734 u16 mii_autoneg_adv_reg;
735 u16 mii_1000t_ctrl_reg;
736
737 u32 max_frame_size;
738 u32 min_frame_size;
739
740 u16 dev_rev;
741
742 /* spi flash */
743 u8 flash_vendor;
744
745 u8 mac_addr[ETH_ALEN];
746 u8 perm_mac_addr[ETH_ALEN];
747
748 bool phy_configured;
749};
750
751struct atl1_adapter {
752 struct net_device *netdev;
753 struct pci_dev *pdev;
754
755 struct atl1_sft_stats soft_stats;
756 u32 rx_buffer_len;
757 u32 wol;
758 u16 link_speed;
759 u16 link_duplex;
760 spinlock_t lock;
761 struct work_struct tx_timeout_task;
762 struct work_struct link_chg_task;
763 struct work_struct pcie_dma_to_rst_task;
764
765 struct timer_list phy_config_timer;
766 bool phy_timer_pending;
767
768 /* all descriptor rings' memory */
769 struct atl1_ring_header ring_header;
770
771 /* TX */
772 struct atl1_tpd_ring tpd_ring;
773 spinlock_t mb_lock;
774
775 /* RX */
776 struct atl1_rfd_ring rfd_ring;
777 struct atl1_rrd_ring rrd_ring;
778 u64 hw_csum_err;
779 u64 hw_csum_good;
780 u32 msg_enable;
781 u16 imt; /* interrupt moderator timer (2us resolution) */
782 u16 ict; /* interrupt clear timer (2us resolution */
783 struct mii_if_info mii; /* MII interface info */
784
785 u32 bd_number; /* board number */
786 bool pci_using_64;
787 struct atl1_hw hw;
788 struct atl1_smb smb;
789 struct atl1_cmb cmb;
790};
791
792#endif /* ATL1_H */