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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI AEMIF driver
4 *
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
6 *
7 * Authors:
8 * Murali Karicheri <m-karicheri2@ti.com>
9 * Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
10 */
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20
21#define TA_SHIFT 2
22#define RHOLD_SHIFT 4
23#define RSTROBE_SHIFT 7
24#define RSETUP_SHIFT 13
25#define WHOLD_SHIFT 17
26#define WSTROBE_SHIFT 20
27#define WSETUP_SHIFT 26
28#define EW_SHIFT 30
29#define SSTROBE_SHIFT 31
30
31#define TA(x) ((x) << TA_SHIFT)
32#define RHOLD(x) ((x) << RHOLD_SHIFT)
33#define RSTROBE(x) ((x) << RSTROBE_SHIFT)
34#define RSETUP(x) ((x) << RSETUP_SHIFT)
35#define WHOLD(x) ((x) << WHOLD_SHIFT)
36#define WSTROBE(x) ((x) << WSTROBE_SHIFT)
37#define WSETUP(x) ((x) << WSETUP_SHIFT)
38#define EW(x) ((x) << EW_SHIFT)
39#define SSTROBE(x) ((x) << SSTROBE_SHIFT)
40
41#define ASIZE_MAX 0x1
42#define TA_MAX 0x3
43#define RHOLD_MAX 0x7
44#define RSTROBE_MAX 0x3f
45#define RSETUP_MAX 0xf
46#define WHOLD_MAX 0x7
47#define WSTROBE_MAX 0x3f
48#define WSETUP_MAX 0xf
49#define EW_MAX 0x1
50#define SSTROBE_MAX 0x1
51#define NUM_CS 4
52
53#define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
54#define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
55#define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
56#define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
57#define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
58#define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
59#define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
60#define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
61#define SSTROBE_VAL(x) (((x) & SSTROBE(SSTROBE_MAX)) >> SSTROBE_SHIFT)
62
63#define NRCSR_OFFSET 0x00
64#define AWCCR_OFFSET 0x04
65#define A1CR_OFFSET 0x10
66
67#define ACR_ASIZE_MASK 0x3
68#define ACR_EW_MASK BIT(30)
69#define ACR_SSTROBE_MASK BIT(31)
70#define ASIZE_16BIT 1
71
72#define CONFIG_MASK (TA(TA_MAX) | \
73 RHOLD(RHOLD_MAX) | \
74 RSTROBE(RSTROBE_MAX) | \
75 RSETUP(RSETUP_MAX) | \
76 WHOLD(WHOLD_MAX) | \
77 WSTROBE(WSTROBE_MAX) | \
78 WSETUP(WSETUP_MAX) | \
79 EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \
80 ASIZE_MAX)
81
82/**
83 * struct aemif_cs_data: structure to hold cs parameters
84 * @cs: chip-select number
85 * @wstrobe: write strobe width, ns
86 * @rstrobe: read strobe width, ns
87 * @wsetup: write setup width, ns
88 * @whold: write hold width, ns
89 * @rsetup: read setup width, ns
90 * @rhold: read hold width, ns
91 * @ta: minimum turn around time, ns
92 * @enable_ss: enable/disable select strobe mode
93 * @enable_ew: enable/disable extended wait mode
94 * @asize: width of the asynchronous device's data bus
95 */
96struct aemif_cs_data {
97 u8 cs;
98 u16 wstrobe;
99 u16 rstrobe;
100 u8 wsetup;
101 u8 whold;
102 u8 rsetup;
103 u8 rhold;
104 u8 ta;
105 u8 enable_ss;
106 u8 enable_ew;
107 u8 asize;
108};
109
110/**
111 * struct aemif_device: structure to hold device data
112 * @base: base address of AEMIF registers
113 * @clk: source clock
114 * @clk_rate: clock's rate in kHz
115 * @num_cs: number of assigned chip-selects
116 * @cs_offset: start number of cs nodes
117 * @cs_data: array of chip-select settings
118 */
119struct aemif_device {
120 void __iomem *base;
121 struct clk *clk;
122 unsigned long clk_rate;
123 u8 num_cs;
124 int cs_offset;
125 struct aemif_cs_data cs_data[NUM_CS];
126};
127
128/**
129 * aemif_calc_rate - calculate timing data.
130 * @pdev: platform device to calculate for
131 * @wanted: The cycle time needed in nanoseconds.
132 * @clk: The input clock rate in kHz.
133 * @max: The maximum divider value that can be programmed.
134 *
135 * On success, returns the calculated timing value minus 1 for easy
136 * programming into AEMIF timing registers, else negative errno.
137 */
138static int aemif_calc_rate(struct platform_device *pdev, int wanted,
139 unsigned long clk, int max)
140{
141 int result;
142
143 result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
144
145 dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result,
146 clk, wanted);
147
148 /* It is generally OK to have a more relaxed timing than requested... */
149 if (result < 0)
150 result = 0;
151
152 /* ... But configuring tighter timings is not an option. */
153 else if (result > max)
154 result = -EINVAL;
155
156 return result;
157}
158
159/**
160 * aemif_config_abus - configure async bus parameters
161 * @pdev: platform device to configure for
162 * @csnum: aemif chip select number
163 *
164 * This function programs the given timing values (in real clock) into the
165 * AEMIF registers taking the AEMIF clock into account.
166 *
167 * This function does not use any locking while programming the AEMIF
168 * because it is expected that there is only one user of a given
169 * chip-select.
170 *
171 * Returns 0 on success, else negative errno.
172 */
173static int aemif_config_abus(struct platform_device *pdev, int csnum)
174{
175 struct aemif_device *aemif = platform_get_drvdata(pdev);
176 struct aemif_cs_data *data = &aemif->cs_data[csnum];
177 int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
178 unsigned long clk_rate = aemif->clk_rate;
179 unsigned offset;
180 u32 set, val;
181
182 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
183
184 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
185 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
186 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
187 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
188 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
189 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
190 wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
191
192 if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
193 whold < 0 || wstrobe < 0 || wsetup < 0) {
194 dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
195 __func__);
196 return -EINVAL;
197 }
198
199 set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
200 WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
201
202 set |= (data->asize & ACR_ASIZE_MASK);
203 if (data->enable_ew)
204 set |= ACR_EW_MASK;
205 if (data->enable_ss)
206 set |= ACR_SSTROBE_MASK;
207
208 val = readl(aemif->base + offset);
209 val &= ~CONFIG_MASK;
210 val |= set;
211 writel(val, aemif->base + offset);
212
213 return 0;
214}
215
216static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
217{
218 return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
219}
220
221/**
222 * aemif_get_hw_params - function to read hw register values
223 * @pdev: platform device to read for
224 * @csnum: aemif chip select number
225 *
226 * This function reads the defaults from the registers and update
227 * the timing values. Required for get/set commands and also for
228 * the case when driver needs to use defaults in hardware.
229 */
230static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
231{
232 struct aemif_device *aemif = platform_get_drvdata(pdev);
233 struct aemif_cs_data *data = &aemif->cs_data[csnum];
234 unsigned long clk_rate = aemif->clk_rate;
235 u32 val, offset;
236
237 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
238 val = readl(aemif->base + offset);
239
240 data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
241 data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
242 data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
243 data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
244 data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
245 data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
246 data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
247 data->enable_ew = EW_VAL(val);
248 data->enable_ss = SSTROBE_VAL(val);
249 data->asize = val & ASIZE_MAX;
250}
251
252/**
253 * of_aemif_parse_abus_config - parse CS configuration from DT
254 * @pdev: platform device to parse for
255 * @np: device node ptr
256 *
257 * This function update the emif async bus configuration based on the values
258 * configured in a cs device binding node.
259 */
260static int of_aemif_parse_abus_config(struct platform_device *pdev,
261 struct device_node *np)
262{
263 struct aemif_device *aemif = platform_get_drvdata(pdev);
264 struct aemif_cs_data *data;
265 u32 cs;
266 u32 val;
267
268 if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) {
269 dev_dbg(&pdev->dev, "cs property is required");
270 return -EINVAL;
271 }
272
273 if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) {
274 dev_dbg(&pdev->dev, "cs number is incorrect %d", cs);
275 return -EINVAL;
276 }
277
278 if (aemif->num_cs >= NUM_CS) {
279 dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS);
280 return -EINVAL;
281 }
282
283 data = &aemif->cs_data[aemif->num_cs];
284 data->cs = cs;
285
286 /* read the current value in the hw register */
287 aemif_get_hw_params(pdev, aemif->num_cs++);
288
289 /* override the values from device node */
290 if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
291 data->ta = val;
292
293 if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
294 data->rhold = val;
295
296 if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
297 data->rstrobe = val;
298
299 if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
300 data->rsetup = val;
301
302 if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
303 data->whold = val;
304
305 if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
306 data->wstrobe = val;
307
308 if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
309 data->wsetup = val;
310
311 if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
312 if (val == 16)
313 data->asize = 1;
314 data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
315 data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
316 return 0;
317}
318
319static const struct of_device_id aemif_of_match[] = {
320 { .compatible = "ti,davinci-aemif", },
321 { .compatible = "ti,da850-aemif", },
322 {},
323};
324MODULE_DEVICE_TABLE(of, aemif_of_match);
325
326static int aemif_probe(struct platform_device *pdev)
327{
328 int i;
329 int ret = -ENODEV;
330 struct device *dev = &pdev->dev;
331 struct device_node *np = dev->of_node;
332 struct aemif_device *aemif;
333
334 aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
335 if (!aemif)
336 return -ENOMEM;
337
338 platform_set_drvdata(pdev, aemif);
339
340 aemif->clk = devm_clk_get_enabled(dev, NULL);
341 if (IS_ERR(aemif->clk))
342 return dev_err_probe(dev, PTR_ERR(aemif->clk),
343 "cannot get clock 'aemif'\n");
344
345 aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
346
347 if (np && of_device_is_compatible(np, "ti,da850-aemif"))
348 aemif->cs_offset = 2;
349
350 aemif->base = devm_platform_ioremap_resource(pdev, 0);
351 if (IS_ERR(aemif->base))
352 return PTR_ERR(aemif->base);
353
354 if (np) {
355 /*
356 * For every controller device node, there is a cs device node
357 * that describe the bus configuration parameters. This
358 * functions iterate over these nodes and update the cs data
359 * array.
360 */
361 for_each_available_child_of_node_scoped(np, child_np) {
362 ret = of_aemif_parse_abus_config(pdev, child_np);
363 if (ret < 0)
364 return ret;
365 }
366 }
367
368 for (i = 0; i < aemif->num_cs; i++) {
369 ret = aemif_config_abus(pdev, i);
370 if (ret < 0) {
371 dev_err(dev, "Error configuring chip select %d\n",
372 aemif->cs_data[i].cs);
373 return ret;
374 }
375 }
376
377 /*
378 * Create a child devices explicitly from here to guarantee that the
379 * child will be probed after the AEMIF timing parameters are set.
380 */
381 if (np) {
382 for_each_available_child_of_node_scoped(np, child_np) {
383 ret = of_platform_populate(child_np, NULL, NULL, dev);
384 if (ret < 0)
385 return ret;
386 }
387 }
388
389 return 0;
390}
391
392static struct platform_driver aemif_driver = {
393 .probe = aemif_probe,
394 .driver = {
395 .name = "ti-aemif",
396 .of_match_table = of_match_ptr(aemif_of_match),
397 },
398};
399
400module_platform_driver(aemif_driver);
401
402MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
403MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
404MODULE_DESCRIPTION("Texas Instruments AEMIF driver");
405MODULE_LICENSE("GPL v2");
406MODULE_ALIAS("platform:" KBUILD_MODNAME);