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1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig MAILBOX
3 bool "Mailbox Hardware Support"
4 help
5 Mailbox is a framework to control hardware communication between
6 on-chip processors through queued messages and interrupt driven
7 signals. Say Y if your platform supports hardware mailboxes.
8
9if MAILBOX
10
11config ARM_MHU
12 tristate "ARM MHU Mailbox"
13 depends on ARM_AMBA
14 help
15 Say Y here if you want to build the ARM MHU controller driver.
16 The controller has 3 mailbox channels, the last of which can be
17 used in Secure mode only.
18
19config ARM_MHU_V2
20 tristate "ARM MHUv2 Mailbox"
21 depends on ARM_AMBA
22 help
23 Say Y here if you want to build the ARM MHUv2 controller driver,
24 which provides unidirectional mailboxes between processing elements.
25
26config ARM_MHU_V3
27 tristate "ARM MHUv3 Mailbox"
28 depends on ARM64 || COMPILE_TEST
29 depends on HAS_IOMEM || COMPILE_TEST
30 depends on OF
31 help
32 Say Y here if you want to build the ARM MHUv3 controller driver,
33 which provides unidirectional mailboxes between processing elements.
34
35 ARM MHUv3 controllers can implement a varying number of extensions
36 that provides different means of transports: supported extensions
37 will be discovered and possibly managed at probe-time.
38
39config IMX_MBOX
40 tristate "i.MX Mailbox"
41 depends on ARCH_MXC || COMPILE_TEST
42 help
43 Mailbox implementation for i.MX Messaging Unit (MU).
44
45config PLATFORM_MHU
46 tristate "Platform MHU Mailbox"
47 depends on OF
48 depends on HAS_IOMEM
49 help
50 Say Y here if you want to build a platform specific variant MHU
51 controller driver.
52 The controller has a maximum of 3 mailbox channels, the last of
53 which can be used in Secure mode only.
54
55config PL320_MBOX
56 bool "ARM PL320 Mailbox"
57 depends on ARM_AMBA
58 help
59 An implementation of the ARM PL320 Interprocessor Communication
60 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
61 send short messages between Highbank's A9 cores and the EnergyCore
62 Management Engine, primarily for cpufreq. Say Y here if you want
63 to use the PL320 IPCM support.
64
65config ARMADA_37XX_RWTM_MBOX
66 tristate "Armada 37xx rWTM BIU Mailbox"
67 depends on ARCH_MVEBU || COMPILE_TEST
68 depends on OF
69 help
70 Mailbox implementation for communication with the the firmware
71 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
72 SOC. Say Y here if you are building for such a device (for example
73 the Turris Mox router).
74
75config OMAP2PLUS_MBOX
76 tristate "OMAP2+ Mailbox framework support"
77 depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
78 help
79 Mailbox implementation for OMAP family chips with hardware for
80 interprocessor communication involving DSP, IVA1.0 and IVA2 in
81 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
82 want to use OMAP2+ Mailbox framework support.
83
84config ROCKCHIP_MBOX
85 bool "Rockchip Soc Integrated Mailbox Support"
86 depends on ARCH_ROCKCHIP || COMPILE_TEST
87 help
88 This driver provides support for inter-processor communication
89 between CPU cores and MCU processor on Some Rockchip SOCs.
90 Please check it that the Soc you use have Mailbox hardware.
91 Say Y here if you want to use the Rockchip Mailbox support.
92
93config PCC
94 bool "Platform Communication Channel Driver"
95 depends on ACPI
96 default n
97 help
98 ACPI 5.0+ spec defines a generic mode of communication
99 between the OS and a platform such as the BMC. This medium
100 (PCC) is typically used by CPPC (ACPI CPU Performance management),
101 RAS (ACPI reliability protocol) and MPST (ACPI Memory power
102 states). Select this driver if your platform implements the
103 PCC clients mentioned above.
104
105config ALTERA_MBOX
106 tristate "Altera Mailbox"
107 depends on HAS_IOMEM
108 help
109 An implementation of the Altera Mailbox soft core. It is used
110 to send message between processors. Say Y here if you want to use the
111 Altera mailbox support.
112
113config BCM2835_MBOX
114 tristate "BCM2835 Mailbox"
115 depends on ARCH_BCM2835
116 help
117 An implementation of the BCM2385 Mailbox. It is used to invoke
118 the services of the Videocore. Say Y here if you want to use the
119 BCM2835 Mailbox.
120
121config STI_MBOX
122 tristate "STI Mailbox framework support"
123 depends on ARCH_STI && OF
124 help
125 Mailbox implementation for STMicroelectonics family chips with
126 hardware for interprocessor communication.
127
128config TI_MESSAGE_MANAGER
129 tristate "Texas Instruments Message Manager Driver"
130 depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
131 default ARCH_K3
132 help
133 An implementation of Message Manager slave driver for Keystone
134 and K3 architecture SoCs from Texas Instruments. Message Manager
135 is a communication entity found on few of Texas Instrument's keystone
136 and K3 architecture SoCs. These may be used for communication between
137 multiple processors within the SoC. Select this driver if your
138 platform has support for the hardware block.
139
140config HI3660_MBOX
141 tristate "Hi3660 Mailbox" if EXPERT
142 depends on (ARCH_HISI || COMPILE_TEST)
143 depends on OF
144 default ARCH_HISI
145 help
146 An implementation of the hi3660 mailbox. It is used to send message
147 between application processors and other processors/MCU/DSP. Select
148 Y here if you want to use Hi3660 mailbox controller.
149
150config HI6220_MBOX
151 tristate "Hi6220 Mailbox" if EXPERT
152 depends on (ARCH_HISI || COMPILE_TEST)
153 depends on OF
154 default ARCH_HISI
155 help
156 An implementation of the hi6220 mailbox. It is used to send message
157 between application processors and MCU. Say Y here if you want to
158 build Hi6220 mailbox controller driver.
159
160config MAILBOX_TEST
161 tristate "Mailbox Test Client"
162 depends on OF
163 depends on HAS_IOMEM
164 help
165 Test client to help with testing new Controller driver
166 implementations.
167
168config POLARFIRE_SOC_MAILBOX
169 tristate "PolarFire SoC (MPFS) Mailbox"
170 depends on HAS_IOMEM
171 depends on MFD_SYSCON
172 depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
173 help
174 This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
175
176 To compile this driver as a module, choose M here. the
177 module will be called mailbox-mpfs.
178
179 If unsure, say N.
180
181config QCOM_APCS_IPC
182 tristate "Qualcomm APCS IPC driver"
183 depends on ARCH_QCOM || COMPILE_TEST
184 help
185 Say y here to enable support for the APCS IPC mailbox driver,
186 providing an interface for invoking the inter-process communication
187 signals from the application processor to other masters.
188
189config TEGRA_HSP_MBOX
190 bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
191 depends on ARCH_TEGRA
192 help
193 The Tegra HSP driver is used for the interprocessor communication
194 between different remote processors and host processors on Tegra186
195 and later SoCs. Say Y here if you want to have this support.
196 If unsure say N.
197
198config XGENE_SLIMPRO_MBOX
199 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
200 depends on ARCH_XGENE
201 help
202 An implementation of the APM X-Gene Interprocessor Communication
203 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
204 It is used to send short messages between ARM64-bit cores and
205 the SLIMpro Management Engine, primarily for PM. Say Y here if you
206 want to use the APM X-Gene SLIMpro IPCM support.
207
208config BCM_PDC_MBOX
209 tristate "Broadcom FlexSparx DMA Mailbox"
210 depends on ARCH_BCM_IPROC || COMPILE_TEST
211 help
212 Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
213 which provides access to various offload engines on Broadcom
214 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
215
216config BCM_FLEXRM_MBOX
217 tristate "Broadcom FlexRM Mailbox"
218 depends on ARM64
219 depends on ARCH_BCM_IPROC || COMPILE_TEST
220 select GENERIC_MSI_IRQ
221 default m if ARCH_BCM_IPROC
222 help
223 Mailbox implementation of the Broadcom FlexRM ring manager,
224 which provides access to various offload engines on Broadcom
225 SoCs. Say Y here if you want to use the Broadcom FlexRM.
226
227config STM32_IPCC
228 tristate "STM32 IPCC Mailbox"
229 depends on MACH_STM32MP157 || COMPILE_TEST
230 help
231 Mailbox implementation for STMicroelectonics STM32 family chips
232 with hardware for Inter-Processor Communication Controller (IPCC)
233 between processors. Say Y here if you want to have this support.
234
235config MTK_ADSP_MBOX
236 tristate "MediaTek ADSP Mailbox Controller"
237 depends on ARCH_MEDIATEK || COMPILE_TEST
238 help
239 Say yes here to add support for "MediaTek ADSP Mailbox Controller.
240 This mailbox driver is used to send notification or short message
241 between processors with ADSP. It will place the message to share
242 buffer and will access the ipc control.
243
244config MTK_CMDQ_MBOX
245 tristate "MediaTek CMDQ Mailbox Support"
246 depends on ARCH_MEDIATEK || COMPILE_TEST
247 select MTK_INFRACFG
248 help
249 Say yes here to add support for the MediaTek Command Queue (CMDQ)
250 mailbox driver. The CMDQ is used to help read/write registers with
251 critical time limitation, such as updating display configuration
252 during the vblank.
253
254config ZYNQMP_IPI_MBOX
255 tristate "Xilinx ZynqMP IPI Mailbox"
256 depends on ARCH_ZYNQMP && OF
257 help
258 Say yes here to add support for Xilinx IPI mailbox driver.
259 This mailbox driver is used to send notification or short message
260 between processors with Xilinx ZynqMP IPI. It will place the
261 message to the IPI buffer and will access the IPI control
262 registers to kick the other processor or enquire status.
263
264config SUN6I_MSGBOX
265 tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
266 depends on ARCH_SUNXI || COMPILE_TEST
267 default ARCH_SUNXI
268 help
269 Mailbox implementation for the hardware message box present in
270 various Allwinner SoCs. This mailbox is used for communication
271 between the application CPUs and the power management coprocessor.
272
273config SPRD_MBOX
274 tristate "Spreadtrum Mailbox"
275 depends on ARCH_SPRD || COMPILE_TEST
276 help
277 Mailbox driver implementation for the Spreadtrum platform. It is used
278 to send message between application processors and MCU. Say Y here if
279 you want to build the Spreatrum mailbox controller driver.
280
281config QCOM_CPUCP_MBOX
282 tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
283 depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT
284 help
285 Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
286 controller driver enables communication between AP and CPUCP. Say
287 Y here if you want to build this driver.
288
289config QCOM_IPCC
290 tristate "Qualcomm Technologies, Inc. IPCC driver"
291 depends on ARCH_QCOM || COMPILE_TEST
292 help
293 Qualcomm Technologies, Inc. Inter-Processor Communication Controller
294 (IPCC) driver for MSM devices. The driver provides mailbox support for
295 sending interrupts to the clients. On the other hand, the driver also
296 acts as an interrupt controller for receiving interrupts from clients.
297 Say Y here if you want to build this driver.
298
299config THEAD_TH1520_MBOX
300 tristate "T-head TH1520 Mailbox"
301 depends on ARCH_THEAD || COMPILE_TEST
302 help
303 Mailbox driver implementation for the Thead TH-1520 platform. Enables
304 two cores within the SoC to communicate and coordinate by passing
305 messages. Could be used to communicate between E910 core, on which the
306 kernel is running, and E902 core used for power management among other
307 things.
308
309endif