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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2020 Linaro Ltd
4 * Author: Georgi Djakov <georgi.djakov@linaro.org>
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect-provider.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14
15#include <dt-bindings/interconnect/qcom,msm8916.h>
16
17#include "icc-rpm.h"
18
19enum {
20 MSM8916_BIMC_SNOC_MAS = 1,
21 MSM8916_BIMC_SNOC_SLV,
22 MSM8916_MASTER_AMPSS_M0,
23 MSM8916_MASTER_LPASS,
24 MSM8916_MASTER_BLSP_1,
25 MSM8916_MASTER_DEHR,
26 MSM8916_MASTER_GRAPHICS_3D,
27 MSM8916_MASTER_JPEG,
28 MSM8916_MASTER_MDP_PORT0,
29 MSM8916_MASTER_CRYPTO_CORE0,
30 MSM8916_MASTER_SDCC_1,
31 MSM8916_MASTER_SDCC_2,
32 MSM8916_MASTER_QDSS_BAM,
33 MSM8916_MASTER_QDSS_ETR,
34 MSM8916_MASTER_SNOC_CFG,
35 MSM8916_MASTER_SPDM,
36 MSM8916_MASTER_TCU0,
37 MSM8916_MASTER_TCU1,
38 MSM8916_MASTER_USB_HS,
39 MSM8916_MASTER_VFE,
40 MSM8916_MASTER_VIDEO_P0,
41 MSM8916_SNOC_MM_INT_0,
42 MSM8916_SNOC_MM_INT_1,
43 MSM8916_SNOC_MM_INT_2,
44 MSM8916_SNOC_MM_INT_BIMC,
45 MSM8916_PNOC_INT_0,
46 MSM8916_PNOC_INT_1,
47 MSM8916_PNOC_MAS_0,
48 MSM8916_PNOC_MAS_1,
49 MSM8916_PNOC_SLV_0,
50 MSM8916_PNOC_SLV_1,
51 MSM8916_PNOC_SLV_2,
52 MSM8916_PNOC_SLV_3,
53 MSM8916_PNOC_SLV_4,
54 MSM8916_PNOC_SLV_8,
55 MSM8916_PNOC_SLV_9,
56 MSM8916_PNOC_SNOC_MAS,
57 MSM8916_PNOC_SNOC_SLV,
58 MSM8916_SNOC_QDSS_INT,
59 MSM8916_SLAVE_AMPSS_L2,
60 MSM8916_SLAVE_APSS,
61 MSM8916_SLAVE_LPASS,
62 MSM8916_SLAVE_BIMC_CFG,
63 MSM8916_SLAVE_BLSP_1,
64 MSM8916_SLAVE_BOOT_ROM,
65 MSM8916_SLAVE_CAMERA_CFG,
66 MSM8916_SLAVE_CATS_128,
67 MSM8916_SLAVE_OCMEM_64,
68 MSM8916_SLAVE_CLK_CTL,
69 MSM8916_SLAVE_CRYPTO_0_CFG,
70 MSM8916_SLAVE_DEHR_CFG,
71 MSM8916_SLAVE_DISPLAY_CFG,
72 MSM8916_SLAVE_EBI_CH0,
73 MSM8916_SLAVE_GRAPHICS_3D_CFG,
74 MSM8916_SLAVE_IMEM_CFG,
75 MSM8916_SLAVE_IMEM,
76 MSM8916_SLAVE_MPM,
77 MSM8916_SLAVE_MSG_RAM,
78 MSM8916_SLAVE_MSS,
79 MSM8916_SLAVE_PDM,
80 MSM8916_SLAVE_PMIC_ARB,
81 MSM8916_SLAVE_PNOC_CFG,
82 MSM8916_SLAVE_PRNG,
83 MSM8916_SLAVE_QDSS_CFG,
84 MSM8916_SLAVE_QDSS_STM,
85 MSM8916_SLAVE_RBCPR_CFG,
86 MSM8916_SLAVE_SDCC_1,
87 MSM8916_SLAVE_SDCC_2,
88 MSM8916_SLAVE_SECURITY,
89 MSM8916_SLAVE_SNOC_CFG,
90 MSM8916_SLAVE_SPDM,
91 MSM8916_SLAVE_SRVC_SNOC,
92 MSM8916_SLAVE_TCSR,
93 MSM8916_SLAVE_TLMM,
94 MSM8916_SLAVE_USB_HS,
95 MSM8916_SLAVE_VENUS_CFG,
96 MSM8916_SNOC_BIMC_0_MAS,
97 MSM8916_SNOC_BIMC_0_SLV,
98 MSM8916_SNOC_BIMC_1_MAS,
99 MSM8916_SNOC_BIMC_1_SLV,
100 MSM8916_SNOC_INT_0,
101 MSM8916_SNOC_INT_1,
102 MSM8916_SNOC_INT_BIMC,
103 MSM8916_SNOC_PNOC_MAS,
104 MSM8916_SNOC_PNOC_SLV,
105};
106
107static const u16 bimc_snoc_mas_links[] = {
108 MSM8916_BIMC_SNOC_SLV
109};
110
111static struct qcom_icc_node bimc_snoc_mas = {
112 .name = "bimc_snoc_mas",
113 .id = MSM8916_BIMC_SNOC_MAS,
114 .buswidth = 8,
115 .mas_rpm_id = -1,
116 .slv_rpm_id = -1,
117 .qos.ap_owned = true,
118 .qos.qos_mode = NOC_QOS_MODE_INVALID,
119 .num_links = ARRAY_SIZE(bimc_snoc_mas_links),
120 .links = bimc_snoc_mas_links,
121};
122
123static const u16 bimc_snoc_slv_links[] = {
124 MSM8916_SNOC_INT_0,
125 MSM8916_SNOC_INT_1
126};
127
128static struct qcom_icc_node bimc_snoc_slv = {
129 .name = "bimc_snoc_slv",
130 .id = MSM8916_BIMC_SNOC_SLV,
131 .buswidth = 8,
132 .mas_rpm_id = -1,
133 .slv_rpm_id = -1,
134 .qos.ap_owned = true,
135 .qos.qos_mode = NOC_QOS_MODE_INVALID,
136 .num_links = ARRAY_SIZE(bimc_snoc_slv_links),
137 .links = bimc_snoc_slv_links,
138};
139
140static const u16 mas_apss_links[] = {
141 MSM8916_SLAVE_EBI_CH0,
142 MSM8916_BIMC_SNOC_MAS,
143 MSM8916_SLAVE_AMPSS_L2
144};
145
146static struct qcom_icc_node mas_apss = {
147 .name = "mas_apss",
148 .id = MSM8916_MASTER_AMPSS_M0,
149 .buswidth = 8,
150 .mas_rpm_id = -1,
151 .slv_rpm_id = -1,
152 .qos.ap_owned = true,
153 .qos.qos_mode = NOC_QOS_MODE_FIXED,
154 .qos.areq_prio = 0,
155 .qos.prio_level = 0,
156 .qos.qos_port = 0,
157 .num_links = ARRAY_SIZE(mas_apss_links),
158 .links = mas_apss_links,
159};
160
161static const u16 mas_audio_links[] = {
162 MSM8916_PNOC_MAS_0
163};
164
165static struct qcom_icc_node mas_audio = {
166 .name = "mas_audio",
167 .id = MSM8916_MASTER_LPASS,
168 .buswidth = 4,
169 .mas_rpm_id = -1,
170 .slv_rpm_id = -1,
171 .num_links = ARRAY_SIZE(mas_audio_links),
172 .links = mas_audio_links,
173};
174
175static const u16 mas_blsp_1_links[] = {
176 MSM8916_PNOC_MAS_1
177};
178
179static struct qcom_icc_node mas_blsp_1 = {
180 .name = "mas_blsp_1",
181 .id = MSM8916_MASTER_BLSP_1,
182 .buswidth = 4,
183 .mas_rpm_id = -1,
184 .slv_rpm_id = -1,
185 .num_links = ARRAY_SIZE(mas_blsp_1_links),
186 .links = mas_blsp_1_links,
187};
188
189static const u16 mas_dehr_links[] = {
190 MSM8916_PNOC_MAS_0
191};
192
193static struct qcom_icc_node mas_dehr = {
194 .name = "mas_dehr",
195 .id = MSM8916_MASTER_DEHR,
196 .buswidth = 4,
197 .mas_rpm_id = -1,
198 .slv_rpm_id = -1,
199 .num_links = ARRAY_SIZE(mas_dehr_links),
200 .links = mas_dehr_links,
201};
202
203static const u16 mas_gfx_links[] = {
204 MSM8916_SLAVE_EBI_CH0,
205 MSM8916_BIMC_SNOC_MAS,
206 MSM8916_SLAVE_AMPSS_L2
207};
208
209static struct qcom_icc_node mas_gfx = {
210 .name = "mas_gfx",
211 .id = MSM8916_MASTER_GRAPHICS_3D,
212 .buswidth = 8,
213 .mas_rpm_id = -1,
214 .slv_rpm_id = -1,
215 .qos.ap_owned = true,
216 .qos.qos_mode = NOC_QOS_MODE_FIXED,
217 .qos.areq_prio = 0,
218 .qos.prio_level = 0,
219 .qos.qos_port = 2,
220 .num_links = ARRAY_SIZE(mas_gfx_links),
221 .links = mas_gfx_links,
222};
223
224static const u16 mas_jpeg_links[] = {
225 MSM8916_SNOC_MM_INT_0,
226 MSM8916_SNOC_MM_INT_2
227};
228
229static struct qcom_icc_node mas_jpeg = {
230 .name = "mas_jpeg",
231 .id = MSM8916_MASTER_JPEG,
232 .buswidth = 16,
233 .mas_rpm_id = -1,
234 .slv_rpm_id = -1,
235 .qos.ap_owned = true,
236 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
237 .qos.areq_prio = 0,
238 .qos.prio_level = 0,
239 .qos.qos_port = 6,
240 .num_links = ARRAY_SIZE(mas_jpeg_links),
241 .links = mas_jpeg_links,
242};
243
244static const u16 mas_mdp_links[] = {
245 MSM8916_SNOC_MM_INT_0,
246 MSM8916_SNOC_MM_INT_2
247};
248
249static struct qcom_icc_node mas_mdp = {
250 .name = "mas_mdp",
251 .id = MSM8916_MASTER_MDP_PORT0,
252 .buswidth = 16,
253 .mas_rpm_id = -1,
254 .slv_rpm_id = -1,
255 .qos.ap_owned = true,
256 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
257 .qos.areq_prio = 0,
258 .qos.prio_level = 0,
259 .qos.qos_port = 7,
260 .num_links = ARRAY_SIZE(mas_mdp_links),
261 .links = mas_mdp_links,
262};
263
264static const u16 mas_pcnoc_crypto_0_links[] = {
265 MSM8916_PNOC_INT_1
266};
267
268static struct qcom_icc_node mas_pcnoc_crypto_0 = {
269 .name = "mas_pcnoc_crypto_0",
270 .id = MSM8916_MASTER_CRYPTO_CORE0,
271 .buswidth = 8,
272 .mas_rpm_id = -1,
273 .slv_rpm_id = -1,
274 .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links),
275 .links = mas_pcnoc_crypto_0_links,
276};
277
278static const u16 mas_pcnoc_sdcc_1_links[] = {
279 MSM8916_PNOC_INT_1
280};
281
282static struct qcom_icc_node mas_pcnoc_sdcc_1 = {
283 .name = "mas_pcnoc_sdcc_1",
284 .id = MSM8916_MASTER_SDCC_1,
285 .buswidth = 8,
286 .mas_rpm_id = -1,
287 .slv_rpm_id = -1,
288 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links),
289 .links = mas_pcnoc_sdcc_1_links,
290};
291
292static const u16 mas_pcnoc_sdcc_2_links[] = {
293 MSM8916_PNOC_INT_1
294};
295
296static struct qcom_icc_node mas_pcnoc_sdcc_2 = {
297 .name = "mas_pcnoc_sdcc_2",
298 .id = MSM8916_MASTER_SDCC_2,
299 .buswidth = 8,
300 .mas_rpm_id = -1,
301 .slv_rpm_id = -1,
302 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links),
303 .links = mas_pcnoc_sdcc_2_links,
304};
305
306static const u16 mas_qdss_bam_links[] = {
307 MSM8916_SNOC_QDSS_INT
308};
309
310static struct qcom_icc_node mas_qdss_bam = {
311 .name = "mas_qdss_bam",
312 .id = MSM8916_MASTER_QDSS_BAM,
313 .buswidth = 8,
314 .mas_rpm_id = -1,
315 .slv_rpm_id = -1,
316 .qos.ap_owned = true,
317 .qos.qos_mode = NOC_QOS_MODE_FIXED,
318 .qos.areq_prio = 1,
319 .qos.prio_level = 1,
320 .qos.qos_port = 11,
321 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
322 .links = mas_qdss_bam_links,
323};
324
325static const u16 mas_qdss_etr_links[] = {
326 MSM8916_SNOC_QDSS_INT
327};
328
329static struct qcom_icc_node mas_qdss_etr = {
330 .name = "mas_qdss_etr",
331 .id = MSM8916_MASTER_QDSS_ETR,
332 .buswidth = 8,
333 .mas_rpm_id = -1,
334 .slv_rpm_id = -1,
335 .qos.ap_owned = true,
336 .qos.qos_mode = NOC_QOS_MODE_FIXED,
337 .qos.areq_prio = 1,
338 .qos.prio_level = 1,
339 .qos.qos_port = 10,
340 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
341 .links = mas_qdss_etr_links,
342};
343
344static const u16 mas_snoc_cfg_links[] = {
345 MSM8916_SNOC_QDSS_INT
346};
347
348static struct qcom_icc_node mas_snoc_cfg = {
349 .name = "mas_snoc_cfg",
350 .id = MSM8916_MASTER_SNOC_CFG,
351 .buswidth = 4,
352 .mas_rpm_id = -1,
353 .slv_rpm_id = -1,
354 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
355 .links = mas_snoc_cfg_links,
356};
357
358static const u16 mas_spdm_links[] = {
359 MSM8916_PNOC_MAS_0
360};
361
362static struct qcom_icc_node mas_spdm = {
363 .name = "mas_spdm",
364 .id = MSM8916_MASTER_SPDM,
365 .buswidth = 4,
366 .mas_rpm_id = -1,
367 .slv_rpm_id = -1,
368 .num_links = ARRAY_SIZE(mas_spdm_links),
369 .links = mas_spdm_links,
370};
371
372static const u16 mas_tcu0_links[] = {
373 MSM8916_SLAVE_EBI_CH0,
374 MSM8916_BIMC_SNOC_MAS,
375 MSM8916_SLAVE_AMPSS_L2
376};
377
378static struct qcom_icc_node mas_tcu0 = {
379 .name = "mas_tcu0",
380 .id = MSM8916_MASTER_TCU0,
381 .buswidth = 8,
382 .mas_rpm_id = -1,
383 .slv_rpm_id = -1,
384 .qos.ap_owned = true,
385 .qos.qos_mode = NOC_QOS_MODE_FIXED,
386 .qos.areq_prio = 2,
387 .qos.prio_level = 2,
388 .qos.qos_port = 5,
389 .num_links = ARRAY_SIZE(mas_tcu0_links),
390 .links = mas_tcu0_links,
391};
392
393static const u16 mas_tcu1_links[] = {
394 MSM8916_SLAVE_EBI_CH0,
395 MSM8916_BIMC_SNOC_MAS,
396 MSM8916_SLAVE_AMPSS_L2
397};
398
399static struct qcom_icc_node mas_tcu1 = {
400 .name = "mas_tcu1",
401 .id = MSM8916_MASTER_TCU1,
402 .buswidth = 8,
403 .mas_rpm_id = -1,
404 .slv_rpm_id = -1,
405 .qos.ap_owned = true,
406 .qos.qos_mode = NOC_QOS_MODE_FIXED,
407 .qos.areq_prio = 2,
408 .qos.prio_level = 2,
409 .qos.qos_port = 6,
410 .num_links = ARRAY_SIZE(mas_tcu1_links),
411 .links = mas_tcu1_links,
412};
413
414static const u16 mas_usb_hs_links[] = {
415 MSM8916_PNOC_MAS_1
416};
417
418static struct qcom_icc_node mas_usb_hs = {
419 .name = "mas_usb_hs",
420 .id = MSM8916_MASTER_USB_HS,
421 .buswidth = 4,
422 .mas_rpm_id = -1,
423 .slv_rpm_id = -1,
424 .num_links = ARRAY_SIZE(mas_usb_hs_links),
425 .links = mas_usb_hs_links,
426};
427
428static const u16 mas_vfe_links[] = {
429 MSM8916_SNOC_MM_INT_1,
430 MSM8916_SNOC_MM_INT_2
431};
432
433static struct qcom_icc_node mas_vfe = {
434 .name = "mas_vfe",
435 .id = MSM8916_MASTER_VFE,
436 .buswidth = 16,
437 .mas_rpm_id = -1,
438 .slv_rpm_id = -1,
439 .qos.ap_owned = true,
440 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
441 .qos.areq_prio = 0,
442 .qos.prio_level = 0,
443 .qos.qos_port = 9,
444 .num_links = ARRAY_SIZE(mas_vfe_links),
445 .links = mas_vfe_links,
446};
447
448static const u16 mas_video_links[] = {
449 MSM8916_SNOC_MM_INT_0,
450 MSM8916_SNOC_MM_INT_2
451};
452
453static struct qcom_icc_node mas_video = {
454 .name = "mas_video",
455 .id = MSM8916_MASTER_VIDEO_P0,
456 .buswidth = 16,
457 .mas_rpm_id = -1,
458 .slv_rpm_id = -1,
459 .qos.ap_owned = true,
460 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
461 .qos.areq_prio = 0,
462 .qos.prio_level = 0,
463 .qos.qos_port = 8,
464 .num_links = ARRAY_SIZE(mas_video_links),
465 .links = mas_video_links,
466};
467
468static const u16 mm_int_0_links[] = {
469 MSM8916_SNOC_MM_INT_BIMC
470};
471
472static struct qcom_icc_node mm_int_0 = {
473 .name = "mm_int_0",
474 .id = MSM8916_SNOC_MM_INT_0,
475 .buswidth = 16,
476 .mas_rpm_id = -1,
477 .slv_rpm_id = -1,
478 .qos.ap_owned = true,
479 .qos.qos_mode = NOC_QOS_MODE_INVALID,
480 .num_links = ARRAY_SIZE(mm_int_0_links),
481 .links = mm_int_0_links,
482};
483
484static const u16 mm_int_1_links[] = {
485 MSM8916_SNOC_MM_INT_BIMC
486};
487
488static struct qcom_icc_node mm_int_1 = {
489 .name = "mm_int_1",
490 .id = MSM8916_SNOC_MM_INT_1,
491 .buswidth = 16,
492 .mas_rpm_id = -1,
493 .slv_rpm_id = -1,
494 .qos.ap_owned = true,
495 .qos.qos_mode = NOC_QOS_MODE_INVALID,
496 .num_links = ARRAY_SIZE(mm_int_1_links),
497 .links = mm_int_1_links,
498};
499
500static const u16 mm_int_2_links[] = {
501 MSM8916_SNOC_INT_0
502};
503
504static struct qcom_icc_node mm_int_2 = {
505 .name = "mm_int_2",
506 .id = MSM8916_SNOC_MM_INT_2,
507 .buswidth = 16,
508 .mas_rpm_id = -1,
509 .slv_rpm_id = -1,
510 .qos.ap_owned = true,
511 .qos.qos_mode = NOC_QOS_MODE_INVALID,
512 .num_links = ARRAY_SIZE(mm_int_2_links),
513 .links = mm_int_2_links,
514};
515
516static const u16 mm_int_bimc_links[] = {
517 MSM8916_SNOC_BIMC_1_MAS
518};
519
520static struct qcom_icc_node mm_int_bimc = {
521 .name = "mm_int_bimc",
522 .id = MSM8916_SNOC_MM_INT_BIMC,
523 .buswidth = 16,
524 .mas_rpm_id = -1,
525 .slv_rpm_id = -1,
526 .qos.ap_owned = true,
527 .qos.qos_mode = NOC_QOS_MODE_INVALID,
528 .num_links = ARRAY_SIZE(mm_int_bimc_links),
529 .links = mm_int_bimc_links,
530};
531
532static const u16 pcnoc_int_0_links[] = {
533 MSM8916_PNOC_SNOC_MAS,
534 MSM8916_PNOC_SLV_0,
535 MSM8916_PNOC_SLV_1,
536 MSM8916_PNOC_SLV_2,
537 MSM8916_PNOC_SLV_3,
538 MSM8916_PNOC_SLV_4,
539 MSM8916_PNOC_SLV_8,
540 MSM8916_PNOC_SLV_9
541};
542
543static struct qcom_icc_node pcnoc_int_0 = {
544 .name = "pcnoc_int_0",
545 .id = MSM8916_PNOC_INT_0,
546 .buswidth = 8,
547 .mas_rpm_id = -1,
548 .slv_rpm_id = -1,
549 .num_links = ARRAY_SIZE(pcnoc_int_0_links),
550 .links = pcnoc_int_0_links,
551};
552
553static const u16 pcnoc_int_1_links[] = {
554 MSM8916_PNOC_SNOC_MAS
555};
556
557static struct qcom_icc_node pcnoc_int_1 = {
558 .name = "pcnoc_int_1",
559 .id = MSM8916_PNOC_INT_1,
560 .buswidth = 8,
561 .mas_rpm_id = -1,
562 .slv_rpm_id = -1,
563 .num_links = ARRAY_SIZE(pcnoc_int_1_links),
564 .links = pcnoc_int_1_links,
565};
566
567static const u16 pcnoc_m_0_links[] = {
568 MSM8916_PNOC_INT_0
569};
570
571static struct qcom_icc_node pcnoc_m_0 = {
572 .name = "pcnoc_m_0",
573 .id = MSM8916_PNOC_MAS_0,
574 .buswidth = 8,
575 .mas_rpm_id = -1,
576 .slv_rpm_id = -1,
577 .num_links = ARRAY_SIZE(pcnoc_m_0_links),
578 .links = pcnoc_m_0_links,
579};
580
581static const u16 pcnoc_m_1_links[] = {
582 MSM8916_PNOC_SNOC_MAS
583};
584
585static struct qcom_icc_node pcnoc_m_1 = {
586 .name = "pcnoc_m_1",
587 .id = MSM8916_PNOC_MAS_1,
588 .buswidth = 8,
589 .mas_rpm_id = -1,
590 .slv_rpm_id = -1,
591 .num_links = ARRAY_SIZE(pcnoc_m_1_links),
592 .links = pcnoc_m_1_links,
593};
594
595static const u16 pcnoc_s_0_links[] = {
596 MSM8916_SLAVE_CLK_CTL,
597 MSM8916_SLAVE_TLMM,
598 MSM8916_SLAVE_TCSR,
599 MSM8916_SLAVE_SECURITY,
600 MSM8916_SLAVE_MSS
601};
602
603static struct qcom_icc_node pcnoc_s_0 = {
604 .name = "pcnoc_s_0",
605 .id = MSM8916_PNOC_SLV_0,
606 .buswidth = 4,
607 .mas_rpm_id = -1,
608 .slv_rpm_id = -1,
609 .num_links = ARRAY_SIZE(pcnoc_s_0_links),
610 .links = pcnoc_s_0_links,
611};
612
613static const u16 pcnoc_s_1_links[] = {
614 MSM8916_SLAVE_IMEM_CFG,
615 MSM8916_SLAVE_CRYPTO_0_CFG,
616 MSM8916_SLAVE_MSG_RAM,
617 MSM8916_SLAVE_PDM,
618 MSM8916_SLAVE_PRNG
619};
620
621static struct qcom_icc_node pcnoc_s_1 = {
622 .name = "pcnoc_s_1",
623 .id = MSM8916_PNOC_SLV_1,
624 .buswidth = 4,
625 .mas_rpm_id = -1,
626 .slv_rpm_id = -1,
627 .num_links = ARRAY_SIZE(pcnoc_s_1_links),
628 .links = pcnoc_s_1_links,
629};
630
631static const u16 pcnoc_s_2_links[] = {
632 MSM8916_SLAVE_SPDM,
633 MSM8916_SLAVE_BOOT_ROM,
634 MSM8916_SLAVE_BIMC_CFG,
635 MSM8916_SLAVE_PNOC_CFG,
636 MSM8916_SLAVE_PMIC_ARB
637};
638
639static struct qcom_icc_node pcnoc_s_2 = {
640 .name = "pcnoc_s_2",
641 .id = MSM8916_PNOC_SLV_2,
642 .buswidth = 4,
643 .mas_rpm_id = -1,
644 .slv_rpm_id = -1,
645 .num_links = ARRAY_SIZE(pcnoc_s_2_links),
646 .links = pcnoc_s_2_links,
647};
648
649static const u16 pcnoc_s_3_links[] = {
650 MSM8916_SLAVE_MPM,
651 MSM8916_SLAVE_SNOC_CFG,
652 MSM8916_SLAVE_RBCPR_CFG,
653 MSM8916_SLAVE_QDSS_CFG,
654 MSM8916_SLAVE_DEHR_CFG
655};
656
657static struct qcom_icc_node pcnoc_s_3 = {
658 .name = "pcnoc_s_3",
659 .id = MSM8916_PNOC_SLV_3,
660 .buswidth = 4,
661 .mas_rpm_id = -1,
662 .slv_rpm_id = -1,
663 .num_links = ARRAY_SIZE(pcnoc_s_3_links),
664 .links = pcnoc_s_3_links,
665};
666
667static const u16 pcnoc_s_4_links[] = {
668 MSM8916_SLAVE_VENUS_CFG,
669 MSM8916_SLAVE_CAMERA_CFG,
670 MSM8916_SLAVE_DISPLAY_CFG
671};
672
673static struct qcom_icc_node pcnoc_s_4 = {
674 .name = "pcnoc_s_4",
675 .id = MSM8916_PNOC_SLV_4,
676 .buswidth = 4,
677 .mas_rpm_id = -1,
678 .slv_rpm_id = -1,
679 .num_links = ARRAY_SIZE(pcnoc_s_4_links),
680 .links = pcnoc_s_4_links,
681};
682
683static const u16 pcnoc_s_8_links[] = {
684 MSM8916_SLAVE_USB_HS,
685 MSM8916_SLAVE_SDCC_1,
686 MSM8916_SLAVE_BLSP_1
687};
688
689static struct qcom_icc_node pcnoc_s_8 = {
690 .name = "pcnoc_s_8",
691 .id = MSM8916_PNOC_SLV_8,
692 .buswidth = 4,
693 .mas_rpm_id = -1,
694 .slv_rpm_id = -1,
695 .num_links = ARRAY_SIZE(pcnoc_s_8_links),
696 .links = pcnoc_s_8_links,
697};
698
699static const u16 pcnoc_s_9_links[] = {
700 MSM8916_SLAVE_SDCC_2,
701 MSM8916_SLAVE_LPASS,
702 MSM8916_SLAVE_GRAPHICS_3D_CFG
703};
704
705static struct qcom_icc_node pcnoc_s_9 = {
706 .name = "pcnoc_s_9",
707 .id = MSM8916_PNOC_SLV_9,
708 .buswidth = 4,
709 .mas_rpm_id = -1,
710 .slv_rpm_id = -1,
711 .num_links = ARRAY_SIZE(pcnoc_s_9_links),
712 .links = pcnoc_s_9_links,
713};
714
715static const u16 pcnoc_snoc_mas_links[] = {
716 MSM8916_PNOC_SNOC_SLV
717};
718
719static struct qcom_icc_node pcnoc_snoc_mas = {
720 .name = "pcnoc_snoc_mas",
721 .id = MSM8916_PNOC_SNOC_MAS,
722 .buswidth = 8,
723 .mas_rpm_id = 29,
724 .slv_rpm_id = -1,
725 .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links),
726 .links = pcnoc_snoc_mas_links,
727};
728
729static const u16 pcnoc_snoc_slv_links[] = {
730 MSM8916_SNOC_INT_0,
731 MSM8916_SNOC_INT_BIMC,
732 MSM8916_SNOC_INT_1
733};
734
735static struct qcom_icc_node pcnoc_snoc_slv = {
736 .name = "pcnoc_snoc_slv",
737 .id = MSM8916_PNOC_SNOC_SLV,
738 .buswidth = 8,
739 .mas_rpm_id = -1,
740 .slv_rpm_id = 45,
741 .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links),
742 .links = pcnoc_snoc_slv_links,
743};
744
745static const u16 qdss_int_links[] = {
746 MSM8916_SNOC_INT_0,
747 MSM8916_SNOC_INT_BIMC
748};
749
750static struct qcom_icc_node qdss_int = {
751 .name = "qdss_int",
752 .id = MSM8916_SNOC_QDSS_INT,
753 .buswidth = 8,
754 .mas_rpm_id = -1,
755 .slv_rpm_id = -1,
756 .qos.ap_owned = true,
757 .qos.qos_mode = NOC_QOS_MODE_INVALID,
758 .num_links = ARRAY_SIZE(qdss_int_links),
759 .links = qdss_int_links,
760};
761
762static struct qcom_icc_node slv_apps_l2 = {
763 .name = "slv_apps_l2",
764 .id = MSM8916_SLAVE_AMPSS_L2,
765 .buswidth = 8,
766 .mas_rpm_id = -1,
767 .slv_rpm_id = -1,
768};
769
770static struct qcom_icc_node slv_apss = {
771 .name = "slv_apss",
772 .id = MSM8916_SLAVE_APSS,
773 .buswidth = 4,
774 .mas_rpm_id = -1,
775 .slv_rpm_id = -1,
776};
777
778static struct qcom_icc_node slv_audio = {
779 .name = "slv_audio",
780 .id = MSM8916_SLAVE_LPASS,
781 .buswidth = 4,
782 .mas_rpm_id = -1,
783 .slv_rpm_id = -1,
784};
785
786static struct qcom_icc_node slv_bimc_cfg = {
787 .name = "slv_bimc_cfg",
788 .id = MSM8916_SLAVE_BIMC_CFG,
789 .buswidth = 4,
790 .mas_rpm_id = -1,
791 .slv_rpm_id = -1,
792};
793
794static struct qcom_icc_node slv_blsp_1 = {
795 .name = "slv_blsp_1",
796 .id = MSM8916_SLAVE_BLSP_1,
797 .buswidth = 4,
798 .mas_rpm_id = -1,
799 .slv_rpm_id = -1,
800};
801
802static struct qcom_icc_node slv_boot_rom = {
803 .name = "slv_boot_rom",
804 .id = MSM8916_SLAVE_BOOT_ROM,
805 .buswidth = 4,
806 .mas_rpm_id = -1,
807 .slv_rpm_id = -1,
808};
809
810static struct qcom_icc_node slv_camera_cfg = {
811 .name = "slv_camera_cfg",
812 .id = MSM8916_SLAVE_CAMERA_CFG,
813 .buswidth = 4,
814 .mas_rpm_id = -1,
815 .slv_rpm_id = -1,
816};
817
818static struct qcom_icc_node slv_cats_0 = {
819 .name = "slv_cats_0",
820 .id = MSM8916_SLAVE_CATS_128,
821 .buswidth = 16,
822 .mas_rpm_id = -1,
823 .slv_rpm_id = -1,
824};
825
826static struct qcom_icc_node slv_cats_1 = {
827 .name = "slv_cats_1",
828 .id = MSM8916_SLAVE_OCMEM_64,
829 .buswidth = 8,
830 .mas_rpm_id = -1,
831 .slv_rpm_id = -1,
832};
833
834static struct qcom_icc_node slv_clk_ctl = {
835 .name = "slv_clk_ctl",
836 .id = MSM8916_SLAVE_CLK_CTL,
837 .buswidth = 4,
838 .mas_rpm_id = -1,
839 .slv_rpm_id = -1,
840};
841
842static struct qcom_icc_node slv_crypto_0_cfg = {
843 .name = "slv_crypto_0_cfg",
844 .id = MSM8916_SLAVE_CRYPTO_0_CFG,
845 .buswidth = 4,
846 .mas_rpm_id = -1,
847 .slv_rpm_id = -1,
848};
849
850static struct qcom_icc_node slv_dehr_cfg = {
851 .name = "slv_dehr_cfg",
852 .id = MSM8916_SLAVE_DEHR_CFG,
853 .buswidth = 4,
854 .mas_rpm_id = -1,
855 .slv_rpm_id = -1,
856};
857
858static struct qcom_icc_node slv_display_cfg = {
859 .name = "slv_display_cfg",
860 .id = MSM8916_SLAVE_DISPLAY_CFG,
861 .buswidth = 4,
862 .mas_rpm_id = -1,
863 .slv_rpm_id = -1,
864};
865
866static struct qcom_icc_node slv_ebi_ch0 = {
867 .name = "slv_ebi_ch0",
868 .id = MSM8916_SLAVE_EBI_CH0,
869 .buswidth = 8,
870 .mas_rpm_id = -1,
871 .slv_rpm_id = 0,
872};
873
874static struct qcom_icc_node slv_gfx_cfg = {
875 .name = "slv_gfx_cfg",
876 .id = MSM8916_SLAVE_GRAPHICS_3D_CFG,
877 .buswidth = 4,
878 .mas_rpm_id = -1,
879 .slv_rpm_id = -1,
880};
881
882static struct qcom_icc_node slv_imem_cfg = {
883 .name = "slv_imem_cfg",
884 .id = MSM8916_SLAVE_IMEM_CFG,
885 .buswidth = 4,
886 .mas_rpm_id = -1,
887 .slv_rpm_id = -1,
888};
889
890static struct qcom_icc_node slv_imem = {
891 .name = "slv_imem",
892 .id = MSM8916_SLAVE_IMEM,
893 .buswidth = 8,
894 .mas_rpm_id = -1,
895 .slv_rpm_id = 26,
896};
897
898static struct qcom_icc_node slv_mpm = {
899 .name = "slv_mpm",
900 .id = MSM8916_SLAVE_MPM,
901 .buswidth = 4,
902 .mas_rpm_id = -1,
903 .slv_rpm_id = -1,
904};
905
906static struct qcom_icc_node slv_msg_ram = {
907 .name = "slv_msg_ram",
908 .id = MSM8916_SLAVE_MSG_RAM,
909 .buswidth = 4,
910 .mas_rpm_id = -1,
911 .slv_rpm_id = -1,
912};
913
914static struct qcom_icc_node slv_mss = {
915 .name = "slv_mss",
916 .id = MSM8916_SLAVE_MSS,
917 .buswidth = 4,
918 .mas_rpm_id = -1,
919 .slv_rpm_id = -1,
920};
921
922static struct qcom_icc_node slv_pdm = {
923 .name = "slv_pdm",
924 .id = MSM8916_SLAVE_PDM,
925 .buswidth = 4,
926 .mas_rpm_id = -1,
927 .slv_rpm_id = -1,
928};
929
930static struct qcom_icc_node slv_pmic_arb = {
931 .name = "slv_pmic_arb",
932 .id = MSM8916_SLAVE_PMIC_ARB,
933 .buswidth = 4,
934 .mas_rpm_id = -1,
935 .slv_rpm_id = -1,
936};
937
938static struct qcom_icc_node slv_pcnoc_cfg = {
939 .name = "slv_pcnoc_cfg",
940 .id = MSM8916_SLAVE_PNOC_CFG,
941 .buswidth = 4,
942 .mas_rpm_id = -1,
943 .slv_rpm_id = -1,
944};
945
946static struct qcom_icc_node slv_prng = {
947 .name = "slv_prng",
948 .id = MSM8916_SLAVE_PRNG,
949 .buswidth = 4,
950 .mas_rpm_id = -1,
951 .slv_rpm_id = -1,
952};
953
954static struct qcom_icc_node slv_qdss_cfg = {
955 .name = "slv_qdss_cfg",
956 .id = MSM8916_SLAVE_QDSS_CFG,
957 .buswidth = 4,
958 .mas_rpm_id = -1,
959 .slv_rpm_id = -1,
960};
961
962static struct qcom_icc_node slv_qdss_stm = {
963 .name = "slv_qdss_stm",
964 .id = MSM8916_SLAVE_QDSS_STM,
965 .buswidth = 4,
966 .mas_rpm_id = -1,
967 .slv_rpm_id = 30,
968};
969
970static struct qcom_icc_node slv_rbcpr_cfg = {
971 .name = "slv_rbcpr_cfg",
972 .id = MSM8916_SLAVE_RBCPR_CFG,
973 .buswidth = 4,
974 .mas_rpm_id = -1,
975 .slv_rpm_id = -1,
976};
977
978static struct qcom_icc_node slv_sdcc_1 = {
979 .name = "slv_sdcc_1",
980 .id = MSM8916_SLAVE_SDCC_1,
981 .buswidth = 4,
982 .mas_rpm_id = -1,
983 .slv_rpm_id = -1,
984};
985
986static struct qcom_icc_node slv_sdcc_2 = {
987 .name = "slv_sdcc_2",
988 .id = MSM8916_SLAVE_SDCC_2,
989 .buswidth = 4,
990 .mas_rpm_id = -1,
991 .slv_rpm_id = -1,
992};
993
994static struct qcom_icc_node slv_security = {
995 .name = "slv_security",
996 .id = MSM8916_SLAVE_SECURITY,
997 .buswidth = 4,
998 .mas_rpm_id = -1,
999 .slv_rpm_id = -1,
1000};
1001
1002static struct qcom_icc_node slv_snoc_cfg = {
1003 .name = "slv_snoc_cfg",
1004 .id = MSM8916_SLAVE_SNOC_CFG,
1005 .buswidth = 4,
1006 .mas_rpm_id = -1,
1007 .slv_rpm_id = -1,
1008};
1009
1010static struct qcom_icc_node slv_spdm = {
1011 .name = "slv_spdm",
1012 .id = MSM8916_SLAVE_SPDM,
1013 .buswidth = 4,
1014 .mas_rpm_id = -1,
1015 .slv_rpm_id = -1,
1016};
1017
1018static struct qcom_icc_node slv_srvc_snoc = {
1019 .name = "slv_srvc_snoc",
1020 .id = MSM8916_SLAVE_SRVC_SNOC,
1021 .buswidth = 8,
1022 .mas_rpm_id = -1,
1023 .slv_rpm_id = -1,
1024};
1025
1026static struct qcom_icc_node slv_tcsr = {
1027 .name = "slv_tcsr",
1028 .id = MSM8916_SLAVE_TCSR,
1029 .buswidth = 4,
1030 .mas_rpm_id = -1,
1031 .slv_rpm_id = -1,
1032};
1033
1034static struct qcom_icc_node slv_tlmm = {
1035 .name = "slv_tlmm",
1036 .id = MSM8916_SLAVE_TLMM,
1037 .buswidth = 4,
1038 .mas_rpm_id = -1,
1039 .slv_rpm_id = -1,
1040};
1041
1042static struct qcom_icc_node slv_usb_hs = {
1043 .name = "slv_usb_hs",
1044 .id = MSM8916_SLAVE_USB_HS,
1045 .buswidth = 4,
1046 .mas_rpm_id = -1,
1047 .slv_rpm_id = -1,
1048};
1049
1050static struct qcom_icc_node slv_venus_cfg = {
1051 .name = "slv_venus_cfg",
1052 .id = MSM8916_SLAVE_VENUS_CFG,
1053 .buswidth = 4,
1054 .mas_rpm_id = -1,
1055 .slv_rpm_id = -1,
1056};
1057
1058static const u16 snoc_bimc_0_mas_links[] = {
1059 MSM8916_SNOC_BIMC_0_SLV
1060};
1061
1062static struct qcom_icc_node snoc_bimc_0_mas = {
1063 .name = "snoc_bimc_0_mas",
1064 .id = MSM8916_SNOC_BIMC_0_MAS,
1065 .buswidth = 8,
1066 .mas_rpm_id = 3,
1067 .slv_rpm_id = -1,
1068 .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links),
1069 .links = snoc_bimc_0_mas_links,
1070};
1071
1072static const u16 snoc_bimc_0_slv_links[] = {
1073 MSM8916_SLAVE_EBI_CH0
1074};
1075
1076static struct qcom_icc_node snoc_bimc_0_slv = {
1077 .name = "snoc_bimc_0_slv",
1078 .id = MSM8916_SNOC_BIMC_0_SLV,
1079 .buswidth = 8,
1080 .mas_rpm_id = -1,
1081 .slv_rpm_id = 24,
1082 .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links),
1083 .links = snoc_bimc_0_slv_links,
1084};
1085
1086static const u16 snoc_bimc_1_mas_links[] = {
1087 MSM8916_SNOC_BIMC_1_SLV
1088};
1089
1090static struct qcom_icc_node snoc_bimc_1_mas = {
1091 .name = "snoc_bimc_1_mas",
1092 .id = MSM8916_SNOC_BIMC_1_MAS,
1093 .buswidth = 16,
1094 .mas_rpm_id = -1,
1095 .slv_rpm_id = -1,
1096 .qos.ap_owned = true,
1097 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1098 .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links),
1099 .links = snoc_bimc_1_mas_links,
1100};
1101
1102static const u16 snoc_bimc_1_slv_links[] = {
1103 MSM8916_SLAVE_EBI_CH0
1104};
1105
1106static struct qcom_icc_node snoc_bimc_1_slv = {
1107 .name = "snoc_bimc_1_slv",
1108 .id = MSM8916_SNOC_BIMC_1_SLV,
1109 .buswidth = 8,
1110 .mas_rpm_id = -1,
1111 .slv_rpm_id = -1,
1112 .qos.ap_owned = true,
1113 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1114 .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links),
1115 .links = snoc_bimc_1_slv_links,
1116};
1117
1118static const u16 snoc_int_0_links[] = {
1119 MSM8916_SLAVE_QDSS_STM,
1120 MSM8916_SLAVE_IMEM,
1121 MSM8916_SNOC_PNOC_MAS
1122};
1123
1124static struct qcom_icc_node snoc_int_0 = {
1125 .name = "snoc_int_0",
1126 .id = MSM8916_SNOC_INT_0,
1127 .buswidth = 8,
1128 .mas_rpm_id = 99,
1129 .slv_rpm_id = 130,
1130 .num_links = ARRAY_SIZE(snoc_int_0_links),
1131 .links = snoc_int_0_links,
1132};
1133
1134static const u16 snoc_int_1_links[] = {
1135 MSM8916_SLAVE_APSS,
1136 MSM8916_SLAVE_CATS_128,
1137 MSM8916_SLAVE_OCMEM_64
1138};
1139
1140static struct qcom_icc_node snoc_int_1 = {
1141 .name = "snoc_int_1",
1142 .id = MSM8916_SNOC_INT_1,
1143 .buswidth = 8,
1144 .mas_rpm_id = -1,
1145 .slv_rpm_id = -1,
1146 .num_links = ARRAY_SIZE(snoc_int_1_links),
1147 .links = snoc_int_1_links,
1148};
1149
1150static const u16 snoc_int_bimc_links[] = {
1151 MSM8916_SNOC_BIMC_0_MAS
1152};
1153
1154static struct qcom_icc_node snoc_int_bimc = {
1155 .name = "snoc_int_bimc",
1156 .id = MSM8916_SNOC_INT_BIMC,
1157 .buswidth = 8,
1158 .mas_rpm_id = 101,
1159 .slv_rpm_id = 132,
1160 .num_links = ARRAY_SIZE(snoc_int_bimc_links),
1161 .links = snoc_int_bimc_links,
1162};
1163
1164static const u16 snoc_pcnoc_mas_links[] = {
1165 MSM8916_SNOC_PNOC_SLV
1166};
1167
1168static struct qcom_icc_node snoc_pcnoc_mas = {
1169 .name = "snoc_pcnoc_mas",
1170 .id = MSM8916_SNOC_PNOC_MAS,
1171 .buswidth = 8,
1172 .mas_rpm_id = -1,
1173 .slv_rpm_id = -1,
1174 .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links),
1175 .links = snoc_pcnoc_mas_links,
1176};
1177
1178static const u16 snoc_pcnoc_slv_links[] = {
1179 MSM8916_PNOC_INT_0
1180};
1181
1182static struct qcom_icc_node snoc_pcnoc_slv = {
1183 .name = "snoc_pcnoc_slv",
1184 .id = MSM8916_SNOC_PNOC_SLV,
1185 .buswidth = 8,
1186 .mas_rpm_id = -1,
1187 .slv_rpm_id = -1,
1188 .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links),
1189 .links = snoc_pcnoc_slv_links,
1190};
1191
1192static struct qcom_icc_node * const msm8916_snoc_nodes[] = {
1193 [BIMC_SNOC_SLV] = &bimc_snoc_slv,
1194 [MASTER_JPEG] = &mas_jpeg,
1195 [MASTER_MDP_PORT0] = &mas_mdp,
1196 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1197 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1198 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1199 [MASTER_VFE] = &mas_vfe,
1200 [MASTER_VIDEO_P0] = &mas_video,
1201 [SNOC_MM_INT_0] = &mm_int_0,
1202 [SNOC_MM_INT_1] = &mm_int_1,
1203 [SNOC_MM_INT_2] = &mm_int_2,
1204 [SNOC_MM_INT_BIMC] = &mm_int_bimc,
1205 [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv,
1206 [SLAVE_APSS] = &slv_apss,
1207 [SLAVE_CATS_128] = &slv_cats_0,
1208 [SLAVE_OCMEM_64] = &slv_cats_1,
1209 [SLAVE_IMEM] = &slv_imem,
1210 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1211 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1212 [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas,
1213 [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas,
1214 [SNOC_INT_0] = &snoc_int_0,
1215 [SNOC_INT_1] = &snoc_int_1,
1216 [SNOC_INT_BIMC] = &snoc_int_bimc,
1217 [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas,
1218 [SNOC_QDSS_INT] = &qdss_int,
1219};
1220
1221static const struct regmap_config msm8916_snoc_regmap_config = {
1222 .reg_bits = 32,
1223 .reg_stride = 4,
1224 .val_bits = 32,
1225 .max_register = 0x14000,
1226 .fast_io = true,
1227};
1228
1229static const struct qcom_icc_desc msm8916_snoc = {
1230 .type = QCOM_ICC_NOC,
1231 .nodes = msm8916_snoc_nodes,
1232 .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes),
1233 .bus_clk_desc = &bus_1_clk,
1234 .regmap_cfg = &msm8916_snoc_regmap_config,
1235 .qos_offset = 0x7000,
1236};
1237
1238static struct qcom_icc_node * const msm8916_bimc_nodes[] = {
1239 [BIMC_SNOC_MAS] = &bimc_snoc_mas,
1240 [MASTER_AMPSS_M0] = &mas_apss,
1241 [MASTER_GRAPHICS_3D] = &mas_gfx,
1242 [MASTER_TCU0] = &mas_tcu0,
1243 [MASTER_TCU1] = &mas_tcu1,
1244 [SLAVE_AMPSS_L2] = &slv_apps_l2,
1245 [SLAVE_EBI_CH0] = &slv_ebi_ch0,
1246 [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv,
1247 [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv,
1248};
1249
1250static const struct regmap_config msm8916_bimc_regmap_config = {
1251 .reg_bits = 32,
1252 .reg_stride = 4,
1253 .val_bits = 32,
1254 .max_register = 0x62000,
1255 .fast_io = true,
1256};
1257
1258static const struct qcom_icc_desc msm8916_bimc = {
1259 .type = QCOM_ICC_BIMC,
1260 .nodes = msm8916_bimc_nodes,
1261 .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes),
1262 .bus_clk_desc = &bimc_clk,
1263 .regmap_cfg = &msm8916_bimc_regmap_config,
1264 .qos_offset = 0x8000,
1265};
1266
1267static struct qcom_icc_node * const msm8916_pcnoc_nodes[] = {
1268 [MASTER_BLSP_1] = &mas_blsp_1,
1269 [MASTER_DEHR] = &mas_dehr,
1270 [MASTER_LPASS] = &mas_audio,
1271 [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0,
1272 [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1,
1273 [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2,
1274 [MASTER_SPDM] = &mas_spdm,
1275 [MASTER_USB_HS] = &mas_usb_hs,
1276 [PCNOC_INT_0] = &pcnoc_int_0,
1277 [PCNOC_INT_1] = &pcnoc_int_1,
1278 [PCNOC_MAS_0] = &pcnoc_m_0,
1279 [PCNOC_MAS_1] = &pcnoc_m_1,
1280 [PCNOC_SLV_0] = &pcnoc_s_0,
1281 [PCNOC_SLV_1] = &pcnoc_s_1,
1282 [PCNOC_SLV_2] = &pcnoc_s_2,
1283 [PCNOC_SLV_3] = &pcnoc_s_3,
1284 [PCNOC_SLV_4] = &pcnoc_s_4,
1285 [PCNOC_SLV_8] = &pcnoc_s_8,
1286 [PCNOC_SLV_9] = &pcnoc_s_9,
1287 [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas,
1288 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1289 [SLAVE_BLSP_1] = &slv_blsp_1,
1290 [SLAVE_BOOT_ROM] = &slv_boot_rom,
1291 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1292 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1293 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1294 [SLAVE_DEHR_CFG] = &slv_dehr_cfg,
1295 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1296 [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg,
1297 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1298 [SLAVE_LPASS] = &slv_audio,
1299 [SLAVE_MPM] = &slv_mpm,
1300 [SLAVE_MSG_RAM] = &slv_msg_ram,
1301 [SLAVE_MSS] = &slv_mss,
1302 [SLAVE_PDM] = &slv_pdm,
1303 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1304 [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg,
1305 [SLAVE_PRNG] = &slv_prng,
1306 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1307 [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg,
1308 [SLAVE_SDCC_1] = &slv_sdcc_1,
1309 [SLAVE_SDCC_2] = &slv_sdcc_2,
1310 [SLAVE_SECURITY] = &slv_security,
1311 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1312 [SLAVE_SPDM] = &slv_spdm,
1313 [SLAVE_TCSR] = &slv_tcsr,
1314 [SLAVE_TLMM] = &slv_tlmm,
1315 [SLAVE_USB_HS] = &slv_usb_hs,
1316 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1317 [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv,
1318};
1319
1320static const struct regmap_config msm8916_pcnoc_regmap_config = {
1321 .reg_bits = 32,
1322 .reg_stride = 4,
1323 .val_bits = 32,
1324 .max_register = 0x11000,
1325 .fast_io = true,
1326};
1327
1328static const struct qcom_icc_desc msm8916_pcnoc = {
1329 .type = QCOM_ICC_NOC,
1330 .nodes = msm8916_pcnoc_nodes,
1331 .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes),
1332 .bus_clk_desc = &bus_0_clk,
1333 .regmap_cfg = &msm8916_pcnoc_regmap_config,
1334 .qos_offset = 0x7000,
1335};
1336
1337static const struct of_device_id msm8916_noc_of_match[] = {
1338 { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc },
1339 { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc },
1340 { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc },
1341 { }
1342};
1343MODULE_DEVICE_TABLE(of, msm8916_noc_of_match);
1344
1345static struct platform_driver msm8916_noc_driver = {
1346 .probe = qnoc_probe,
1347 .remove = qnoc_remove,
1348 .driver = {
1349 .name = "qnoc-msm8916",
1350 .of_match_table = msm8916_noc_of_match,
1351 },
1352};
1353module_platform_driver(msm8916_noc_driver);
1354MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
1355MODULE_DESCRIPTION("Qualcomm MSM8916 NoC driver");
1356MODULE_LICENSE("GPL v2");