1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef __DPU_ENCODER_PHYS_H__
  8#define __DPU_ENCODER_PHYS_H__
  9
 10#include <drm/drm_writeback.h>
 11#include <linux/jiffies.h>
 12
 13#include "dpu_kms.h"
 14#include "dpu_hw_intf.h"
 15#include "dpu_hw_wb.h"
 16#include "dpu_hw_pingpong.h"
 17#include "dpu_hw_cdm.h"
 18#include "dpu_hw_ctl.h"
 19#include "dpu_hw_top.h"
 20#include "dpu_hw_util.h"
 21#include "dpu_encoder.h"
 22#include "dpu_crtc.h"
 23
 24#define DPU_ENCODER_NAME_MAX	16
 25
 26/* wait for at most 2 vsync for lowest refresh rate (24hz) */
 27#define KICKOFF_TIMEOUT_MS		84
 28#define KICKOFF_TIMEOUT_JIFFIES		msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
 29
 30/**
 31 * enum dpu_enc_split_role - Role this physical encoder will play in a
 32 *	split-panel configuration, where one panel is master, and others slaves.
 33 *	Masters have extra responsibilities, like managing the VBLANK IRQ.
 34 * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
 35 * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
 36 * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
 37 */
 38enum dpu_enc_split_role {
 39	ENC_ROLE_SOLO,
 40	ENC_ROLE_MASTER,
 41	ENC_ROLE_SLAVE,
 42};
 43
 44/**
 45 * enum dpu_enc_enable_state - current enabled state of the physical encoder
 46 * @DPU_ENC_DISABLING:	Encoder transitioning to disable state
 47 *			Events bounding transition are encoder type specific
 48 * @DPU_ENC_DISABLED:	Encoder is disabled
 49 * @DPU_ENC_ENABLING:	Encoder transitioning to enabled
 50 *			Events bounding transition are encoder type specific
 51 * @DPU_ENC_ENABLED:	Encoder is enabled
 52 * @DPU_ENC_ERR_NEEDS_HW_RESET:	Encoder is enabled, but requires a hw_reset
 53 *				to recover from a previous error
 54 */
 55enum dpu_enc_enable_state {
 56	DPU_ENC_DISABLING,
 57	DPU_ENC_DISABLED,
 58	DPU_ENC_ENABLING,
 59	DPU_ENC_ENABLED,
 60	DPU_ENC_ERR_NEEDS_HW_RESET
 61};
 62
 63struct dpu_encoder_phys;
 64
 65/**
 66 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
 67 *	the containing virtual encoder.
 68 * @prepare_commit:		MSM Atomic Call, start of atomic commit sequence
 69 * @is_master:			Whether this phys_enc is the current master
 70 *				encoder. Can be switched at enable time. Based
 71 *				on split_role and current mode (CMD/VID).
 72 * @atomic_mode_set:		DRM Call. Set a DRM mode.
 73 *				This likely caches the mode, for use at enable.
 74 * @enable:			DRM Call. Enable a DRM mode.
 75 * @disable:			DRM Call. Disable mode.
 76 * @control_vblank_irq		Register/Deregister for VBLANK IRQ
 77 * @wait_for_commit_done:	Wait for hardware to have flushed the
 78 *				current pending frames to hardware
 79 * @wait_for_tx_complete:	Wait for hardware to transfer the pixels
 80 *				to the panel
 81 * @wait_for_vblank:		Wait for VBLANK, for sub-driver internal use
 82 * @prepare_for_kickoff:	Do any work necessary prior to a kickoff
 83 *				For CMD encoder, may wait for previous tx done
 84 * @handle_post_kickoff:	Do any work necessary post-kickoff work
 85 * @trigger_start:		Process start event on physical encoder
 86 * @needs_single_flush:		Whether encoder slaves need to be flushed
 87 * @irq_enable:			Handler to enable all the encoder IRQs
 88 * @irq_disable:		Handler to disable all the encoder IRQs
 89 * @prepare_idle_pc:		phys encoder can update the vsync_enable status
 90 *                              on idle power collapse prepare
 91 * @restore:			Restore all the encoder configs.
 92 * @get_line_count:		Obtain current vertical line count
 93 */
 94
 95struct dpu_encoder_phys_ops {
 96	void (*prepare_commit)(struct dpu_encoder_phys *encoder);
 97	bool (*is_master)(struct dpu_encoder_phys *encoder);
 98	void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
 99			struct drm_crtc_state *crtc_state,
100			struct drm_connector_state *conn_state);
101	void (*enable)(struct dpu_encoder_phys *encoder);
102	void (*disable)(struct dpu_encoder_phys *encoder);
103	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
104	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
105	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
106	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
107	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
108	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
109	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
110	void (*irq_enable)(struct dpu_encoder_phys *phys);
111	void (*irq_disable)(struct dpu_encoder_phys *phys);
112	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
113	void (*restore)(struct dpu_encoder_phys *phys);
114	int (*get_line_count)(struct dpu_encoder_phys *phys);
115	int (*get_frame_count)(struct dpu_encoder_phys *phys);
116	void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
117			struct drm_writeback_job *job);
118	void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
119			struct drm_writeback_job *job);
120	bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
121};
122
123/**
124 * enum dpu_intr_idx - dpu encoder interrupt index
125 * @INTR_IDX_VSYNC:    Vsync interrupt for video mode panel
126 * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
127 * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
128 * @INTR_IDX_RDPTR:    Readpointer done interrupt for cmd mode panel
129 * @INTR_IDX_WB_DONE:  Writeback done interrupt for virtual connector
130 */
131enum dpu_intr_idx {
132	INTR_IDX_VSYNC,
133	INTR_IDX_PINGPONG,
134	INTR_IDX_UNDERRUN,
135	INTR_IDX_CTL_START,
136	INTR_IDX_RDPTR,
137	INTR_IDX_WB_DONE,
138	INTR_IDX_MAX,
139};
140
141/**
142 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
143 *	tied to a specific panel / sub-panel. Abstract type, sub-classed by
144 *	phys_vid or phys_cmd for video mode or command mode encs respectively.
145 * @parent:		Pointer to the containing virtual encoder
146 * @ops:		Operations exposed to the virtual encoder
147 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
148 * @hw_mdptop:		Hardware interface to the top registers
149 * @hw_ctl:		Hardware interface to the ctl registers
150 * @hw_pp:		Hardware interface to the ping pong registers
151 * @hw_intf:		Hardware interface to the intf registers
152 * @hw_wb:		Hardware interface to the wb registers
153 * @hw_cdm:		Hardware interface to the CDM registers
154 * @dpu_kms:		Pointer to the dpu_kms top level
155 * @cdm_cfg:		CDM block config needed to store WB/DP block's CDM configuration
156 * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
157 * @vblank_ctl_lock:	Vblank ctl mutex lock to protect vblank_refcount
158 * @enabled:		Whether the encoder has enabled and running a mode
159 * @split_role:		Role to play in a split-panel configuration
160 * @intf_mode:		Interface mode
161 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
162 * @enable_state:	Enable state tracking
163 * @vblank_refcount:	Reference count of vblank request
164 * @vsync_cnt:		Vsync count for the physical encoder
165 * @underrun_cnt:	Underrun count for the physical encoder
166 * @pending_kickoff_cnt:	Atomic counter tracking the number of kickoffs
167 *				vs. the number of done/vblank irqs. Should hover
168 *				between 0-2 Incremented when a new kickoff is
169 *				scheduled. Decremented in irq handler
170 * @pending_ctlstart_cnt:	Atomic counter tracking the number of ctl start
171 *                              pending.
172 * @pending_kickoff_wq:		Wait queue for blocking until kickoff completes
173 * @irq:			IRQ indices
174 * @has_intf_te:		Interface TE configuration support
175 */
176struct dpu_encoder_phys {
177	struct drm_encoder *parent;
178	struct dpu_encoder_phys_ops ops;
179	struct dpu_hw_mdp *hw_mdptop;
180	struct dpu_hw_ctl *hw_ctl;
181	struct dpu_hw_pingpong *hw_pp;
182	struct dpu_hw_intf *hw_intf;
183	struct dpu_hw_wb *hw_wb;
184	struct dpu_hw_cdm *hw_cdm;
185	struct dpu_kms *dpu_kms;
186	struct dpu_hw_cdm_cfg cdm_cfg;
187	struct drm_display_mode cached_mode;
188	struct mutex vblank_ctl_lock;
189	enum dpu_enc_split_role split_role;
190	enum dpu_intf_mode intf_mode;
191	spinlock_t *enc_spinlock;
192	enum dpu_enc_enable_state enable_state;
193	int vblank_refcount;
194	atomic_t vsync_cnt;
195	atomic_t underrun_cnt;
196	atomic_t pending_ctlstart_cnt;
197	atomic_t pending_kickoff_cnt;
198	wait_queue_head_t pending_kickoff_wq;
199	unsigned int irq[INTR_IDX_MAX];
200	bool has_intf_te;
201};
202
203static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
204{
205	atomic_inc_return(&phys->pending_ctlstart_cnt);
206	return atomic_inc_return(&phys->pending_kickoff_cnt);
207}
208
209/**
210 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
211 *	mode specific operations
212 * @base:	Baseclass physical encoder structure
213 * @wbirq_refcount:     Reference count of writeback interrupt
214 * @wb_done_timeout_cnt: number of wb done irq timeout errors
215 * @wb_cfg:  writeback block config to store fb related details
216 * @wb_conn: backpointer to writeback connector
217 * @wb_job: backpointer to current writeback job
218 * @dest:   dpu buffer layout for current writeback output buffer
219 */
220struct dpu_encoder_phys_wb {
221	struct dpu_encoder_phys base;
222	atomic_t wbirq_refcount;
223	int wb_done_timeout_cnt;
224	struct dpu_hw_wb_cfg wb_cfg;
225	struct drm_writeback_connector *wb_conn;
226	struct drm_writeback_job *wb_job;
227	struct dpu_hw_fmt_layout dest;
228};
229
230/**
231 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
232 *	mode specific operations
233 * @base:	Baseclass physical encoder structure
234 * @intf_idx:	Intf Block index used by this phys encoder
235 * @stream_sel:	Stream selection for multi-stream interfaces
236 * @serialize_wait4pp:	serialize wait4pp feature waits for pp_done interrupt
237 *			after ctl_start instead of before next frame kickoff
238 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
239 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
240 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
241 */
242struct dpu_encoder_phys_cmd {
243	struct dpu_encoder_phys base;
244	int stream_sel;
245	bool serialize_wait4pp;
246	int pp_timeout_report_cnt;
247	atomic_t pending_vblank_cnt;
248	wait_queue_head_t pending_vblank_wq;
249};
250
251/**
252 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
253 * @dpu_kms:		Pointer to the dpu_kms top level
254 * @parent:		Pointer to the containing virtual encoder
255 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
256 * @split_role:		Role to play in a split-panel configuration
257 * @hw_intf:		Hardware interface to the intf registers
258 * @hw_wb:		Hardware interface to the wb registers
259 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
260 */
261struct dpu_enc_phys_init_params {
262	struct dpu_kms *dpu_kms;
263	struct drm_encoder *parent;
264	enum dpu_enc_split_role split_role;
265	struct dpu_hw_intf *hw_intf;
266	struct dpu_hw_wb *hw_wb;
267	spinlock_t *enc_spinlock;
268};
269
270/**
271 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
272 * @wq: wait queue structure
273 * @atomic_cnt: wait until atomic_cnt equals zero
274 * @timeout_ms: timeout value in milliseconds
275 */
276struct dpu_encoder_wait_info {
277	wait_queue_head_t *wq;
278	atomic_t *atomic_cnt;
279	s64 timeout_ms;
280};
281
282struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev,
283		struct dpu_enc_phys_init_params *p);
284
285struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev,
286		struct dpu_enc_phys_init_params *p);
287
288struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
289		struct dpu_enc_phys_init_params *p);
290
291void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
292
293static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
294		struct dpu_encoder_phys *phys_enc)
295{
296	struct dpu_crtc_state *dpu_cstate;
297
298	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
299		return BLEND_3D_NONE;
300
301	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
302
303	/* Use merge_3d unless DSC MERGE topology is used */
304	if (phys_enc->split_role == ENC_ROLE_SOLO &&
305	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
306	    !dpu_encoder_use_dsc_merge(phys_enc->parent))
307		return BLEND_3D_H_ROW_INT;
308
309	return BLEND_3D_NONE;
310}
311
312unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
313
314struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc);
315
316u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc);
317
318bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc);
319
320void dpu_encoder_helper_split_config(
321		struct dpu_encoder_phys *phys_enc,
322		enum dpu_intf interface);
323
324void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
325		enum dpu_intr_idx intr_idx);
326
327int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
328		unsigned int irq,
329		void (*func)(void *arg),
330		struct dpu_encoder_wait_info *wait_info);
331
332void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
333
334void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
335				       const struct msm_format *dpu_fmt,
336				       u32 output_type);
337
338void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
339				 struct dpu_encoder_phys *phy_enc);
340
341void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
342				   struct dpu_encoder_phys *phy_enc);
343
344void dpu_encoder_frame_done_callback(
345		struct drm_encoder *drm_enc,
346		struct dpu_encoder_phys *ready_phys, u32 event);
347
348void dpu_encoder_phys_init(struct dpu_encoder_phys *phys,
349			   struct dpu_enc_phys_init_params *p);
350
351#endif /* __dpu_encoder_phys_H__ */