Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include <drm/drm_drv.h>
32#include <drm/drm_fb_helper.h>
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "atom.h"
36
37#include <linux/vga_switcheroo.h>
38#include <linux/slab.h>
39#include <linux/uaccess.h>
40#include <linux/pci.h>
41#include <linux/pm_runtime.h>
42#include "amdgpu_amdkfd.h"
43#include "amdgpu_gem.h"
44#include "amdgpu_display.h"
45#include "amdgpu_ras.h"
46#include "amdgpu_reset.h"
47#include "amd_pcie.h"
48
49void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
50{
51 struct amdgpu_gpu_instance *gpu_instance;
52 int i;
53
54 mutex_lock(&mgpu_info.mutex);
55
56 for (i = 0; i < mgpu_info.num_gpu; i++) {
57 gpu_instance = &(mgpu_info.gpu_ins[i]);
58 if (gpu_instance->adev == adev) {
59 mgpu_info.gpu_ins[i] =
60 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
61 mgpu_info.num_gpu--;
62 if (adev->flags & AMD_IS_APU)
63 mgpu_info.num_apu--;
64 else
65 mgpu_info.num_dgpu--;
66 break;
67 }
68 }
69
70 mutex_unlock(&mgpu_info.mutex);
71}
72
73/**
74 * amdgpu_driver_unload_kms - Main unload function for KMS.
75 *
76 * @dev: drm dev pointer
77 *
78 * This is the main unload function for KMS (all asics).
79 * Returns 0 on success.
80 */
81void amdgpu_driver_unload_kms(struct drm_device *dev)
82{
83 struct amdgpu_device *adev = drm_to_adev(dev);
84
85 if (adev == NULL)
86 return;
87
88 amdgpu_unregister_gpu_instance(adev);
89
90 if (adev->rmmio == NULL)
91 return;
92
93 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
94 DRM_WARN("smart shift update failed\n");
95
96 amdgpu_acpi_fini(adev);
97 amdgpu_device_fini_hw(adev);
98}
99
100void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
101{
102 struct amdgpu_gpu_instance *gpu_instance;
103
104 mutex_lock(&mgpu_info.mutex);
105
106 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
107 DRM_ERROR("Cannot register more gpu instance\n");
108 mutex_unlock(&mgpu_info.mutex);
109 return;
110 }
111
112 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
113 gpu_instance->adev = adev;
114 gpu_instance->mgpu_fan_enabled = 0;
115
116 mgpu_info.num_gpu++;
117 if (adev->flags & AMD_IS_APU)
118 mgpu_info.num_apu++;
119 else
120 mgpu_info.num_dgpu++;
121
122 mutex_unlock(&mgpu_info.mutex);
123}
124
125/**
126 * amdgpu_driver_load_kms - Main load function for KMS.
127 *
128 * @adev: pointer to struct amdgpu_device
129 * @flags: device flags
130 *
131 * This is the main load function for KMS (all asics).
132 * Returns 0 on success, error on failure.
133 */
134int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
135{
136 struct drm_device *dev;
137 int r, acpi_status;
138
139 dev = adev_to_drm(adev);
140
141 /* amdgpu_device_init should report only fatal error
142 * like memory allocation failure or iomapping failure,
143 * or memory manager initialization failure, it must
144 * properly initialize the GPU MC controller and permit
145 * VRAM allocation
146 */
147 r = amdgpu_device_init(adev, flags);
148 if (r) {
149 dev_err(dev->dev, "Fatal error during GPU init\n");
150 goto out;
151 }
152
153 amdgpu_device_detect_runtime_pm_mode(adev);
154
155 /* Call ACPI methods: require modeset init
156 * but failure is not fatal
157 */
158
159 acpi_status = amdgpu_acpi_init(adev);
160 if (acpi_status)
161 dev_dbg(dev->dev, "Error during ACPI methods call\n");
162
163 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
164 DRM_WARN("smart shift update failed\n");
165
166out:
167 if (r)
168 amdgpu_driver_unload_kms(dev);
169
170 return r;
171}
172
173static enum amd_ip_block_type
174 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)
175{
176 enum amd_ip_block_type type;
177
178 switch (ip) {
179 case AMDGPU_HW_IP_GFX:
180 type = AMD_IP_BLOCK_TYPE_GFX;
181 break;
182 case AMDGPU_HW_IP_COMPUTE:
183 type = AMD_IP_BLOCK_TYPE_GFX;
184 break;
185 case AMDGPU_HW_IP_DMA:
186 type = AMD_IP_BLOCK_TYPE_SDMA;
187 break;
188 case AMDGPU_HW_IP_UVD:
189 case AMDGPU_HW_IP_UVD_ENC:
190 type = AMD_IP_BLOCK_TYPE_UVD;
191 break;
192 case AMDGPU_HW_IP_VCE:
193 type = AMD_IP_BLOCK_TYPE_VCE;
194 break;
195 case AMDGPU_HW_IP_VCN_DEC:
196 case AMDGPU_HW_IP_VCN_ENC:
197 type = AMD_IP_BLOCK_TYPE_VCN;
198 break;
199 case AMDGPU_HW_IP_VCN_JPEG:
200 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
201 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
202 break;
203 default:
204 type = AMD_IP_BLOCK_TYPE_NUM;
205 break;
206 }
207
208 return type;
209}
210
211static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
212 struct drm_amdgpu_query_fw *query_fw,
213 struct amdgpu_device *adev)
214{
215 switch (query_fw->fw_type) {
216 case AMDGPU_INFO_FW_VCE:
217 fw_info->ver = adev->vce.fw_version;
218 fw_info->feature = adev->vce.fb_version;
219 break;
220 case AMDGPU_INFO_FW_UVD:
221 fw_info->ver = adev->uvd.fw_version;
222 fw_info->feature = 0;
223 break;
224 case AMDGPU_INFO_FW_VCN:
225 fw_info->ver = adev->vcn.fw_version;
226 fw_info->feature = 0;
227 break;
228 case AMDGPU_INFO_FW_GMC:
229 fw_info->ver = adev->gmc.fw_version;
230 fw_info->feature = 0;
231 break;
232 case AMDGPU_INFO_FW_GFX_ME:
233 fw_info->ver = adev->gfx.me_fw_version;
234 fw_info->feature = adev->gfx.me_feature_version;
235 break;
236 case AMDGPU_INFO_FW_GFX_PFP:
237 fw_info->ver = adev->gfx.pfp_fw_version;
238 fw_info->feature = adev->gfx.pfp_feature_version;
239 break;
240 case AMDGPU_INFO_FW_GFX_CE:
241 fw_info->ver = adev->gfx.ce_fw_version;
242 fw_info->feature = adev->gfx.ce_feature_version;
243 break;
244 case AMDGPU_INFO_FW_GFX_RLC:
245 fw_info->ver = adev->gfx.rlc_fw_version;
246 fw_info->feature = adev->gfx.rlc_feature_version;
247 break;
248 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
249 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
250 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
251 break;
252 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
253 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
254 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
255 break;
256 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
257 fw_info->ver = adev->gfx.rlc_srls_fw_version;
258 fw_info->feature = adev->gfx.rlc_srls_feature_version;
259 break;
260 case AMDGPU_INFO_FW_GFX_RLCP:
261 fw_info->ver = adev->gfx.rlcp_ucode_version;
262 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
263 break;
264 case AMDGPU_INFO_FW_GFX_RLCV:
265 fw_info->ver = adev->gfx.rlcv_ucode_version;
266 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
267 break;
268 case AMDGPU_INFO_FW_GFX_MEC:
269 if (query_fw->index == 0) {
270 fw_info->ver = adev->gfx.mec_fw_version;
271 fw_info->feature = adev->gfx.mec_feature_version;
272 } else if (query_fw->index == 1) {
273 fw_info->ver = adev->gfx.mec2_fw_version;
274 fw_info->feature = adev->gfx.mec2_feature_version;
275 } else
276 return -EINVAL;
277 break;
278 case AMDGPU_INFO_FW_SMC:
279 fw_info->ver = adev->pm.fw_version;
280 fw_info->feature = 0;
281 break;
282 case AMDGPU_INFO_FW_TA:
283 switch (query_fw->index) {
284 case TA_FW_TYPE_PSP_XGMI:
285 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
286 fw_info->feature = adev->psp.xgmi_context.context
287 .bin_desc.feature_version;
288 break;
289 case TA_FW_TYPE_PSP_RAS:
290 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
291 fw_info->feature = adev->psp.ras_context.context
292 .bin_desc.feature_version;
293 break;
294 case TA_FW_TYPE_PSP_HDCP:
295 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
296 fw_info->feature = adev->psp.hdcp_context.context
297 .bin_desc.feature_version;
298 break;
299 case TA_FW_TYPE_PSP_DTM:
300 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
301 fw_info->feature = adev->psp.dtm_context.context
302 .bin_desc.feature_version;
303 break;
304 case TA_FW_TYPE_PSP_RAP:
305 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
306 fw_info->feature = adev->psp.rap_context.context
307 .bin_desc.feature_version;
308 break;
309 case TA_FW_TYPE_PSP_SECUREDISPLAY:
310 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
311 fw_info->feature =
312 adev->psp.securedisplay_context.context.bin_desc
313 .feature_version;
314 break;
315 default:
316 return -EINVAL;
317 }
318 break;
319 case AMDGPU_INFO_FW_SDMA:
320 if (query_fw->index >= adev->sdma.num_instances)
321 return -EINVAL;
322 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
323 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
324 break;
325 case AMDGPU_INFO_FW_SOS:
326 fw_info->ver = adev->psp.sos.fw_version;
327 fw_info->feature = adev->psp.sos.feature_version;
328 break;
329 case AMDGPU_INFO_FW_ASD:
330 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
331 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
332 break;
333 case AMDGPU_INFO_FW_DMCU:
334 fw_info->ver = adev->dm.dmcu_fw_version;
335 fw_info->feature = 0;
336 break;
337 case AMDGPU_INFO_FW_DMCUB:
338 fw_info->ver = adev->dm.dmcub_fw_version;
339 fw_info->feature = 0;
340 break;
341 case AMDGPU_INFO_FW_TOC:
342 fw_info->ver = adev->psp.toc.fw_version;
343 fw_info->feature = adev->psp.toc.feature_version;
344 break;
345 case AMDGPU_INFO_FW_CAP:
346 fw_info->ver = adev->psp.cap_fw_version;
347 fw_info->feature = adev->psp.cap_feature_version;
348 break;
349 case AMDGPU_INFO_FW_MES_KIQ:
350 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
351 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
352 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
353 break;
354 case AMDGPU_INFO_FW_MES:
355 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
356 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
357 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
358 break;
359 case AMDGPU_INFO_FW_IMU:
360 fw_info->ver = adev->gfx.imu_fw_version;
361 fw_info->feature = 0;
362 break;
363 case AMDGPU_INFO_FW_VPE:
364 fw_info->ver = adev->vpe.fw_version;
365 fw_info->feature = adev->vpe.feature_version;
366 break;
367 default:
368 return -EINVAL;
369 }
370 return 0;
371}
372
373static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
374 struct drm_amdgpu_info *info,
375 struct drm_amdgpu_info_hw_ip *result)
376{
377 uint32_t ib_start_alignment = 0;
378 uint32_t ib_size_alignment = 0;
379 enum amd_ip_block_type type;
380 unsigned int num_rings = 0;
381 unsigned int i, j;
382
383 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
384 return -EINVAL;
385
386 switch (info->query_hw_ip.type) {
387 case AMDGPU_HW_IP_GFX:
388 type = AMD_IP_BLOCK_TYPE_GFX;
389 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
390 if (adev->gfx.gfx_ring[i].sched.ready)
391 ++num_rings;
392 ib_start_alignment = 32;
393 ib_size_alignment = 32;
394 break;
395 case AMDGPU_HW_IP_COMPUTE:
396 type = AMD_IP_BLOCK_TYPE_GFX;
397 for (i = 0; i < adev->gfx.num_compute_rings; i++)
398 if (adev->gfx.compute_ring[i].sched.ready)
399 ++num_rings;
400 ib_start_alignment = 32;
401 ib_size_alignment = 32;
402 break;
403 case AMDGPU_HW_IP_DMA:
404 type = AMD_IP_BLOCK_TYPE_SDMA;
405 for (i = 0; i < adev->sdma.num_instances; i++)
406 if (adev->sdma.instance[i].ring.sched.ready)
407 ++num_rings;
408 ib_start_alignment = 256;
409 ib_size_alignment = 4;
410 break;
411 case AMDGPU_HW_IP_UVD:
412 type = AMD_IP_BLOCK_TYPE_UVD;
413 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
414 if (adev->uvd.harvest_config & (1 << i))
415 continue;
416
417 if (adev->uvd.inst[i].ring.sched.ready)
418 ++num_rings;
419 }
420 ib_start_alignment = 256;
421 ib_size_alignment = 64;
422 break;
423 case AMDGPU_HW_IP_VCE:
424 type = AMD_IP_BLOCK_TYPE_VCE;
425 for (i = 0; i < adev->vce.num_rings; i++)
426 if (adev->vce.ring[i].sched.ready)
427 ++num_rings;
428 ib_start_alignment = 256;
429 ib_size_alignment = 4;
430 break;
431 case AMDGPU_HW_IP_UVD_ENC:
432 type = AMD_IP_BLOCK_TYPE_UVD;
433 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
434 if (adev->uvd.harvest_config & (1 << i))
435 continue;
436
437 for (j = 0; j < adev->uvd.num_enc_rings; j++)
438 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
439 ++num_rings;
440 }
441 ib_start_alignment = 256;
442 ib_size_alignment = 4;
443 break;
444 case AMDGPU_HW_IP_VCN_DEC:
445 type = AMD_IP_BLOCK_TYPE_VCN;
446 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
447 if (adev->vcn.harvest_config & (1 << i))
448 continue;
449
450 if (adev->vcn.inst[i].ring_dec.sched.ready)
451 ++num_rings;
452 }
453 ib_start_alignment = 256;
454 ib_size_alignment = 64;
455 break;
456 case AMDGPU_HW_IP_VCN_ENC:
457 type = AMD_IP_BLOCK_TYPE_VCN;
458 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
459 if (adev->vcn.harvest_config & (1 << i))
460 continue;
461
462 for (j = 0; j < adev->vcn.num_enc_rings; j++)
463 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
464 ++num_rings;
465 }
466 ib_start_alignment = 256;
467 ib_size_alignment = 4;
468 break;
469 case AMDGPU_HW_IP_VCN_JPEG:
470 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
471 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
472
473 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
474 if (adev->jpeg.harvest_config & (1 << i))
475 continue;
476
477 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
478 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
479 ++num_rings;
480 }
481 ib_start_alignment = 256;
482 ib_size_alignment = 64;
483 break;
484 case AMDGPU_HW_IP_VPE:
485 type = AMD_IP_BLOCK_TYPE_VPE;
486 if (adev->vpe.ring.sched.ready)
487 ++num_rings;
488 ib_start_alignment = 256;
489 ib_size_alignment = 4;
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 for (i = 0; i < adev->num_ip_blocks; i++)
496 if (adev->ip_blocks[i].version->type == type &&
497 adev->ip_blocks[i].status.valid)
498 break;
499
500 if (i == adev->num_ip_blocks)
501 return 0;
502
503 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
504 num_rings);
505
506 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
507 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
508
509 if (adev->asic_type >= CHIP_VEGA10) {
510 switch (type) {
511 case AMD_IP_BLOCK_TYPE_GFX:
512 result->ip_discovery_version =
513 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0));
514 break;
515 case AMD_IP_BLOCK_TYPE_SDMA:
516 result->ip_discovery_version =
517 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));
518 break;
519 case AMD_IP_BLOCK_TYPE_UVD:
520 case AMD_IP_BLOCK_TYPE_VCN:
521 case AMD_IP_BLOCK_TYPE_JPEG:
522 result->ip_discovery_version =
523 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
524 break;
525 case AMD_IP_BLOCK_TYPE_VCE:
526 result->ip_discovery_version =
527 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0));
528 break;
529 case AMD_IP_BLOCK_TYPE_VPE:
530 result->ip_discovery_version =
531 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
532 break;
533 default:
534 result->ip_discovery_version = 0;
535 break;
536 }
537 } else {
538 result->ip_discovery_version = 0;
539 }
540 result->capabilities_flags = 0;
541 result->available_rings = (1 << num_rings) - 1;
542 result->ib_start_alignment = ib_start_alignment;
543 result->ib_size_alignment = ib_size_alignment;
544 return 0;
545}
546
547/*
548 * Userspace get information ioctl
549 */
550/**
551 * amdgpu_info_ioctl - answer a device specific request.
552 *
553 * @dev: drm device pointer
554 * @data: request object
555 * @filp: drm filp
556 *
557 * This function is used to pass device specific parameters to the userspace
558 * drivers. Examples include: pci device id, pipeline parms, tiling params,
559 * etc. (all asics).
560 * Returns 0 on success, -EINVAL on failure.
561 */
562int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
563{
564 struct amdgpu_device *adev = drm_to_adev(dev);
565 struct drm_amdgpu_info *info = data;
566 struct amdgpu_mode_info *minfo = &adev->mode_info;
567 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
568 struct amdgpu_fpriv *fpriv;
569 struct amdgpu_ip_block *ip_block;
570 enum amd_ip_block_type type;
571 struct amdgpu_xcp *xcp;
572 u32 count, inst_mask;
573 uint32_t size = info->return_size;
574 struct drm_crtc *crtc;
575 uint32_t ui32 = 0;
576 uint64_t ui64 = 0;
577 int i, found, ret;
578 int ui32_size = sizeof(ui32);
579
580 if (!info->return_size || !info->return_pointer)
581 return -EINVAL;
582
583 switch (info->query) {
584 case AMDGPU_INFO_ACCEL_WORKING:
585 ui32 = adev->accel_working;
586 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
587 case AMDGPU_INFO_CRTC_FROM_ID:
588 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
589 crtc = (struct drm_crtc *)minfo->crtcs[i];
590 if (crtc && crtc->base.id == info->mode_crtc.id) {
591 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
592
593 ui32 = amdgpu_crtc->crtc_id;
594 found = 1;
595 break;
596 }
597 }
598 if (!found) {
599 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
600 return -EINVAL;
601 }
602 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
603 case AMDGPU_INFO_HW_IP_INFO: {
604 struct drm_amdgpu_info_hw_ip ip = {};
605
606 ret = amdgpu_hw_ip_info(adev, info, &ip);
607 if (ret)
608 return ret;
609
610 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
611 return ret ? -EFAULT : 0;
612 }
613 case AMDGPU_INFO_HW_IP_COUNT: {
614 fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
615 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
616 ip_block = amdgpu_device_ip_get_ip_block(adev, type);
617
618 if (!ip_block || !ip_block->status.valid)
619 return -EINVAL;
620
621 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
622 fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
623 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
624 switch (type) {
625 case AMD_IP_BLOCK_TYPE_GFX:
626 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
627 if (ret)
628 return ret;
629 count = hweight32(inst_mask);
630 break;
631 case AMD_IP_BLOCK_TYPE_SDMA:
632 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask);
633 if (ret)
634 return ret;
635 count = hweight32(inst_mask);
636 break;
637 case AMD_IP_BLOCK_TYPE_JPEG:
638 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
639 if (ret)
640 return ret;
641 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings;
642 break;
643 case AMD_IP_BLOCK_TYPE_VCN:
644 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
645 if (ret)
646 return ret;
647 count = hweight32(inst_mask);
648 break;
649 default:
650 return -EINVAL;
651 }
652
653 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
654 }
655
656 switch (type) {
657 case AMD_IP_BLOCK_TYPE_GFX:
658 case AMD_IP_BLOCK_TYPE_VCE:
659 count = 1;
660 break;
661 case AMD_IP_BLOCK_TYPE_SDMA:
662 count = adev->sdma.num_instances;
663 break;
664 case AMD_IP_BLOCK_TYPE_JPEG:
665 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings;
666 break;
667 case AMD_IP_BLOCK_TYPE_VCN:
668 count = adev->vcn.num_vcn_inst;
669 break;
670 case AMD_IP_BLOCK_TYPE_UVD:
671 count = adev->uvd.num_uvd_inst;
672 break;
673 /* For all other IP block types not listed in the switch statement
674 * the ip status is valid here and the instance count is one.
675 */
676 default:
677 count = 1;
678 break;
679 }
680
681 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
682 }
683 case AMDGPU_INFO_TIMESTAMP:
684 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
685 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
686 case AMDGPU_INFO_FW_VERSION: {
687 struct drm_amdgpu_info_firmware fw_info;
688
689 /* We only support one instance of each IP block right now. */
690 if (info->query_fw.ip_instance != 0)
691 return -EINVAL;
692
693 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
694 if (ret)
695 return ret;
696
697 return copy_to_user(out, &fw_info,
698 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
699 }
700 case AMDGPU_INFO_NUM_BYTES_MOVED:
701 ui64 = atomic64_read(&adev->num_bytes_moved);
702 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
703 case AMDGPU_INFO_NUM_EVICTIONS:
704 ui64 = atomic64_read(&adev->num_evictions);
705 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
706 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
707 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
708 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
709 case AMDGPU_INFO_VRAM_USAGE:
710 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
711 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
712 case AMDGPU_INFO_VIS_VRAM_USAGE:
713 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
714 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
715 case AMDGPU_INFO_GTT_USAGE:
716 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
717 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
718 case AMDGPU_INFO_GDS_CONFIG: {
719 struct drm_amdgpu_info_gds gds_info;
720
721 memset(&gds_info, 0, sizeof(gds_info));
722 gds_info.compute_partition_size = adev->gds.gds_size;
723 gds_info.gds_total_size = adev->gds.gds_size;
724 gds_info.gws_per_compute_partition = adev->gds.gws_size;
725 gds_info.oa_per_compute_partition = adev->gds.oa_size;
726 return copy_to_user(out, &gds_info,
727 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
728 }
729 case AMDGPU_INFO_VRAM_GTT: {
730 struct drm_amdgpu_info_vram_gtt vram_gtt;
731
732 vram_gtt.vram_size = adev->gmc.real_vram_size -
733 atomic64_read(&adev->vram_pin_size) -
734 AMDGPU_VM_RESERVED_VRAM;
735 vram_gtt.vram_cpu_accessible_size =
736 min(adev->gmc.visible_vram_size -
737 atomic64_read(&adev->visible_pin_size),
738 vram_gtt.vram_size);
739 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
740 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
741 return copy_to_user(out, &vram_gtt,
742 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
743 }
744 case AMDGPU_INFO_MEMORY: {
745 struct drm_amdgpu_memory_info mem;
746 struct ttm_resource_manager *gtt_man =
747 &adev->mman.gtt_mgr.manager;
748 struct ttm_resource_manager *vram_man =
749 &adev->mman.vram_mgr.manager;
750
751 memset(&mem, 0, sizeof(mem));
752 mem.vram.total_heap_size = adev->gmc.real_vram_size;
753 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
754 atomic64_read(&adev->vram_pin_size) -
755 AMDGPU_VM_RESERVED_VRAM;
756 mem.vram.heap_usage =
757 ttm_resource_manager_usage(vram_man);
758 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
759
760 mem.cpu_accessible_vram.total_heap_size =
761 adev->gmc.visible_vram_size;
762 mem.cpu_accessible_vram.usable_heap_size =
763 min(adev->gmc.visible_vram_size -
764 atomic64_read(&adev->visible_pin_size),
765 mem.vram.usable_heap_size);
766 mem.cpu_accessible_vram.heap_usage =
767 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
768 mem.cpu_accessible_vram.max_allocation =
769 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
770
771 mem.gtt.total_heap_size = gtt_man->size;
772 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
773 atomic64_read(&adev->gart_pin_size);
774 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
775 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
776
777 return copy_to_user(out, &mem,
778 min((size_t)size, sizeof(mem)))
779 ? -EFAULT : 0;
780 }
781 case AMDGPU_INFO_READ_MMR_REG: {
782 int ret = 0;
783 unsigned int n, alloc_size;
784 uint32_t *regs;
785 unsigned int se_num = (info->read_mmr_reg.instance >>
786 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
787 AMDGPU_INFO_MMR_SE_INDEX_MASK;
788 unsigned int sh_num = (info->read_mmr_reg.instance >>
789 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
790 AMDGPU_INFO_MMR_SH_INDEX_MASK;
791
792 if (!down_read_trylock(&adev->reset_domain->sem))
793 return -ENOENT;
794
795 /* set full masks if the userspace set all bits
796 * in the bitfields
797 */
798 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {
799 se_num = 0xffffffff;
800 } else if (se_num >= AMDGPU_GFX_MAX_SE) {
801 ret = -EINVAL;
802 goto out;
803 }
804
805 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {
806 sh_num = 0xffffffff;
807 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {
808 ret = -EINVAL;
809 goto out;
810 }
811
812 if (info->read_mmr_reg.count > 128) {
813 ret = -EINVAL;
814 goto out;
815 }
816
817 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
818 if (!regs) {
819 ret = -ENOMEM;
820 goto out;
821 }
822
823 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
824
825 amdgpu_gfx_off_ctrl(adev, false);
826 for (i = 0; i < info->read_mmr_reg.count; i++) {
827 if (amdgpu_asic_read_register(adev, se_num, sh_num,
828 info->read_mmr_reg.dword_offset + i,
829 ®s[i])) {
830 DRM_DEBUG_KMS("unallowed offset %#x\n",
831 info->read_mmr_reg.dword_offset + i);
832 kfree(regs);
833 amdgpu_gfx_off_ctrl(adev, true);
834 ret = -EFAULT;
835 goto out;
836 }
837 }
838 amdgpu_gfx_off_ctrl(adev, true);
839 n = copy_to_user(out, regs, min(size, alloc_size));
840 kfree(regs);
841 ret = (n ? -EFAULT : 0);
842out:
843 up_read(&adev->reset_domain->sem);
844 return ret;
845 }
846 case AMDGPU_INFO_DEV_INFO: {
847 struct drm_amdgpu_info_device *dev_info;
848 uint64_t vm_size;
849 uint32_t pcie_gen_mask;
850
851 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
852 if (!dev_info)
853 return -ENOMEM;
854
855 dev_info->device_id = adev->pdev->device;
856 dev_info->chip_rev = adev->rev_id;
857 dev_info->external_rev = adev->external_rev_id;
858 dev_info->pci_rev = adev->pdev->revision;
859 dev_info->family = adev->family;
860 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
861 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
862 /* return all clocks in KHz */
863 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
864 if (adev->pm.dpm_enabled) {
865 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
866 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
867 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
868 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
869 } else {
870 dev_info->max_engine_clock =
871 dev_info->min_engine_clock =
872 adev->clock.default_sclk * 10;
873 dev_info->max_memory_clock =
874 dev_info->min_memory_clock =
875 adev->clock.default_mclk * 10;
876 }
877 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
878 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
879 adev->gfx.config.max_shader_engines;
880 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
881 dev_info->ids_flags = 0;
882 if (adev->flags & AMD_IS_APU)
883 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
884 if (adev->gfx.mcbp)
885 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
886 if (amdgpu_is_tmz(adev))
887 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
888 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
889 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
890
891 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
892 vm_size -= AMDGPU_VA_RESERVED_TOP;
893
894 /* Older VCE FW versions are buggy and can handle only 40bits */
895 if (adev->vce.fw_version &&
896 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
897 vm_size = min(vm_size, 1ULL << 40);
898
899 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM;
900 dev_info->virtual_address_max =
901 min(vm_size, AMDGPU_GMC_HOLE_START);
902
903 if (vm_size > AMDGPU_GMC_HOLE_START) {
904 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
905 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
906 }
907 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
908 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
909 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
910 dev_info->cu_active_number = adev->gfx.cu_info.number;
911 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
912 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
913 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
914 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
915 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
916 sizeof(dev_info->cu_bitmap));
917 dev_info->vram_type = adev->gmc.vram_type;
918 dev_info->vram_bit_width = adev->gmc.vram_width;
919 dev_info->vce_harvest_config = adev->vce.harvest_config;
920 dev_info->gc_double_offchip_lds_buf =
921 adev->gfx.config.double_offchip_lds_buf;
922 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
923 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
924 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
925 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
926 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
927 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
928 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
929
930 if (adev->family >= AMDGPU_FAMILY_NV)
931 dev_info->pa_sc_tile_steering_override =
932 adev->gfx.config.pa_sc_tile_steering_override;
933
934 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
935
936 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
937 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
938 dev_info->pcie_gen = fls(pcie_gen_mask);
939 dev_info->pcie_num_lanes =
940 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
941 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
942 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
943 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
944 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
945 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
946
947 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
948 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
949 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
950 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
951 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
952 adev->gfx.config.gc_gl1c_per_sa;
953 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
954 dev_info->mall_size = adev->gmc.mall_size;
955
956
957 if (adev->gfx.funcs->get_gfx_shadow_info) {
958 struct amdgpu_gfx_shadow_info shadow_info;
959
960 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
961 if (!ret) {
962 dev_info->shadow_size = shadow_info.shadow_size;
963 dev_info->shadow_alignment = shadow_info.shadow_alignment;
964 dev_info->csa_size = shadow_info.csa_size;
965 dev_info->csa_alignment = shadow_info.csa_alignment;
966 }
967 }
968
969 ret = copy_to_user(out, dev_info,
970 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
971 kfree(dev_info);
972 return ret;
973 }
974 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
975 unsigned int i;
976 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
977 struct amd_vce_state *vce_state;
978
979 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
980 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
981 if (vce_state) {
982 vce_clk_table.entries[i].sclk = vce_state->sclk;
983 vce_clk_table.entries[i].mclk = vce_state->mclk;
984 vce_clk_table.entries[i].eclk = vce_state->evclk;
985 vce_clk_table.num_valid_entries++;
986 }
987 }
988
989 return copy_to_user(out, &vce_clk_table,
990 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
991 }
992 case AMDGPU_INFO_VBIOS: {
993 uint32_t bios_size = adev->bios_size;
994
995 switch (info->vbios_info.type) {
996 case AMDGPU_INFO_VBIOS_SIZE:
997 return copy_to_user(out, &bios_size,
998 min((size_t)size, sizeof(bios_size)))
999 ? -EFAULT : 0;
1000 case AMDGPU_INFO_VBIOS_IMAGE: {
1001 uint8_t *bios;
1002 uint32_t bios_offset = info->vbios_info.offset;
1003
1004 if (bios_offset >= bios_size)
1005 return -EINVAL;
1006
1007 bios = adev->bios + bios_offset;
1008 return copy_to_user(out, bios,
1009 min((size_t)size, (size_t)(bios_size - bios_offset)))
1010 ? -EFAULT : 0;
1011 }
1012 case AMDGPU_INFO_VBIOS_INFO: {
1013 struct drm_amdgpu_info_vbios vbios_info = {};
1014 struct atom_context *atom_context;
1015
1016 atom_context = adev->mode_info.atom_context;
1017 if (atom_context) {
1018 memcpy(vbios_info.name, atom_context->name,
1019 sizeof(atom_context->name));
1020 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
1021 sizeof(atom_context->vbios_pn));
1022 vbios_info.version = atom_context->version;
1023 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
1024 sizeof(atom_context->vbios_ver_str));
1025 memcpy(vbios_info.date, atom_context->date,
1026 sizeof(atom_context->date));
1027 }
1028
1029 return copy_to_user(out, &vbios_info,
1030 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
1031 }
1032 default:
1033 DRM_DEBUG_KMS("Invalid request %d\n",
1034 info->vbios_info.type);
1035 return -EINVAL;
1036 }
1037 }
1038 case AMDGPU_INFO_NUM_HANDLES: {
1039 struct drm_amdgpu_info_num_handles handle;
1040
1041 switch (info->query_hw_ip.type) {
1042 case AMDGPU_HW_IP_UVD:
1043 /* Starting Polaris, we support unlimited UVD handles */
1044 if (adev->asic_type < CHIP_POLARIS10) {
1045 handle.uvd_max_handles = adev->uvd.max_handles;
1046 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
1047
1048 return copy_to_user(out, &handle,
1049 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
1050 } else {
1051 return -ENODATA;
1052 }
1053
1054 break;
1055 default:
1056 return -EINVAL;
1057 }
1058 }
1059 case AMDGPU_INFO_SENSOR: {
1060 if (!adev->pm.dpm_enabled)
1061 return -ENOENT;
1062
1063 switch (info->sensor_info.type) {
1064 case AMDGPU_INFO_SENSOR_GFX_SCLK:
1065 /* get sclk in Mhz */
1066 if (amdgpu_dpm_read_sensor(adev,
1067 AMDGPU_PP_SENSOR_GFX_SCLK,
1068 (void *)&ui32, &ui32_size)) {
1069 return -EINVAL;
1070 }
1071 ui32 /= 100;
1072 break;
1073 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1074 /* get mclk in Mhz */
1075 if (amdgpu_dpm_read_sensor(adev,
1076 AMDGPU_PP_SENSOR_GFX_MCLK,
1077 (void *)&ui32, &ui32_size)) {
1078 return -EINVAL;
1079 }
1080 ui32 /= 100;
1081 break;
1082 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1083 /* get temperature in millidegrees C */
1084 if (amdgpu_dpm_read_sensor(adev,
1085 AMDGPU_PP_SENSOR_GPU_TEMP,
1086 (void *)&ui32, &ui32_size)) {
1087 return -EINVAL;
1088 }
1089 break;
1090 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1091 /* get GPU load */
1092 if (amdgpu_dpm_read_sensor(adev,
1093 AMDGPU_PP_SENSOR_GPU_LOAD,
1094 (void *)&ui32, &ui32_size)) {
1095 return -EINVAL;
1096 }
1097 break;
1098 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1099 /* get average GPU power */
1100 if (amdgpu_dpm_read_sensor(adev,
1101 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1102 (void *)&ui32, &ui32_size)) {
1103 /* fall back to input power for backwards compat */
1104 if (amdgpu_dpm_read_sensor(adev,
1105 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1106 (void *)&ui32, &ui32_size)) {
1107 return -EINVAL;
1108 }
1109 }
1110 ui32 >>= 8;
1111 break;
1112 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER:
1113 /* get input GPU power */
1114 if (amdgpu_dpm_read_sensor(adev,
1115 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1116 (void *)&ui32, &ui32_size)) {
1117 return -EINVAL;
1118 }
1119 ui32 >>= 8;
1120 break;
1121 case AMDGPU_INFO_SENSOR_VDDNB:
1122 /* get VDDNB in millivolts */
1123 if (amdgpu_dpm_read_sensor(adev,
1124 AMDGPU_PP_SENSOR_VDDNB,
1125 (void *)&ui32, &ui32_size)) {
1126 return -EINVAL;
1127 }
1128 break;
1129 case AMDGPU_INFO_SENSOR_VDDGFX:
1130 /* get VDDGFX in millivolts */
1131 if (amdgpu_dpm_read_sensor(adev,
1132 AMDGPU_PP_SENSOR_VDDGFX,
1133 (void *)&ui32, &ui32_size)) {
1134 return -EINVAL;
1135 }
1136 break;
1137 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1138 /* get stable pstate sclk in Mhz */
1139 if (amdgpu_dpm_read_sensor(adev,
1140 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1141 (void *)&ui32, &ui32_size)) {
1142 return -EINVAL;
1143 }
1144 ui32 /= 100;
1145 break;
1146 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1147 /* get stable pstate mclk in Mhz */
1148 if (amdgpu_dpm_read_sensor(adev,
1149 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1150 (void *)&ui32, &ui32_size)) {
1151 return -EINVAL;
1152 }
1153 ui32 /= 100;
1154 break;
1155 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1156 /* get peak pstate sclk in Mhz */
1157 if (amdgpu_dpm_read_sensor(adev,
1158 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1159 (void *)&ui32, &ui32_size)) {
1160 return -EINVAL;
1161 }
1162 ui32 /= 100;
1163 break;
1164 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1165 /* get peak pstate mclk in Mhz */
1166 if (amdgpu_dpm_read_sensor(adev,
1167 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1168 (void *)&ui32, &ui32_size)) {
1169 return -EINVAL;
1170 }
1171 ui32 /= 100;
1172 break;
1173 default:
1174 DRM_DEBUG_KMS("Invalid request %d\n",
1175 info->sensor_info.type);
1176 return -EINVAL;
1177 }
1178 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1179 }
1180 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1181 ui32 = atomic_read(&adev->vram_lost_counter);
1182 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1183 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1184 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1185 uint64_t ras_mask;
1186
1187 if (!ras)
1188 return -EINVAL;
1189 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1190
1191 return copy_to_user(out, &ras_mask,
1192 min_t(u64, size, sizeof(ras_mask))) ?
1193 -EFAULT : 0;
1194 }
1195 case AMDGPU_INFO_VIDEO_CAPS: {
1196 const struct amdgpu_video_codecs *codecs;
1197 struct drm_amdgpu_info_video_caps *caps;
1198 int r;
1199
1200 if (!adev->asic_funcs->query_video_codecs)
1201 return -EINVAL;
1202
1203 switch (info->video_cap.type) {
1204 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1205 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1206 if (r)
1207 return -EINVAL;
1208 break;
1209 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1210 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1211 if (r)
1212 return -EINVAL;
1213 break;
1214 default:
1215 DRM_DEBUG_KMS("Invalid request %d\n",
1216 info->video_cap.type);
1217 return -EINVAL;
1218 }
1219
1220 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1221 if (!caps)
1222 return -ENOMEM;
1223
1224 for (i = 0; i < codecs->codec_count; i++) {
1225 int idx = codecs->codec_array[i].codec_type;
1226
1227 switch (idx) {
1228 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1229 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1230 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1231 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1232 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1233 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1234 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1235 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1236 caps->codec_info[idx].valid = 1;
1237 caps->codec_info[idx].max_width =
1238 codecs->codec_array[i].max_width;
1239 caps->codec_info[idx].max_height =
1240 codecs->codec_array[i].max_height;
1241 caps->codec_info[idx].max_pixels_per_frame =
1242 codecs->codec_array[i].max_pixels_per_frame;
1243 caps->codec_info[idx].max_level =
1244 codecs->codec_array[i].max_level;
1245 break;
1246 default:
1247 break;
1248 }
1249 }
1250 r = copy_to_user(out, caps,
1251 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1252 kfree(caps);
1253 return r;
1254 }
1255 case AMDGPU_INFO_MAX_IBS: {
1256 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1257
1258 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1259 max_ibs[i] = amdgpu_ring_max_ibs(i);
1260
1261 return copy_to_user(out, max_ibs,
1262 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1263 }
1264 case AMDGPU_INFO_GPUVM_FAULT: {
1265 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1266 struct amdgpu_vm *vm = &fpriv->vm;
1267 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault;
1268 unsigned long flags;
1269
1270 if (!vm)
1271 return -EINVAL;
1272
1273 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault));
1274
1275 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
1276 gpuvm_fault.addr = vm->fault_info.addr;
1277 gpuvm_fault.status = vm->fault_info.status;
1278 gpuvm_fault.vmhub = vm->fault_info.vmhub;
1279 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
1280
1281 return copy_to_user(out, &gpuvm_fault,
1282 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
1283 }
1284 default:
1285 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1286 return -EINVAL;
1287 }
1288 return 0;
1289}
1290
1291/**
1292 * amdgpu_driver_open_kms - drm callback for open
1293 *
1294 * @dev: drm dev pointer
1295 * @file_priv: drm file
1296 *
1297 * On device open, init vm on cayman+ (all asics).
1298 * Returns 0 on success, error on failure.
1299 */
1300int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1301{
1302 struct amdgpu_device *adev = drm_to_adev(dev);
1303 struct amdgpu_fpriv *fpriv;
1304 int r, pasid;
1305
1306 /* Ensure IB tests are run on ring */
1307 flush_delayed_work(&adev->delayed_init_work);
1308
1309
1310 if (amdgpu_ras_intr_triggered()) {
1311 DRM_ERROR("RAS Intr triggered, device disabled!!");
1312 return -EHWPOISON;
1313 }
1314
1315 file_priv->driver_priv = NULL;
1316
1317 r = pm_runtime_get_sync(dev->dev);
1318 if (r < 0)
1319 goto pm_put;
1320
1321 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1322 if (unlikely(!fpriv)) {
1323 r = -ENOMEM;
1324 goto out_suspend;
1325 }
1326
1327 pasid = amdgpu_pasid_alloc(16);
1328 if (pasid < 0) {
1329 dev_warn(adev->dev, "No more PASIDs available!");
1330 pasid = 0;
1331 }
1332
1333 r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1334 if (r)
1335 goto error_pasid;
1336
1337 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1338 if (r)
1339 goto error_pasid;
1340
1341 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1342 if (r)
1343 goto error_vm;
1344
1345 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1346 if (!fpriv->prt_va) {
1347 r = -ENOMEM;
1348 goto error_vm;
1349 }
1350
1351 if (adev->gfx.mcbp) {
1352 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1353
1354 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1355 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1356 if (r)
1357 goto error_vm;
1358 }
1359
1360 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va);
1361 if (r)
1362 goto error_vm;
1363
1364 mutex_init(&fpriv->bo_list_lock);
1365 idr_init_base(&fpriv->bo_list_handles, 1);
1366
1367 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1368
1369 file_priv->driver_priv = fpriv;
1370 goto out_suspend;
1371
1372error_vm:
1373 amdgpu_vm_fini(adev, &fpriv->vm);
1374
1375error_pasid:
1376 if (pasid) {
1377 amdgpu_pasid_free(pasid);
1378 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1379 }
1380
1381 kfree(fpriv);
1382
1383out_suspend:
1384 pm_runtime_mark_last_busy(dev->dev);
1385pm_put:
1386 pm_runtime_put_autosuspend(dev->dev);
1387
1388 return r;
1389}
1390
1391/**
1392 * amdgpu_driver_postclose_kms - drm callback for post close
1393 *
1394 * @dev: drm dev pointer
1395 * @file_priv: drm file
1396 *
1397 * On device post close, tear down vm on cayman+ (all asics).
1398 */
1399void amdgpu_driver_postclose_kms(struct drm_device *dev,
1400 struct drm_file *file_priv)
1401{
1402 struct amdgpu_device *adev = drm_to_adev(dev);
1403 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1404 struct amdgpu_bo_list *list;
1405 struct amdgpu_bo *pd;
1406 u32 pasid;
1407 int handle;
1408
1409 if (!fpriv)
1410 return;
1411
1412 pm_runtime_get_sync(dev->dev);
1413
1414 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1415 amdgpu_uvd_free_handles(adev, file_priv);
1416 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1417 amdgpu_vce_free_handles(adev, file_priv);
1418
1419 if (fpriv->csa_va) {
1420 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1421
1422 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1423 fpriv->csa_va, csa_addr));
1424 fpriv->csa_va = NULL;
1425 }
1426
1427 amdgpu_seq64_unmap(adev, fpriv);
1428
1429 pasid = fpriv->vm.pasid;
1430 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1431 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1432 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1433 amdgpu_bo_unreserve(pd);
1434 }
1435
1436 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1437 amdgpu_vm_fini(adev, &fpriv->vm);
1438
1439 if (pasid)
1440 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1441 amdgpu_bo_unref(&pd);
1442
1443 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1444 amdgpu_bo_list_put(list);
1445
1446 idr_destroy(&fpriv->bo_list_handles);
1447 mutex_destroy(&fpriv->bo_list_lock);
1448
1449 kfree(fpriv);
1450 file_priv->driver_priv = NULL;
1451
1452 pm_runtime_mark_last_busy(dev->dev);
1453 pm_runtime_put_autosuspend(dev->dev);
1454}
1455
1456
1457void amdgpu_driver_release_kms(struct drm_device *dev)
1458{
1459 struct amdgpu_device *adev = drm_to_adev(dev);
1460
1461 amdgpu_device_fini_sw(adev);
1462 pci_set_drvdata(adev->pdev, NULL);
1463}
1464
1465/*
1466 * VBlank related functions.
1467 */
1468/**
1469 * amdgpu_get_vblank_counter_kms - get frame count
1470 *
1471 * @crtc: crtc to get the frame count from
1472 *
1473 * Gets the frame count on the requested crtc (all asics).
1474 * Returns frame count on success, -EINVAL on failure.
1475 */
1476u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1477{
1478 struct drm_device *dev = crtc->dev;
1479 unsigned int pipe = crtc->index;
1480 struct amdgpu_device *adev = drm_to_adev(dev);
1481 int vpos, hpos, stat;
1482 u32 count;
1483
1484 if (pipe >= adev->mode_info.num_crtc) {
1485 DRM_ERROR("Invalid crtc %u\n", pipe);
1486 return -EINVAL;
1487 }
1488
1489 /* The hw increments its frame counter at start of vsync, not at start
1490 * of vblank, as is required by DRM core vblank counter handling.
1491 * Cook the hw count here to make it appear to the caller as if it
1492 * incremented at start of vblank. We measure distance to start of
1493 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1494 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1495 * result by 1 to give the proper appearance to caller.
1496 */
1497 if (adev->mode_info.crtcs[pipe]) {
1498 /* Repeat readout if needed to provide stable result if
1499 * we cross start of vsync during the queries.
1500 */
1501 do {
1502 count = amdgpu_display_vblank_get_counter(adev, pipe);
1503 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1504 * vpos as distance to start of vblank, instead of
1505 * regular vertical scanout pos.
1506 */
1507 stat = amdgpu_display_get_crtc_scanoutpos(
1508 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1509 &vpos, &hpos, NULL, NULL,
1510 &adev->mode_info.crtcs[pipe]->base.hwmode);
1511 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1512
1513 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1514 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1515 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1516 } else {
1517 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1518 pipe, vpos);
1519
1520 /* Bump counter if we are at >= leading edge of vblank,
1521 * but before vsync where vpos would turn negative and
1522 * the hw counter really increments.
1523 */
1524 if (vpos >= 0)
1525 count++;
1526 }
1527 } else {
1528 /* Fallback to use value as is. */
1529 count = amdgpu_display_vblank_get_counter(adev, pipe);
1530 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1531 }
1532
1533 return count;
1534}
1535
1536/**
1537 * amdgpu_enable_vblank_kms - enable vblank interrupt
1538 *
1539 * @crtc: crtc to enable vblank interrupt for
1540 *
1541 * Enable the interrupt on the requested crtc (all asics).
1542 * Returns 0 on success, -EINVAL on failure.
1543 */
1544int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1545{
1546 struct drm_device *dev = crtc->dev;
1547 unsigned int pipe = crtc->index;
1548 struct amdgpu_device *adev = drm_to_adev(dev);
1549 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1550
1551 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1552}
1553
1554/**
1555 * amdgpu_disable_vblank_kms - disable vblank interrupt
1556 *
1557 * @crtc: crtc to disable vblank interrupt for
1558 *
1559 * Disable the interrupt on the requested crtc (all asics).
1560 */
1561void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1562{
1563 struct drm_device *dev = crtc->dev;
1564 unsigned int pipe = crtc->index;
1565 struct amdgpu_device *adev = drm_to_adev(dev);
1566 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1567
1568 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1569}
1570
1571/*
1572 * Debugfs info
1573 */
1574#if defined(CONFIG_DEBUG_FS)
1575
1576static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1577{
1578 struct amdgpu_device *adev = m->private;
1579 struct drm_amdgpu_info_firmware fw_info;
1580 struct drm_amdgpu_query_fw query_fw;
1581 struct atom_context *ctx = adev->mode_info.atom_context;
1582 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1583 int ret, i;
1584
1585 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1586#define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1587 TA_FW_NAME(XGMI),
1588 TA_FW_NAME(RAS),
1589 TA_FW_NAME(HDCP),
1590 TA_FW_NAME(DTM),
1591 TA_FW_NAME(RAP),
1592 TA_FW_NAME(SECUREDISPLAY),
1593#undef TA_FW_NAME
1594 };
1595
1596 /* VCE */
1597 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1598 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1599 if (ret)
1600 return ret;
1601 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1602 fw_info.feature, fw_info.ver);
1603
1604 /* UVD */
1605 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1606 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1607 if (ret)
1608 return ret;
1609 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1610 fw_info.feature, fw_info.ver);
1611
1612 /* GMC */
1613 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1614 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1615 if (ret)
1616 return ret;
1617 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1618 fw_info.feature, fw_info.ver);
1619
1620 /* ME */
1621 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1622 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1623 if (ret)
1624 return ret;
1625 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1626 fw_info.feature, fw_info.ver);
1627
1628 /* PFP */
1629 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1630 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1631 if (ret)
1632 return ret;
1633 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1634 fw_info.feature, fw_info.ver);
1635
1636 /* CE */
1637 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1638 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1639 if (ret)
1640 return ret;
1641 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1642 fw_info.feature, fw_info.ver);
1643
1644 /* RLC */
1645 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1646 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1647 if (ret)
1648 return ret;
1649 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1650 fw_info.feature, fw_info.ver);
1651
1652 /* RLC SAVE RESTORE LIST CNTL */
1653 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1654 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1655 if (ret)
1656 return ret;
1657 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1658 fw_info.feature, fw_info.ver);
1659
1660 /* RLC SAVE RESTORE LIST GPM MEM */
1661 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1662 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1663 if (ret)
1664 return ret;
1665 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1666 fw_info.feature, fw_info.ver);
1667
1668 /* RLC SAVE RESTORE LIST SRM MEM */
1669 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1670 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1671 if (ret)
1672 return ret;
1673 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1674 fw_info.feature, fw_info.ver);
1675
1676 /* RLCP */
1677 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1678 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1679 if (ret)
1680 return ret;
1681 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1682 fw_info.feature, fw_info.ver);
1683
1684 /* RLCV */
1685 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1686 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1687 if (ret)
1688 return ret;
1689 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1690 fw_info.feature, fw_info.ver);
1691
1692 /* MEC */
1693 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1694 query_fw.index = 0;
1695 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1696 if (ret)
1697 return ret;
1698 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1699 fw_info.feature, fw_info.ver);
1700
1701 /* MEC2 */
1702 if (adev->gfx.mec2_fw) {
1703 query_fw.index = 1;
1704 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1705 if (ret)
1706 return ret;
1707 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1708 fw_info.feature, fw_info.ver);
1709 }
1710
1711 /* IMU */
1712 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1713 query_fw.index = 0;
1714 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1715 if (ret)
1716 return ret;
1717 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1718 fw_info.feature, fw_info.ver);
1719
1720 /* PSP SOS */
1721 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1722 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1723 if (ret)
1724 return ret;
1725 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1726 fw_info.feature, fw_info.ver);
1727
1728
1729 /* PSP ASD */
1730 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1731 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1732 if (ret)
1733 return ret;
1734 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1735 fw_info.feature, fw_info.ver);
1736
1737 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1738 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1739 query_fw.index = i;
1740 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1741 if (ret)
1742 continue;
1743
1744 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1745 ta_fw_name[i], fw_info.feature, fw_info.ver);
1746 }
1747
1748 /* SMC */
1749 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1750 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1751 if (ret)
1752 return ret;
1753 smu_program = (fw_info.ver >> 24) & 0xff;
1754 smu_major = (fw_info.ver >> 16) & 0xff;
1755 smu_minor = (fw_info.ver >> 8) & 0xff;
1756 smu_debug = (fw_info.ver >> 0) & 0xff;
1757 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1758 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1759
1760 /* SDMA */
1761 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1762 for (i = 0; i < adev->sdma.num_instances; i++) {
1763 query_fw.index = i;
1764 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1765 if (ret)
1766 return ret;
1767 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1768 i, fw_info.feature, fw_info.ver);
1769 }
1770
1771 /* VCN */
1772 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1773 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1774 if (ret)
1775 return ret;
1776 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1777 fw_info.feature, fw_info.ver);
1778
1779 /* DMCU */
1780 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1781 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1782 if (ret)
1783 return ret;
1784 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1785 fw_info.feature, fw_info.ver);
1786
1787 /* DMCUB */
1788 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1789 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1790 if (ret)
1791 return ret;
1792 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1793 fw_info.feature, fw_info.ver);
1794
1795 /* TOC */
1796 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1797 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1798 if (ret)
1799 return ret;
1800 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1801 fw_info.feature, fw_info.ver);
1802
1803 /* CAP */
1804 if (adev->psp.cap_fw) {
1805 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1806 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1807 if (ret)
1808 return ret;
1809 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1810 fw_info.feature, fw_info.ver);
1811 }
1812
1813 /* MES_KIQ */
1814 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1815 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1816 if (ret)
1817 return ret;
1818 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1819 fw_info.feature, fw_info.ver);
1820
1821 /* MES */
1822 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1823 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1824 if (ret)
1825 return ret;
1826 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1827 fw_info.feature, fw_info.ver);
1828
1829 /* VPE */
1830 query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1831 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1832 if (ret)
1833 return ret;
1834 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1835 fw_info.feature, fw_info.ver);
1836
1837 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1838
1839 return 0;
1840}
1841
1842DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1843
1844#endif
1845
1846void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1847{
1848#if defined(CONFIG_DEBUG_FS)
1849 struct drm_minor *minor = adev_to_drm(adev)->primary;
1850 struct dentry *root = minor->debugfs_root;
1851
1852 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1853 adev, &amdgpu_debugfs_firmware_info_fops);
1854
1855#endif
1856}