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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD CPU Microcode Update Driver for Linux
4 *
5 * This driver allows to upgrade microcode on F10h AMD
6 * CPUs and later.
7 *
8 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * 2013-2018 Borislav Petkov <bp@alien8.de>
10 *
11 * Author: Peter Oruba <peter.oruba@amd.com>
12 *
13 * Based on work by:
14 * Tigran Aivazian <aivazian.tigran@gmail.com>
15 *
16 * early loader:
17 * Copyright (C) 2013 Advanced Micro Devices, Inc.
18 *
19 * Author: Jacob Shin <jacob.shin@amd.com>
20 * Fixes: Borislav Petkov <bp@suse.de>
21 */
22#define pr_fmt(fmt) "microcode: " fmt
23
24#include <linux/earlycpio.h>
25#include <linux/firmware.h>
26#include <linux/bsearch.h>
27#include <linux/uaccess.h>
28#include <linux/vmalloc.h>
29#include <linux/initrd.h>
30#include <linux/kernel.h>
31#include <linux/pci.h>
32
33#include <crypto/sha2.h>
34
35#include <asm/microcode.h>
36#include <asm/processor.h>
37#include <asm/cmdline.h>
38#include <asm/setup.h>
39#include <asm/cpu.h>
40#include <asm/msr.h>
41#include <asm/tlb.h>
42
43#include "internal.h"
44
45struct ucode_patch {
46 struct list_head plist;
47 void *data;
48 unsigned int size;
49 u32 patch_id;
50 u16 equiv_cpu;
51};
52
53static LIST_HEAD(microcode_cache);
54
55#define UCODE_MAGIC 0x00414d44
56#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
57#define UCODE_UCODE_TYPE 0x00000001
58
59#define SECTION_HDR_SIZE 8
60#define CONTAINER_HDR_SZ 12
61
62struct equiv_cpu_entry {
63 u32 installed_cpu;
64 u32 fixed_errata_mask;
65 u32 fixed_errata_compare;
66 u16 equiv_cpu;
67 u16 res;
68} __packed;
69
70struct microcode_header_amd {
71 u32 data_code;
72 u32 patch_id;
73 u16 mc_patch_data_id;
74 u8 mc_patch_data_len;
75 u8 init_flag;
76 u32 mc_patch_data_checksum;
77 u32 nb_dev_id;
78 u32 sb_dev_id;
79 u16 processor_rev_id;
80 u8 nb_rev_id;
81 u8 sb_rev_id;
82 u8 bios_api_rev;
83 u8 reserved1[3];
84 u32 match_reg[8];
85} __packed;
86
87struct microcode_amd {
88 struct microcode_header_amd hdr;
89 unsigned int mpb[];
90};
91
92static struct equiv_cpu_table {
93 unsigned int num_entries;
94 struct equiv_cpu_entry *entry;
95} equiv_table;
96
97union zen_patch_rev {
98 struct {
99 __u32 rev : 8,
100 stepping : 4,
101 model : 4,
102 __reserved : 4,
103 ext_model : 4,
104 ext_fam : 8;
105 };
106 __u32 ucode_rev;
107};
108
109union cpuid_1_eax {
110 struct {
111 __u32 stepping : 4,
112 model : 4,
113 family : 4,
114 __reserved0 : 4,
115 ext_model : 4,
116 ext_fam : 8,
117 __reserved1 : 4;
118 };
119 __u32 full;
120};
121
122/*
123 * This points to the current valid container of microcode patches which we will
124 * save from the initrd/builtin before jettisoning its contents. @mc is the
125 * microcode patch we found to match.
126 */
127struct cont_desc {
128 struct microcode_amd *mc;
129 u32 psize;
130 u8 *data;
131 size_t size;
132};
133
134/*
135 * Microcode patch container file is prepended to the initrd in cpio
136 * format. See Documentation/arch/x86/microcode.rst
137 */
138static const char
139ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
140
141/*
142 * This is CPUID(1).EAX on the BSP. It is used in two ways:
143 *
144 * 1. To ignore the equivalence table on Zen1 and newer.
145 *
146 * 2. To match which patches to load because the patch revision ID
147 * already contains the f/m/s for which the microcode is destined
148 * for.
149 */
150static u32 bsp_cpuid_1_eax __ro_after_init;
151
152static bool sha_check = true;
153
154struct patch_digest {
155 u32 patch_id;
156 u8 sha256[SHA256_DIGEST_SIZE];
157};
158
159#include "amd_shas.c"
160
161static int cmp_id(const void *key, const void *elem)
162{
163 struct patch_digest *pd = (struct patch_digest *)elem;
164 u32 patch_id = *(u32 *)key;
165
166 if (patch_id == pd->patch_id)
167 return 0;
168 else if (patch_id < pd->patch_id)
169 return -1;
170 else
171 return 1;
172}
173
174static bool need_sha_check(u32 cur_rev)
175{
176 switch (cur_rev >> 8) {
177 case 0x80012: return cur_rev <= 0x800126f; break;
178 case 0x80082: return cur_rev <= 0x800820f; break;
179 case 0x83010: return cur_rev <= 0x830107c; break;
180 case 0x86001: return cur_rev <= 0x860010e; break;
181 case 0x86081: return cur_rev <= 0x8608108; break;
182 case 0x87010: return cur_rev <= 0x8701034; break;
183 case 0x8a000: return cur_rev <= 0x8a0000a; break;
184 case 0xa0010: return cur_rev <= 0xa00107a; break;
185 case 0xa0011: return cur_rev <= 0xa0011da; break;
186 case 0xa0012: return cur_rev <= 0xa001243; break;
187 case 0xa0082: return cur_rev <= 0xa00820e; break;
188 case 0xa1011: return cur_rev <= 0xa101153; break;
189 case 0xa1012: return cur_rev <= 0xa10124e; break;
190 case 0xa1081: return cur_rev <= 0xa108109; break;
191 case 0xa2010: return cur_rev <= 0xa20102f; break;
192 case 0xa2012: return cur_rev <= 0xa201212; break;
193 case 0xa4041: return cur_rev <= 0xa404109; break;
194 case 0xa5000: return cur_rev <= 0xa500013; break;
195 case 0xa6012: return cur_rev <= 0xa60120a; break;
196 case 0xa7041: return cur_rev <= 0xa704109; break;
197 case 0xa7052: return cur_rev <= 0xa705208; break;
198 case 0xa7080: return cur_rev <= 0xa708009; break;
199 case 0xa70c0: return cur_rev <= 0xa70C009; break;
200 case 0xaa001: return cur_rev <= 0xaa00116; break;
201 case 0xaa002: return cur_rev <= 0xaa00218; break;
202 default: break;
203 }
204
205 pr_info("You should not be seeing this. Please send the following couple of lines to x86-<at>-kernel.org\n");
206 pr_info("CPUID(1).EAX: 0x%x, current revision: 0x%x\n", bsp_cpuid_1_eax, cur_rev);
207 return true;
208}
209
210static bool verify_sha256_digest(u32 patch_id, u32 cur_rev, const u8 *data, unsigned int len)
211{
212 struct patch_digest *pd = NULL;
213 u8 digest[SHA256_DIGEST_SIZE];
214 struct sha256_state s;
215 int i;
216
217 if (x86_family(bsp_cpuid_1_eax) < 0x17 ||
218 x86_family(bsp_cpuid_1_eax) > 0x19)
219 return true;
220
221 if (!need_sha_check(cur_rev))
222 return true;
223
224 if (!sha_check)
225 return true;
226
227 pd = bsearch(&patch_id, phashes, ARRAY_SIZE(phashes), sizeof(struct patch_digest), cmp_id);
228 if (!pd) {
229 pr_err("No sha256 digest for patch ID: 0x%x found\n", patch_id);
230 return false;
231 }
232
233 sha256_init(&s);
234 sha256_update(&s, data, len);
235 sha256_final(&s, digest);
236
237 if (memcmp(digest, pd->sha256, sizeof(digest))) {
238 pr_err("Patch 0x%x SHA256 digest mismatch!\n", patch_id);
239
240 for (i = 0; i < SHA256_DIGEST_SIZE; i++)
241 pr_cont("0x%x ", digest[i]);
242 pr_info("\n");
243
244 return false;
245 }
246
247 return true;
248}
249
250static u32 get_patch_level(void)
251{
252 u32 rev, dummy __always_unused;
253
254 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
255
256 return rev;
257}
258
259static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val)
260{
261 union zen_patch_rev p;
262 union cpuid_1_eax c;
263
264 p.ucode_rev = val;
265 c.full = 0;
266
267 c.stepping = p.stepping;
268 c.model = p.model;
269 c.ext_model = p.ext_model;
270 c.family = 0xf;
271 c.ext_fam = p.ext_fam;
272
273 return c;
274}
275
276static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
277{
278 unsigned int i;
279
280 /* Zen and newer do not need an equivalence table. */
281 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
282 return 0;
283
284 if (!et || !et->num_entries)
285 return 0;
286
287 for (i = 0; i < et->num_entries; i++) {
288 struct equiv_cpu_entry *e = &et->entry[i];
289
290 if (sig == e->installed_cpu)
291 return e->equiv_cpu;
292 }
293 return 0;
294}
295
296/*
297 * Check whether there is a valid microcode container file at the beginning
298 * of @buf of size @buf_size.
299 */
300static bool verify_container(const u8 *buf, size_t buf_size)
301{
302 u32 cont_magic;
303
304 if (buf_size <= CONTAINER_HDR_SZ) {
305 pr_debug("Truncated microcode container header.\n");
306 return false;
307 }
308
309 cont_magic = *(const u32 *)buf;
310 if (cont_magic != UCODE_MAGIC) {
311 pr_debug("Invalid magic value (0x%08x).\n", cont_magic);
312 return false;
313 }
314
315 return true;
316}
317
318/*
319 * Check whether there is a valid, non-truncated CPU equivalence table at the
320 * beginning of @buf of size @buf_size.
321 */
322static bool verify_equivalence_table(const u8 *buf, size_t buf_size)
323{
324 const u32 *hdr = (const u32 *)buf;
325 u32 cont_type, equiv_tbl_len;
326
327 if (!verify_container(buf, buf_size))
328 return false;
329
330 /* Zen and newer do not need an equivalence table. */
331 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
332 return true;
333
334 cont_type = hdr[1];
335 if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) {
336 pr_debug("Wrong microcode container equivalence table type: %u.\n",
337 cont_type);
338 return false;
339 }
340
341 buf_size -= CONTAINER_HDR_SZ;
342
343 equiv_tbl_len = hdr[2];
344 if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) ||
345 buf_size < equiv_tbl_len) {
346 pr_debug("Truncated equivalence table.\n");
347 return false;
348 }
349
350 return true;
351}
352
353/*
354 * Check whether there is a valid, non-truncated microcode patch section at the
355 * beginning of @buf of size @buf_size.
356 *
357 * On success, @sh_psize returns the patch size according to the section header,
358 * to the caller.
359 */
360static bool __verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize)
361{
362 u32 p_type, p_size;
363 const u32 *hdr;
364
365 if (buf_size < SECTION_HDR_SIZE) {
366 pr_debug("Truncated patch section.\n");
367 return false;
368 }
369
370 hdr = (const u32 *)buf;
371 p_type = hdr[0];
372 p_size = hdr[1];
373
374 if (p_type != UCODE_UCODE_TYPE) {
375 pr_debug("Invalid type field (0x%x) in container file section header.\n",
376 p_type);
377 return false;
378 }
379
380 if (p_size < sizeof(struct microcode_header_amd)) {
381 pr_debug("Patch of size %u too short.\n", p_size);
382 return false;
383 }
384
385 *sh_psize = p_size;
386
387 return true;
388}
389
390/*
391 * Check whether the passed remaining file @buf_size is large enough to contain
392 * a patch of the indicated @sh_psize (and also whether this size does not
393 * exceed the per-family maximum). @sh_psize is the size read from the section
394 * header.
395 */
396static unsigned int __verify_patch_size(u32 sh_psize, size_t buf_size)
397{
398 u8 family = x86_family(bsp_cpuid_1_eax);
399 u32 max_size;
400
401 if (family >= 0x15)
402 return min_t(u32, sh_psize, buf_size);
403
404#define F1XH_MPB_MAX_SIZE 2048
405#define F14H_MPB_MAX_SIZE 1824
406
407 switch (family) {
408 case 0x10 ... 0x12:
409 max_size = F1XH_MPB_MAX_SIZE;
410 break;
411 case 0x14:
412 max_size = F14H_MPB_MAX_SIZE;
413 break;
414 default:
415 WARN(1, "%s: WTF family: 0x%x\n", __func__, family);
416 return 0;
417 }
418
419 if (sh_psize > min_t(u32, buf_size, max_size))
420 return 0;
421
422 return sh_psize;
423}
424
425/*
426 * Verify the patch in @buf.
427 *
428 * Returns:
429 * negative: on error
430 * positive: patch is not for this family, skip it
431 * 0: success
432 */
433static int verify_patch(const u8 *buf, size_t buf_size, u32 *patch_size)
434{
435 u8 family = x86_family(bsp_cpuid_1_eax);
436 struct microcode_header_amd *mc_hdr;
437 unsigned int ret;
438 u32 sh_psize;
439 u16 proc_id;
440 u8 patch_fam;
441
442 if (!__verify_patch_section(buf, buf_size, &sh_psize))
443 return -1;
444
445 /*
446 * The section header length is not included in this indicated size
447 * but is present in the leftover file length so we need to subtract
448 * it before passing this value to the function below.
449 */
450 buf_size -= SECTION_HDR_SIZE;
451
452 /*
453 * Check if the remaining buffer is big enough to contain a patch of
454 * size sh_psize, as the section claims.
455 */
456 if (buf_size < sh_psize) {
457 pr_debug("Patch of size %u truncated.\n", sh_psize);
458 return -1;
459 }
460
461 ret = __verify_patch_size(sh_psize, buf_size);
462 if (!ret) {
463 pr_debug("Per-family patch size mismatch.\n");
464 return -1;
465 }
466
467 *patch_size = sh_psize;
468
469 mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE);
470 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
471 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id);
472 return -1;
473 }
474
475 proc_id = mc_hdr->processor_rev_id;
476 patch_fam = 0xf + (proc_id >> 12);
477 if (patch_fam != family)
478 return 1;
479
480 return 0;
481}
482
483static bool mc_patch_matches(struct microcode_amd *mc, u16 eq_id)
484{
485 /* Zen and newer do not need an equivalence table. */
486 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
487 return ucode_rev_to_cpuid(mc->hdr.patch_id).full == bsp_cpuid_1_eax;
488 else
489 return eq_id == mc->hdr.processor_rev_id;
490}
491
492/*
493 * This scans the ucode blob for the proper container as we can have multiple
494 * containers glued together. Returns the equivalence ID from the equivalence
495 * table or 0 if none found.
496 * Returns the amount of bytes consumed while scanning. @desc contains all the
497 * data we're going to use in later stages of the application.
498 */
499static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc)
500{
501 struct equiv_cpu_table table;
502 size_t orig_size = size;
503 u32 *hdr = (u32 *)ucode;
504 u16 eq_id;
505 u8 *buf;
506
507 if (!verify_equivalence_table(ucode, size))
508 return 0;
509
510 buf = ucode;
511
512 table.entry = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
513 table.num_entries = hdr[2] / sizeof(struct equiv_cpu_entry);
514
515 /*
516 * Find the equivalence ID of our CPU in this table. Even if this table
517 * doesn't contain a patch for the CPU, scan through the whole container
518 * so that it can be skipped in case there are other containers appended.
519 */
520 eq_id = find_equiv_id(&table, bsp_cpuid_1_eax);
521
522 buf += hdr[2] + CONTAINER_HDR_SZ;
523 size -= hdr[2] + CONTAINER_HDR_SZ;
524
525 /*
526 * Scan through the rest of the container to find where it ends. We do
527 * some basic sanity-checking too.
528 */
529 while (size > 0) {
530 struct microcode_amd *mc;
531 u32 patch_size;
532 int ret;
533
534 ret = verify_patch(buf, size, &patch_size);
535 if (ret < 0) {
536 /*
537 * Patch verification failed, skip to the next container, if
538 * there is one. Before exit, check whether that container has
539 * found a patch already. If so, use it.
540 */
541 goto out;
542 } else if (ret > 0) {
543 goto skip;
544 }
545
546 mc = (struct microcode_amd *)(buf + SECTION_HDR_SIZE);
547 if (mc_patch_matches(mc, eq_id)) {
548 desc->psize = patch_size;
549 desc->mc = mc;
550 }
551
552skip:
553 /* Skip patch section header too: */
554 buf += patch_size + SECTION_HDR_SIZE;
555 size -= patch_size + SECTION_HDR_SIZE;
556 }
557
558out:
559 /*
560 * If we have found a patch (desc->mc), it means we're looking at the
561 * container which has a patch for this CPU so return 0 to mean, @ucode
562 * already points to the proper container. Otherwise, we return the size
563 * we scanned so that we can advance to the next container in the
564 * buffer.
565 */
566 if (desc->mc) {
567 desc->data = ucode;
568 desc->size = orig_size - size;
569
570 return 0;
571 }
572
573 return orig_size - size;
574}
575
576/*
577 * Scan the ucode blob for the proper container as we can have multiple
578 * containers glued together.
579 */
580static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
581{
582 while (size) {
583 size_t s = parse_container(ucode, size, desc);
584 if (!s)
585 return;
586
587 /* catch wraparound */
588 if (size >= s) {
589 ucode += s;
590 size -= s;
591 } else {
592 return;
593 }
594 }
595}
596
597static bool __apply_microcode_amd(struct microcode_amd *mc, u32 *cur_rev,
598 unsigned int psize)
599{
600 unsigned long p_addr = (unsigned long)&mc->hdr.data_code;
601
602 if (!verify_sha256_digest(mc->hdr.patch_id, *cur_rev, (const u8 *)p_addr, psize))
603 return -1;
604
605 native_wrmsrl(MSR_AMD64_PATCH_LOADER, p_addr);
606
607 if (x86_family(bsp_cpuid_1_eax) == 0x17) {
608 unsigned long p_addr_end = p_addr + psize - 1;
609
610 invlpg(p_addr);
611
612 /*
613 * Flush next page too if patch image is crossing a page
614 * boundary.
615 */
616 if (p_addr >> PAGE_SHIFT != p_addr_end >> PAGE_SHIFT)
617 invlpg(p_addr_end);
618 }
619
620 /* verify patch application was successful */
621 *cur_rev = get_patch_level();
622 if (*cur_rev != mc->hdr.patch_id)
623 return false;
624
625 return true;
626}
627
628
629static bool get_builtin_microcode(struct cpio_data *cp)
630{
631 char fw_name[36] = "amd-ucode/microcode_amd.bin";
632 u8 family = x86_family(bsp_cpuid_1_eax);
633 struct firmware fw;
634
635 if (IS_ENABLED(CONFIG_X86_32))
636 return false;
637
638 if (family >= 0x15)
639 snprintf(fw_name, sizeof(fw_name),
640 "amd-ucode/microcode_amd_fam%02hhxh.bin", family);
641
642 if (firmware_request_builtin(&fw, fw_name)) {
643 cp->size = fw.size;
644 cp->data = (void *)fw.data;
645 return true;
646 }
647
648 return false;
649}
650
651static bool __init find_blobs_in_containers(struct cpio_data *ret)
652{
653 struct cpio_data cp;
654 bool found;
655
656 if (!get_builtin_microcode(&cp))
657 cp = find_microcode_in_initrd(ucode_path);
658
659 found = cp.data && cp.size;
660 if (found)
661 *ret = cp;
662
663 return found;
664}
665
666/*
667 * Early load occurs before we can vmalloc(). So we look for the microcode
668 * patch container file in initrd, traverse equivalent cpu table, look for a
669 * matching microcode patch, and update, all in initrd memory in place.
670 * When vmalloc() is available for use later -- on 64-bit during first AP load,
671 * and on 32-bit during save_microcode_in_initrd() -- we can call
672 * load_microcode_amd() to save equivalent cpu table and microcode patches in
673 * kernel heap memory.
674 */
675void __init load_ucode_amd_bsp(struct early_load_data *ed, unsigned int cpuid_1_eax)
676{
677 struct cont_desc desc = { };
678 struct microcode_amd *mc;
679 struct cpio_data cp = { };
680 char buf[4];
681 u32 rev;
682
683 if (cmdline_find_option(boot_command_line, "microcode.amd_sha_check", buf, 4)) {
684 if (!strncmp(buf, "off", 3)) {
685 sha_check = false;
686 pr_warn_once("It is a very very bad idea to disable the blobs SHA check!\n");
687 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
688 }
689 }
690
691 bsp_cpuid_1_eax = cpuid_1_eax;
692
693 rev = get_patch_level();
694 ed->old_rev = rev;
695
696 /* Needed in load_microcode_amd() */
697 ucode_cpu_info[0].cpu_sig.sig = cpuid_1_eax;
698
699 if (!find_blobs_in_containers(&cp))
700 return;
701
702 scan_containers(cp.data, cp.size, &desc);
703
704 mc = desc.mc;
705 if (!mc)
706 return;
707
708 /*
709 * Allow application of the same revision to pick up SMT-specific
710 * changes even if the revision of the other SMT thread is already
711 * up-to-date.
712 */
713 if (ed->old_rev > mc->hdr.patch_id)
714 return;
715
716 if (__apply_microcode_amd(mc, &rev, desc.psize))
717 ed->new_rev = rev;
718}
719
720static inline bool patch_cpus_equivalent(struct ucode_patch *p,
721 struct ucode_patch *n,
722 bool ignore_stepping)
723{
724 /* Zen and newer hardcode the f/m/s in the patch ID */
725 if (x86_family(bsp_cpuid_1_eax) >= 0x17) {
726 union cpuid_1_eax p_cid = ucode_rev_to_cpuid(p->patch_id);
727 union cpuid_1_eax n_cid = ucode_rev_to_cpuid(n->patch_id);
728
729 if (ignore_stepping) {
730 p_cid.stepping = 0;
731 n_cid.stepping = 0;
732 }
733
734 return p_cid.full == n_cid.full;
735 } else {
736 return p->equiv_cpu == n->equiv_cpu;
737 }
738}
739
740/*
741 * a small, trivial cache of per-family ucode patches
742 */
743static struct ucode_patch *cache_find_patch(struct ucode_cpu_info *uci, u16 equiv_cpu)
744{
745 struct ucode_patch *p;
746 struct ucode_patch n;
747
748 n.equiv_cpu = equiv_cpu;
749 n.patch_id = uci->cpu_sig.rev;
750
751 WARN_ON_ONCE(!n.patch_id);
752
753 list_for_each_entry(p, µcode_cache, plist)
754 if (patch_cpus_equivalent(p, &n, false))
755 return p;
756
757 return NULL;
758}
759
760static inline int patch_newer(struct ucode_patch *p, struct ucode_patch *n)
761{
762 /* Zen and newer hardcode the f/m/s in the patch ID */
763 if (x86_family(bsp_cpuid_1_eax) >= 0x17) {
764 union zen_patch_rev zp, zn;
765
766 zp.ucode_rev = p->patch_id;
767 zn.ucode_rev = n->patch_id;
768
769 if (zn.stepping != zp.stepping)
770 return -1;
771
772 return zn.rev > zp.rev;
773 } else {
774 return n->patch_id > p->patch_id;
775 }
776}
777
778static void update_cache(struct ucode_patch *new_patch)
779{
780 struct ucode_patch *p;
781 int ret;
782
783 list_for_each_entry(p, µcode_cache, plist) {
784 if (patch_cpus_equivalent(p, new_patch, true)) {
785 ret = patch_newer(p, new_patch);
786 if (ret < 0)
787 continue;
788 else if (!ret) {
789 /* we already have the latest patch */
790 kfree(new_patch->data);
791 kfree(new_patch);
792 return;
793 }
794
795 list_replace(&p->plist, &new_patch->plist);
796 kfree(p->data);
797 kfree(p);
798 return;
799 }
800 }
801 /* no patch found, add it */
802 list_add_tail(&new_patch->plist, µcode_cache);
803}
804
805static void free_cache(void)
806{
807 struct ucode_patch *p, *tmp;
808
809 list_for_each_entry_safe(p, tmp, µcode_cache, plist) {
810 __list_del(p->plist.prev, p->plist.next);
811 kfree(p->data);
812 kfree(p);
813 }
814}
815
816static struct ucode_patch *find_patch(unsigned int cpu)
817{
818 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
819 u16 equiv_id = 0;
820
821 uci->cpu_sig.rev = get_patch_level();
822
823 if (x86_family(bsp_cpuid_1_eax) < 0x17) {
824 equiv_id = find_equiv_id(&equiv_table, uci->cpu_sig.sig);
825 if (!equiv_id)
826 return NULL;
827 }
828
829 return cache_find_patch(uci, equiv_id);
830}
831
832void reload_ucode_amd(unsigned int cpu)
833{
834 u32 rev, dummy __always_unused;
835 struct microcode_amd *mc;
836 struct ucode_patch *p;
837
838 p = find_patch(cpu);
839 if (!p)
840 return;
841
842 mc = p->data;
843
844 rev = get_patch_level();
845 if (rev < mc->hdr.patch_id) {
846 if (__apply_microcode_amd(mc, &rev, p->size))
847 pr_info_once("reload revision: 0x%08x\n", rev);
848 }
849}
850
851static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
852{
853 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
854 struct ucode_patch *p;
855
856 csig->sig = cpuid_eax(0x00000001);
857 csig->rev = get_patch_level();
858
859 /*
860 * a patch could have been loaded early, set uci->mc so that
861 * mc_bp_resume() can call apply_microcode()
862 */
863 p = find_patch(cpu);
864 if (p && (p->patch_id == csig->rev))
865 uci->mc = p->data;
866
867 return 0;
868}
869
870static enum ucode_state apply_microcode_amd(int cpu)
871{
872 struct cpuinfo_x86 *c = &cpu_data(cpu);
873 struct microcode_amd *mc_amd;
874 struct ucode_cpu_info *uci;
875 struct ucode_patch *p;
876 enum ucode_state ret;
877 u32 rev;
878
879 BUG_ON(raw_smp_processor_id() != cpu);
880
881 uci = ucode_cpu_info + cpu;
882
883 p = find_patch(cpu);
884 if (!p)
885 return UCODE_NFOUND;
886
887 rev = uci->cpu_sig.rev;
888
889 mc_amd = p->data;
890 uci->mc = p->data;
891
892 /* need to apply patch? */
893 if (rev > mc_amd->hdr.patch_id) {
894 ret = UCODE_OK;
895 goto out;
896 }
897
898 if (!__apply_microcode_amd(mc_amd, &rev, p->size)) {
899 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
900 cpu, mc_amd->hdr.patch_id);
901 return UCODE_ERROR;
902 }
903
904 rev = mc_amd->hdr.patch_id;
905 ret = UCODE_UPDATED;
906
907out:
908 uci->cpu_sig.rev = rev;
909 c->microcode = rev;
910
911 /* Update boot_cpu_data's revision too, if we're on the BSP: */
912 if (c->cpu_index == boot_cpu_data.cpu_index)
913 boot_cpu_data.microcode = rev;
914
915 return ret;
916}
917
918void load_ucode_amd_ap(unsigned int cpuid_1_eax)
919{
920 unsigned int cpu = smp_processor_id();
921
922 ucode_cpu_info[cpu].cpu_sig.sig = cpuid_1_eax;
923 apply_microcode_amd(cpu);
924}
925
926static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
927{
928 u32 equiv_tbl_len;
929 const u32 *hdr;
930
931 if (!verify_equivalence_table(buf, buf_size))
932 return 0;
933
934 hdr = (const u32 *)buf;
935 equiv_tbl_len = hdr[2];
936
937 /* Zen and newer do not need an equivalence table. */
938 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
939 goto out;
940
941 equiv_table.entry = vmalloc(equiv_tbl_len);
942 if (!equiv_table.entry) {
943 pr_err("failed to allocate equivalent CPU table\n");
944 return 0;
945 }
946
947 memcpy(equiv_table.entry, buf + CONTAINER_HDR_SZ, equiv_tbl_len);
948 equiv_table.num_entries = equiv_tbl_len / sizeof(struct equiv_cpu_entry);
949
950out:
951 /* add header length */
952 return equiv_tbl_len + CONTAINER_HDR_SZ;
953}
954
955static void free_equiv_cpu_table(void)
956{
957 if (x86_family(bsp_cpuid_1_eax) >= 0x17)
958 return;
959
960 vfree(equiv_table.entry);
961 memset(&equiv_table, 0, sizeof(equiv_table));
962}
963
964static void cleanup(void)
965{
966 free_equiv_cpu_table();
967 free_cache();
968}
969
970/*
971 * Return a non-negative value even if some of the checks failed so that
972 * we can skip over the next patch. If we return a negative value, we
973 * signal a grave error like a memory allocation has failed and the
974 * driver cannot continue functioning normally. In such cases, we tear
975 * down everything we've used up so far and exit.
976 */
977static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover,
978 unsigned int *patch_size)
979{
980 struct microcode_header_amd *mc_hdr;
981 struct ucode_patch *patch;
982 u16 proc_id;
983 int ret;
984
985 ret = verify_patch(fw, leftover, patch_size);
986 if (ret)
987 return ret;
988
989 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
990 if (!patch) {
991 pr_err("Patch allocation failure.\n");
992 return -EINVAL;
993 }
994
995 patch->data = kmemdup(fw + SECTION_HDR_SIZE, *patch_size, GFP_KERNEL);
996 if (!patch->data) {
997 pr_err("Patch data allocation failure.\n");
998 kfree(patch);
999 return -EINVAL;
1000 }
1001 patch->size = *patch_size;
1002
1003 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
1004 proc_id = mc_hdr->processor_rev_id;
1005
1006 INIT_LIST_HEAD(&patch->plist);
1007 patch->patch_id = mc_hdr->patch_id;
1008 patch->equiv_cpu = proc_id;
1009
1010 pr_debug("%s: Adding patch_id: 0x%08x, proc_id: 0x%04x\n",
1011 __func__, patch->patch_id, proc_id);
1012
1013 /* ... and add to cache. */
1014 update_cache(patch);
1015
1016 return 0;
1017}
1018
1019/* Scan the blob in @data and add microcode patches to the cache. */
1020static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, size_t size)
1021{
1022 u8 *fw = (u8 *)data;
1023 size_t offset;
1024
1025 offset = install_equiv_cpu_table(data, size);
1026 if (!offset)
1027 return UCODE_ERROR;
1028
1029 fw += offset;
1030 size -= offset;
1031
1032 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
1033 pr_err("invalid type field in container file section header\n");
1034 free_equiv_cpu_table();
1035 return UCODE_ERROR;
1036 }
1037
1038 while (size > 0) {
1039 unsigned int crnt_size = 0;
1040 int ret;
1041
1042 ret = verify_and_add_patch(family, fw, size, &crnt_size);
1043 if (ret < 0)
1044 return UCODE_ERROR;
1045
1046 fw += crnt_size + SECTION_HDR_SIZE;
1047 size -= (crnt_size + SECTION_HDR_SIZE);
1048 }
1049
1050 return UCODE_OK;
1051}
1052
1053static enum ucode_state _load_microcode_amd(u8 family, const u8 *data, size_t size)
1054{
1055 enum ucode_state ret;
1056
1057 /* free old equiv table */
1058 free_equiv_cpu_table();
1059
1060 ret = __load_microcode_amd(family, data, size);
1061 if (ret != UCODE_OK)
1062 cleanup();
1063
1064 return ret;
1065}
1066
1067static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
1068{
1069 struct cpuinfo_x86 *c;
1070 unsigned int nid, cpu;
1071 struct ucode_patch *p;
1072 enum ucode_state ret;
1073
1074 ret = _load_microcode_amd(family, data, size);
1075 if (ret != UCODE_OK)
1076 return ret;
1077
1078 for_each_node(nid) {
1079 cpu = cpumask_first(cpumask_of_node(nid));
1080 c = &cpu_data(cpu);
1081
1082 p = find_patch(cpu);
1083 if (!p)
1084 continue;
1085
1086 if (c->microcode >= p->patch_id)
1087 continue;
1088
1089 ret = UCODE_NEW;
1090 }
1091
1092 return ret;
1093}
1094
1095static int __init save_microcode_in_initrd(void)
1096{
1097 unsigned int cpuid_1_eax = native_cpuid_eax(1);
1098 struct cpuinfo_x86 *c = &boot_cpu_data;
1099 struct cont_desc desc = { 0 };
1100 enum ucode_state ret;
1101 struct cpio_data cp;
1102
1103 if (dis_ucode_ldr || c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10)
1104 return 0;
1105
1106 if (!find_blobs_in_containers(&cp))
1107 return -EINVAL;
1108
1109 scan_containers(cp.data, cp.size, &desc);
1110 if (!desc.mc)
1111 return -EINVAL;
1112
1113 ret = _load_microcode_amd(x86_family(cpuid_1_eax), desc.data, desc.size);
1114 if (ret > UCODE_UPDATED)
1115 return -EINVAL;
1116
1117 return 0;
1118}
1119early_initcall(save_microcode_in_initrd);
1120
1121/*
1122 * AMD microcode firmware naming convention, up to family 15h they are in
1123 * the legacy file:
1124 *
1125 * amd-ucode/microcode_amd.bin
1126 *
1127 * This legacy file is always smaller than 2K in size.
1128 *
1129 * Beginning with family 15h, they are in family-specific firmware files:
1130 *
1131 * amd-ucode/microcode_amd_fam15h.bin
1132 * amd-ucode/microcode_amd_fam16h.bin
1133 * ...
1134 *
1135 * These might be larger than 2K.
1136 */
1137static enum ucode_state request_microcode_amd(int cpu, struct device *device)
1138{
1139 char fw_name[36] = "amd-ucode/microcode_amd.bin";
1140 struct cpuinfo_x86 *c = &cpu_data(cpu);
1141 enum ucode_state ret = UCODE_NFOUND;
1142 const struct firmware *fw;
1143
1144 if (force_minrev)
1145 return UCODE_NFOUND;
1146
1147 if (c->x86 >= 0x15)
1148 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
1149
1150 if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
1151 pr_debug("failed to load file %s\n", fw_name);
1152 goto out;
1153 }
1154
1155 ret = UCODE_ERROR;
1156 if (!verify_container(fw->data, fw->size))
1157 goto fw_release;
1158
1159 ret = load_microcode_amd(c->x86, fw->data, fw->size);
1160
1161 fw_release:
1162 release_firmware(fw);
1163
1164 out:
1165 return ret;
1166}
1167
1168static void microcode_fini_cpu_amd(int cpu)
1169{
1170 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1171
1172 uci->mc = NULL;
1173}
1174
1175static struct microcode_ops microcode_amd_ops = {
1176 .request_microcode_fw = request_microcode_amd,
1177 .collect_cpu_info = collect_cpu_info_amd,
1178 .apply_microcode = apply_microcode_amd,
1179 .microcode_fini_cpu = microcode_fini_cpu_amd,
1180 .nmi_safe = true,
1181};
1182
1183struct microcode_ops * __init init_amd_microcode(void)
1184{
1185 struct cpuinfo_x86 *c = &boot_cpu_data;
1186
1187 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
1188 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
1189 return NULL;
1190 }
1191 return µcode_amd_ops;
1192}
1193
1194void __exit exit_amd_microcode(void)
1195{
1196 cleanup();
1197}