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1/*
2 * GPIOs on MPC512x/8349/8572/8610 and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/gpio.h>
18#include <linux/slab.h>
19#include <linux/irq.h>
20
21#define MPC8XXX_GPIO_PINS 32
22
23#define GPIO_DIR 0x00
24#define GPIO_ODR 0x04
25#define GPIO_DAT 0x08
26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14
29#define GPIO_ICR2 0x18
30
31struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
34
35 /*
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
38 */
39 u32 data;
40 struct irq_host *irq;
41 void *of_dev_id_data;
42};
43
44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
45{
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
47}
48
49static inline struct mpc8xxx_gpio_chip *
50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
51{
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
53}
54
55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
56{
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
58
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60}
61
62/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
66 */
67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68{
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
72
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
74
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
76}
77
78static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
79{
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
81
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
83}
84
85static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
89 unsigned long flags;
90
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
92
93 if (val)
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
95 else
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
97
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
99
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
101}
102
103static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
104{
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107 unsigned long flags;
108
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
110
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
112
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
114
115 return 0;
116}
117
118static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
119{
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122 unsigned long flags;
123
124 mpc8xxx_gpio_set(gc, gpio, val);
125
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
127
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
129
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131
132 return 0;
133}
134
135static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
136{
137 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
138 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
139
140 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
141 return irq_create_mapping(mpc8xxx_gc->irq, offset);
142 else
143 return -ENXIO;
144}
145
146static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
147{
148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
149 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
150 unsigned int mask;
151
152 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
153 if (mask)
154 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
155 32 - ffs(mask)));
156}
157
158static void mpc8xxx_irq_unmask(struct irq_data *d)
159{
160 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
161 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
162 unsigned long flags;
163
164 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
165
166 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
167
168 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
169}
170
171static void mpc8xxx_irq_mask(struct irq_data *d)
172{
173 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
174 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
175 unsigned long flags;
176
177 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
178
179 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
180
181 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
182}
183
184static void mpc8xxx_irq_ack(struct irq_data *d)
185{
186 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
187 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
188
189 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
190}
191
192static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
193{
194 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
195 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
196 unsigned long flags;
197
198 switch (flow_type) {
199 case IRQ_TYPE_EDGE_FALLING:
200 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
201 setbits32(mm->regs + GPIO_ICR,
202 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
203 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
204 break;
205
206 case IRQ_TYPE_EDGE_BOTH:
207 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
208 clrbits32(mm->regs + GPIO_ICR,
209 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
210 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
211 break;
212
213 default:
214 return -EINVAL;
215 }
216
217 return 0;
218}
219
220static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
221{
222 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
223 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
224 unsigned long gpio = irqd_to_hwirq(d);
225 void __iomem *reg;
226 unsigned int shift;
227 unsigned long flags;
228
229 if (gpio < 16) {
230 reg = mm->regs + GPIO_ICR;
231 shift = (15 - gpio) * 2;
232 } else {
233 reg = mm->regs + GPIO_ICR2;
234 shift = (15 - (gpio % 16)) * 2;
235 }
236
237 switch (flow_type) {
238 case IRQ_TYPE_EDGE_FALLING:
239 case IRQ_TYPE_LEVEL_LOW:
240 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
241 clrsetbits_be32(reg, 3 << shift, 2 << shift);
242 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
243 break;
244
245 case IRQ_TYPE_EDGE_RISING:
246 case IRQ_TYPE_LEVEL_HIGH:
247 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
248 clrsetbits_be32(reg, 3 << shift, 1 << shift);
249 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
250 break;
251
252 case IRQ_TYPE_EDGE_BOTH:
253 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
254 clrbits32(reg, 3 << shift);
255 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
256 break;
257
258 default:
259 return -EINVAL;
260 }
261
262 return 0;
263}
264
265static struct irq_chip mpc8xxx_irq_chip = {
266 .name = "mpc8xxx-gpio",
267 .irq_unmask = mpc8xxx_irq_unmask,
268 .irq_mask = mpc8xxx_irq_mask,
269 .irq_ack = mpc8xxx_irq_ack,
270 .irq_set_type = mpc8xxx_irq_set_type,
271};
272
273static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
274 irq_hw_number_t hw)
275{
276 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
277
278 if (mpc8xxx_gc->of_dev_id_data)
279 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
280
281 irq_set_chip_data(virq, h->host_data);
282 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
283 irq_set_irq_type(virq, IRQ_TYPE_NONE);
284
285 return 0;
286}
287
288static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
289 const u32 *intspec, unsigned int intsize,
290 irq_hw_number_t *out_hwirq,
291 unsigned int *out_flags)
292
293{
294 /* interrupt sense values coming from the device tree equal either
295 * EDGE_FALLING or EDGE_BOTH
296 */
297 *out_hwirq = intspec[0];
298 *out_flags = intspec[1];
299
300 return 0;
301}
302
303static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
304 .map = mpc8xxx_gpio_irq_map,
305 .xlate = mpc8xxx_gpio_irq_xlate,
306};
307
308static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
309 { .compatible = "fsl,mpc8349-gpio", },
310 { .compatible = "fsl,mpc8572-gpio", },
311 { .compatible = "fsl,mpc8610-gpio", },
312 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
313 { .compatible = "fsl,qoriq-gpio", },
314 {}
315};
316
317static void __init mpc8xxx_add_controller(struct device_node *np)
318{
319 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
320 struct of_mm_gpio_chip *mm_gc;
321 struct gpio_chip *gc;
322 const struct of_device_id *id;
323 unsigned hwirq;
324 int ret;
325
326 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
327 if (!mpc8xxx_gc) {
328 ret = -ENOMEM;
329 goto err;
330 }
331
332 spin_lock_init(&mpc8xxx_gc->lock);
333
334 mm_gc = &mpc8xxx_gc->mm_gc;
335 gc = &mm_gc->gc;
336
337 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
338 gc->ngpio = MPC8XXX_GPIO_PINS;
339 gc->direction_input = mpc8xxx_gpio_dir_in;
340 gc->direction_output = mpc8xxx_gpio_dir_out;
341 if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
342 gc->get = mpc8572_gpio_get;
343 else
344 gc->get = mpc8xxx_gpio_get;
345 gc->set = mpc8xxx_gpio_set;
346 gc->to_irq = mpc8xxx_gpio_to_irq;
347
348 ret = of_mm_gpiochip_add(np, mm_gc);
349 if (ret)
350 goto err;
351
352 hwirq = irq_of_parse_and_map(np, 0);
353 if (hwirq == NO_IRQ)
354 goto skip_irq;
355
356 mpc8xxx_gc->irq =
357 irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
358 &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
359 if (!mpc8xxx_gc->irq)
360 goto skip_irq;
361
362 id = of_match_node(mpc8xxx_gpio_ids, np);
363 if (id)
364 mpc8xxx_gc->of_dev_id_data = id->data;
365
366 mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
367
368 /* ack and mask all irqs */
369 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
370 out_be32(mm_gc->regs + GPIO_IMR, 0);
371
372 irq_set_handler_data(hwirq, mpc8xxx_gc);
373 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
374
375skip_irq:
376 return;
377
378err:
379 pr_err("%s: registration failed with status %d\n",
380 np->full_name, ret);
381 kfree(mpc8xxx_gc);
382
383 return;
384}
385
386static int __init mpc8xxx_add_gpiochips(void)
387{
388 struct device_node *np;
389
390 for_each_matching_node(np, mpc8xxx_gpio_ids)
391 mpc8xxx_add_controller(np);
392
393 return 0;
394}
395arch_initcall(mpc8xxx_add_gpiochips);