1/*
  2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
  3 *
  4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
  5 *
  6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
  7 *
  8 * This program is free software; you can redistribute  it and/or modify it
  9 * under  the terms of  the GNU General  Public License as published by the
 10 * Free Software Foundation;  either version 2 of the  License, or (at your
 11 * option) any later version.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16 * GNU General Public License for more details.
 17 *
 18 * You should have received a copy of the GNU General Public License
 19 * along with this program; if not, write to the Free Software
 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21 */
 22
 23#include <linux/kernel.h>
 24#include <linux/of_platform.h>
 25#include <asm/io.h>
 26
 27#include "fsl_85xx_cache_ctlr.h"
 28
 29static char *sram_size;
 30static char *sram_offset;
 31struct mpc85xx_l2ctlr __iomem *l2ctlr;
 32
 33static long get_cache_sram_size(void)
 34{
 35	unsigned long val;
 36
 37	if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
 38		return -EINVAL;
 39
 40	return val;
 41}
 42
 43static long get_cache_sram_offset(void)
 44{
 45	unsigned long val;
 46
 47	if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
 48		return -EINVAL;
 49
 50	return val;
 51}
 52
 53static int __init get_size_from_cmdline(char *str)
 54{
 55	if (!str)
 56		return 0;
 57
 58	sram_size = str;
 59	return 1;
 60}
 61
 62static int __init get_offset_from_cmdline(char *str)
 63{
 64	if (!str)
 65		return 0;
 66
 67	sram_offset = str;
 68	return 1;
 69}
 70
 71__setup("cache-sram-size=", get_size_from_cmdline);
 72__setup("cache-sram-offset=", get_offset_from_cmdline);
 73
 74static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
 75{
 76	long rval;
 77	unsigned int rem;
 78	unsigned char ways;
 79	const unsigned int *prop;
 80	unsigned int l2cache_size;
 81	struct sram_parameters sram_params;
 82
 83	if (!dev->dev.of_node) {
 84		dev_err(&dev->dev, "Device's OF-node is NULL\n");
 85		return -EINVAL;
 86	}
 87
 88	prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
 89	if (!prop) {
 90		dev_err(&dev->dev, "Missing L2 cache-size\n");
 91		return -EINVAL;
 92	}
 93	l2cache_size = *prop;
 94
 95	sram_params.sram_size  = get_cache_sram_size();
 96	if ((int)sram_params.sram_size <= 0) {
 97		dev_err(&dev->dev,
 98			"Entire L2 as cache, Aborting Cache-SRAM stuff\n");
 99		return -EINVAL;
100	}
101
102	sram_params.sram_offset  = get_cache_sram_offset();
103	if ((int64_t)sram_params.sram_offset <= 0) {
104		dev_err(&dev->dev,
105			"Entire L2 as cache, provide a valid sram offset\n");
106		return -EINVAL;
107	}
108
109
110	rem = l2cache_size % sram_params.sram_size;
111	ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
112	if (rem || (ways & (ways - 1))) {
113		dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
114		return -EINVAL;
115	}
116
117	l2ctlr = of_iomap(dev->dev.of_node, 0);
118	if (!l2ctlr) {
119		dev_err(&dev->dev, "Can't map L2 controller\n");
120		return -EINVAL;
121	}
122
123	/*
124	 * Write bits[0-17] to srbar0
125	 */
126	out_be32(&l2ctlr->srbar0,
127		sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
128
129	/*
130	 * Write bits[18-21] to srbare0
131	 */
132#ifdef CONFIG_PHYS_64BIT
133	out_be32(&l2ctlr->srbarea0,
134		(sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
135#endif
136
137	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
138
139	switch (ways) {
140	case LOCK_WAYS_EIGHTH:
141		setbits32(&l2ctlr->ctl,
142			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
143		break;
144
145	case LOCK_WAYS_TWO_EIGHTH:
146		setbits32(&l2ctlr->ctl,
147			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
148		break;
149
150	case LOCK_WAYS_HALF:
151		setbits32(&l2ctlr->ctl,
152			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
153		break;
154
155	case LOCK_WAYS_FULL:
156	default:
157		setbits32(&l2ctlr->ctl,
158			L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
159		break;
160	}
161	eieio();
162
163	rval = instantiate_cache_sram(dev, sram_params);
164	if (rval < 0) {
165		dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
166		iounmap(l2ctlr);
167		return -EINVAL;
168	}
169
170	return 0;
171}
172
173static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
174{
175	BUG_ON(!l2ctlr);
176
177	iounmap(l2ctlr);
178	remove_cache_sram(dev);
179	dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
180
181	return 0;
182}
183
184static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
185	{
186		.compatible = "fsl,p2020-l2-cache-controller",
187	},
188	{
189		.compatible = "fsl,p2010-l2-cache-controller",
190	},
191	{
192		.compatible = "fsl,p1020-l2-cache-controller",
193	},
194	{
195		.compatible = "fsl,p1011-l2-cache-controller",
196	},
197	{
198		.compatible = "fsl,p1013-l2-cache-controller",
199	},
200	{
201		.compatible = "fsl,p1022-l2-cache-controller",
202	},
203	{},
204};
205
206static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
207	.driver	= {
208		.name		= "fsl-l2ctlr",
209		.owner		= THIS_MODULE,
210		.of_match_table	= mpc85xx_l2ctlr_of_match,
211	},
212	.probe		= mpc85xx_l2ctlr_of_probe,
213	.remove		= __devexit_p(mpc85xx_l2ctlr_of_remove),
214};
215
216static __init int mpc85xx_l2ctlr_of_init(void)
217{
218	return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
219}
220
221static void __exit mpc85xx_l2ctlr_of_exit(void)
222{
223	platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
224}
225
226subsys_initcall(mpc85xx_l2ctlr_of_init);
227module_exit(mpc85xx_l2ctlr_of_exit);
228
229MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
230MODULE_LICENSE("GPL v2");