1/*****************************************************************************/
  2
  3/*
  4 *	head.S -- common startup code for ColdFire CPUs.
  5 *
  6 *	(C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>.
  7 */
  8
  9/*****************************************************************************/
 10
 11#include <linux/linkage.h>
 12#include <linux/init.h>
 13#include <asm/asm-offsets.h>
 14#include <asm/coldfire.h>
 15#include <asm/mcfsim.h>
 16#include <asm/thread_info.h>
 17
 18/*****************************************************************************/
 19
 20/*
 21 *	If we don't have a fixed memory size, then lets build in code
 22 *	to auto detect the DRAM size. Obviously this is the preferred
 23 *	method, and should work for most boards. It won't work for those
 24 *	that do not have their RAM starting at address 0, and it only
 25 *	works on SDRAM (not boards fitted with SRAM).
 26 */
 27#if CONFIG_RAMSIZE != 0
 28.macro GET_MEM_SIZE
 29	movel	#CONFIG_RAMSIZE,%d0	/* hard coded memory size */
 30.endm
 31
 32#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
 33      defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
 34      defined(CONFIG_M528x) || defined(CONFIG_M5307) || \
 35      defined(CONFIG_M5407)
 36/*
 37 *	Not all these devices have exactly the same DRAM controller,
 38 *	but the DCMR register is virtually identical - give or take
 39 *	a couple of bits. The only exception is the 5272 devices, their
 40 *	DRAM controller is quite different.
 41 */
 42.macro GET_MEM_SIZE
 43	movel	MCFSIM_DMR0,%d0		/* get mask for 1st bank */
 44	btst	#0,%d0			/* check if region enabled */
 45	beq	1f
 46	andl	#0xfffc0000,%d0
 47	beq	1f
 48	addl	#0x00040000,%d0		/* convert mask to size */
 491:
 50	movel	MCFSIM_DMR1,%d1		/* get mask for 2nd bank */
 51	btst	#0,%d1			/* check if region enabled */
 52	beq	2f
 53	andl	#0xfffc0000,%d1
 54	beq	2f
 55	addl	#0x00040000,%d1
 56	addl	%d1,%d0			/* total mem size in d0 */
 572:
 58.endm
 59
 60#elif defined(CONFIG_M5272)
 61.macro GET_MEM_SIZE
 62	movel	MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
 63	andil	#0xfffff000,%d0		/* mask out chip select options */
 64	negl	%d0			/* negate bits */
 65.endm
 66
 67#elif defined(CONFIG_M520x)
 68.macro GET_MEM_SIZE
 69	clrl	%d0
 70	movel	MCFSIM_SDCS0, %d2	/* Get SDRAM chip select 0 config */
 71	andl	#0x1f, %d2		/* Get only the chip select size */
 72	beq	3f			/* Check if it is enabled */
 73	addql	#1, %d2			/* Form exponent */
 74	moveql	#1, %d0
 75	lsll	%d2, %d0		/* 2 ^ exponent */
 763:
 77	movel	MCFSIM_SDCS1, %d2	/* Get SDRAM chip select 1 config */
 78	andl	#0x1f, %d2		/* Get only the chip select size */
 79	beq	4f			/* Check if it is enabled */
 80	addql	#1, %d2			/* Form exponent */
 81	moveql	#1, %d1
 82	lsll	%d2, %d1		/* 2 ^ exponent */
 83	addl	%d1, %d0		/* Total size of SDRAM in d0 */
 844:
 85.endm
 86
 87#else
 88#error "ERROR: I don't know how to probe your boards memory size?"
 89#endif
 90
 91/*****************************************************************************/
 92
 93/*
 94 *	Boards and platforms can do specific early hardware setup if
 95 *	they need to. Most don't need this, define away if not required.
 96 */
 97#ifndef PLATFORM_SETUP
 98#define	PLATFORM_SETUP
 99#endif
100
101/*****************************************************************************/
102
103.global	_start
104.global _rambase
105.global _ramvec
106.global	_ramstart
107.global	_ramend
108#if defined(CONFIG_UBOOT)
109.global	_init_sp
110#endif
111
112/*****************************************************************************/
113
114.data
115
116/*
117 *	During startup we store away the RAM setup. These are not in the
118 *	bss, since their values are determined and written before the bss
119 *	has been cleared.
120 */
121_rambase:
122.long	0
123_ramvec:
124.long	0
125_ramstart:
126.long	0
127_ramend:
128.long	0
129#if defined(CONFIG_UBOOT)
130_init_sp:
131.long	0
132#endif
133
134/*****************************************************************************/
135
136__HEAD
137
138/*
139 *	This is the codes first entry point. This is where it all
140 *	begins...
141 */
142
143_start:
144	nop					/* filler */
145	movew	#0x2700, %sr			/* no interrupts */
146#if defined(CONFIG_UBOOT)
147	movel	%sp,_init_sp			/* save initial stack pointer */
148#endif
149
150	/*
151	 *	Do any platform or board specific setup now. Most boards
152	 *	don't need anything. Those exceptions are define this in
153	 *	their board specific includes.
154	 */
155	PLATFORM_SETUP
156
157	/*
158	 *	Create basic memory configuration. Set VBR accordingly,
159	 *	and size memory.
160	 */
161	movel	#CONFIG_VECTORBASE,%a7
162	movec   %a7,%VBR			/* set vectors addr */
163	movel	%a7,_ramvec
164
165	movel	#CONFIG_RAMBASE,%a7		/* mark the base of RAM */
166	movel	%a7,_rambase
167
168	GET_MEM_SIZE				/* macro code determines size */
169	addl	%a7,%d0
170	movel	%d0,_ramend			/* set end ram addr */
171
172	/*
173	 *	Now that we know what the memory is, lets enable cache
174	 *	and get things moving. This is Coldfire CPU specific. Not
175	 *	all version cores have identical cache register setup. But
176	 *	it is very similar. Define the exact settings in the headers
177	 *	then the code here is the same for all.
178	 */
179	movel	#CACHE_INIT,%d0			/* invalidate whole cache */
180	movec	%d0,%CACR
181	nop
182	movel	#ACR0_MODE,%d0			/* set RAM region for caching */
183	movec	%d0,%ACR0
184	movel	#ACR1_MODE,%d0			/* anything else to cache? */
185	movec	%d0,%ACR1
186#ifdef ACR2_MODE
187	movel	#ACR2_MODE,%d0
188	movec	%d0,%ACR2
189	movel	#ACR3_MODE,%d0
190	movec	%d0,%ACR3
191#endif
192	movel	#CACHE_MODE,%d0			/* enable cache */
193	movec	%d0,%CACR
194	nop
195
196#ifdef CONFIG_ROMFS_FS
197	/*
198	 *	Move ROM filesystem above bss :-)
199	 */
200	lea	_sbss,%a0			/* get start of bss */
201	lea	_ebss,%a1			/* set up destination  */
202	movel	%a0,%a2				/* copy of bss start */
203
204	movel	8(%a0),%d0			/* get size of ROMFS */
205	addql	#8,%d0				/* allow for rounding */
206	andl	#0xfffffffc, %d0		/* whole words */
207
208	addl	%d0,%a0				/* copy from end */
209	addl	%d0,%a1				/* copy from end */
210	movel	%a1,_ramstart			/* set start of ram */
211
212_copy_romfs:
213	movel	-(%a0),%d0			/* copy dword */
214	movel	%d0,-(%a1)
215	cmpl	%a0,%a2				/* check if at end */
216	bne	_copy_romfs
217
218#else /* CONFIG_ROMFS_FS */
219	lea	_ebss,%a1
220	movel	%a1,_ramstart
221#endif /* CONFIG_ROMFS_FS */
222
223
224	/*
225	 *	Zero out the bss region.
226	 */
227	lea	_sbss,%a0			/* get start of bss */
228	lea	_ebss,%a1			/* get end of bss */
229	clrl	%d0				/* set value */
230_clear_bss:
231	movel	%d0,(%a0)+			/* clear each word */
232	cmpl	%a0,%a1				/* check if at end */
233	bne	_clear_bss
234
235	/*
236	 *	Load the current task pointer and stack.
237	 */
238	lea	init_thread_union,%a0
239	lea	THREAD_SIZE(%a0),%sp
240
241	/*
242	 *	Assember start up done, start code proper.
243	 */
244	jsr	start_kernel			/* start Linux kernel */
245
246_exit:
247	jmp	_exit				/* should never get here */
248
249/*****************************************************************************/