1#ifndef _M68K_SYSTEM_H
  2#define _M68K_SYSTEM_H
  3
  4#include <linux/linkage.h>
  5#include <linux/kernel.h>
  6#include <linux/irqflags.h>
  7#include <asm/segment.h>
  8#include <asm/entry.h>
  9
 10#ifdef __KERNEL__
 11
 12/*
 13 * switch_to(n) should switch tasks to task ptr, first checking that
 14 * ptr isn't the current task, in which case it does nothing.  This
 15 * also clears the TS-flag if the task we switched to has used the
 16 * math co-processor latest.
 17 */
 18/*
 19 * switch_to() saves the extra registers, that are not saved
 20 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
 21 * a0-a1. Some of these are used by schedule() and its predecessors
 22 * and so we might get see unexpected behaviors when a task returns
 23 * with unexpected register values.
 24 *
 25 * syscall stores these registers itself and none of them are used
 26 * by syscall after the function in the syscall has been called.
 27 *
 28 * Beware that resume now expects *next to be in d1 and the offset of
 29 * tss to be in a1. This saves a few instructions as we no longer have
 30 * to push them onto the stack and read them back right after.
 31 *
 32 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
 33 *
 34 * Changed 96/09/19 by Andreas Schwab
 35 * pass prev in a0, next in a1
 36 */
 37asmlinkage void resume(void);
 38#define switch_to(prev,next,last) do { \
 39  register void *_prev __asm__ ("a0") = (prev); \
 40  register void *_next __asm__ ("a1") = (next); \
 41  register void *_last __asm__ ("d1"); \
 42  __asm__ __volatile__("jbsr resume" \
 43		       : "=a" (_prev), "=a" (_next), "=d" (_last) \
 44		       : "0" (_prev), "1" (_next) \
 45		       : "d0", "d2", "d3", "d4", "d5"); \
 46  (last) = _last; \
 47} while (0)
 48
 49
 50/*
 51 * Force strict CPU ordering.
 52 * Not really required on m68k...
 53 */
 54#define nop()		do { asm volatile ("nop"); barrier(); } while (0)
 55#define mb()		barrier()
 56#define rmb()		barrier()
 57#define wmb()		barrier()
 58#define read_barrier_depends()	((void)0)
 59#define set_mb(var, value)	({ (var) = (value); wmb(); })
 60
 61#define smp_mb()	barrier()
 62#define smp_rmb()	barrier()
 63#define smp_wmb()	barrier()
 64#define smp_read_barrier_depends()	((void)0)
 65
 66#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 67
 68struct __xchg_dummy { unsigned long a[100]; };
 69#define __xg(x) ((volatile struct __xchg_dummy *)(x))
 70
 71#ifndef CONFIG_RMW_INSNS
 72static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 73{
 74	unsigned long flags, tmp;
 75
 76	local_irq_save(flags);
 77
 78	switch (size) {
 79	case 1:
 80		tmp = *(u8 *)ptr;
 81		*(u8 *)ptr = x;
 82		x = tmp;
 83		break;
 84	case 2:
 85		tmp = *(u16 *)ptr;
 86		*(u16 *)ptr = x;
 87		x = tmp;
 88		break;
 89	case 4:
 90		tmp = *(u32 *)ptr;
 91		*(u32 *)ptr = x;
 92		x = tmp;
 93		break;
 94	default:
 95		BUG();
 96	}
 97
 98	local_irq_restore(flags);
 99	return x;
100}
101#else
102static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
103{
104	switch (size) {
105	    case 1:
106		__asm__ __volatile__
107			("moveb %2,%0\n\t"
108			 "1:\n\t"
109			 "casb %0,%1,%2\n\t"
110			 "jne 1b"
111			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
112		break;
113	    case 2:
114		__asm__ __volatile__
115			("movew %2,%0\n\t"
116			 "1:\n\t"
117			 "casw %0,%1,%2\n\t"
118			 "jne 1b"
119			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
120		break;
121	    case 4:
122		__asm__ __volatile__
123			("movel %2,%0\n\t"
124			 "1:\n\t"
125			 "casl %0,%1,%2\n\t"
126			 "jne 1b"
127			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
128		break;
129	}
130	return x;
131}
132#endif
133
134#include <asm-generic/cmpxchg-local.h>
135
136#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
137
138/*
139 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
140 * store NEW in MEM.  Return the initial value in MEM.  Success is
141 * indicated by comparing RETURN with OLD.
142 */
143#ifdef CONFIG_RMW_INSNS
144#define __HAVE_ARCH_CMPXCHG	1
145
146static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
147				      unsigned long new, int size)
148{
149	switch (size) {
150	case 1:
151		__asm__ __volatile__ ("casb %0,%2,%1"
152				      : "=d" (old), "=m" (*(char *)p)
153				      : "d" (new), "0" (old), "m" (*(char *)p));
154		break;
155	case 2:
156		__asm__ __volatile__ ("casw %0,%2,%1"
157				      : "=d" (old), "=m" (*(short *)p)
158				      : "d" (new), "0" (old), "m" (*(short *)p));
159		break;
160	case 4:
161		__asm__ __volatile__ ("casl %0,%2,%1"
162				      : "=d" (old), "=m" (*(int *)p)
163				      : "d" (new), "0" (old), "m" (*(int *)p));
164		break;
165	}
166	return old;
167}
168
169#define cmpxchg(ptr, o, n)						    \
170	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	    \
171			(unsigned long)(n), sizeof(*(ptr))))
172#define cmpxchg_local(ptr, o, n)					    \
173	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	    \
174			(unsigned long)(n), sizeof(*(ptr))))
175#else
176
177/*
178 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
179 * them available.
180 */
181#define cmpxchg_local(ptr, o, n)				  	       \
182	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
183			(unsigned long)(n), sizeof(*(ptr))))
184
185#include <asm-generic/cmpxchg.h>
186
187#endif
188
189#define arch_align_stack(x) (x)
190
191#endif /* __KERNEL__ */
192
193#endif /* _M68K_SYSTEM_H */